OV - exec - Loop 694

	Loop Id: 694	Module: exec	Source: BsplineFunctor.h:305-336 [...]	Coverage: 0.01%

0x436224 PUNPKLO	P5.H, P4.B

0x436228 PUNPKHI	P6.H, P4.B

0x43622c LD1D	{Z27.D}, P5/Z, [X12, X1,LSL #3]    [32]

0x436230 LD1D	{Z25.D}, P6/Z, [X3, X1,LSL #3]    [6]

0x436234 FMUL	Z15.D, Z19.D, Z27.D

0x436238 FMUL	Z31.D, Z19.D, Z25.D

0x43623c MOVPRFX	Z17, Z15

0x436240 FCVTZS	Z17.S, P7/M, Z15.D

0x436244 MOVPRFX	Z18, Z31

0x436248 FCVTZS	Z18.S, P7/M, Z31.D

0x43624c MOVPRFX	Z20, Z15

0x436250 FRINTZ	Z20.D, P7/M, Z15.D

0x436254 UZP1	Z21.S, Z17.S, Z18.S

0x436258 FSUB	Z30.D, Z15.D, Z20.D

0x43625c MOVPRFX	Z22, Z21

0x436260 ADD	Z22.S, Z22.S, #1

0x436264 MOVPRFX	Z28, Z3

0x436268 FMLA	Z28.D, P7/M, Z2.D, Z30.D

0x43626c MOVPRFX	Z29, Z21

0x436270 ADD	Z29.S, Z29.S, #3

0x436274 SUNPKHI	Z23.D, Z22

0x436278 SUNPKLO	Z24.D, Z22

0x43627c SUNPKLO	Z16.D, Z21

0x436280 LD1D	{Z13.D}, P5/Z, [X11, Z24.D,LSL #3]    [48]

0x436284 SUNPKLO	Z22.D, Z29

0x436288 FMUL	Z12.D, Z28.D, Z13.D

0x43628c SUNPKHI	Z29.D, Z29

0x436290 MOVPRFX	Z28, Z21

0x436294 ADD	Z28.S, Z28.S, #2

0x436298 ADDVL	X2, SP, #21

0x43629c LD1D	{Z14.D}, P5/Z, [X11, Z16.D,LSL #3]    [3]

0x4362a0 LD1D	{Z17.D}, P6/Z, [X11, Z23.D,LSL #3]    [46]

0x4362a4 LD1D	{Z15.D}, P5/Z, [X11, Z22.D,LSL #3]    [41]

0x4362a8 LD1D	{Z23.D}, P6/Z, [X11, Z29.D,LSL #3]    [13]

0x4362ac SUNPKHI	Z16.D, Z21

0x4362b0 SUNPKHI	Z29.D, Z28

0x4362b4 SUNPKLO	Z21.D, Z28

0x4362b8 ADD	X2, X2, #160

0x4362bc LDR	Z20, [X2, MUL VL]    [19]

0x4362c0 LD1D	{Z22.D}, P5/Z, [X11, Z21.D,LSL #3]    [39]

0x4362c4 MOVPRFX	Z26, Z1

0x4362c8 FMLA	Z26.D, P7/M, Z0.D, Z30.D

0x4362cc ORR	Z18.D, Z20.D, Z20.D

0x4362d0 FMAD	Z26.D, P7/M, Z14.D, Z12.D

0x4362d4 FMLA	Z18.D, P7/M, Z6.D, Z30.D

0x4362d8 MOVPRFX	Z12, Z5

0x4362dc FMLA	Z12.D, P7/M, Z4.D, Z30.D

0x4362e0 FMUL	Z24.D, Z18.D, Z15.D

0x4362e4 ADDVL	X7, SP, #24

0x4362e8 FMAD	Z12.D, P7/M, Z22.D, Z24.D

0x4362ec FADD	Z28.D, Z12.D, Z26.D

0x4362f0 LD1D	{Z24.D}, P6/Z, [X11, Z29.D,LSL #3]    [12]

0x4362f4 ADD	X7, X7, #160

0x4362f8 LDR	Z12, [X7, MUL VL]    [5]

0x4362fc MOVPRFX	Z29, Z31

0x436300 FRINTZ	Z29.D, P7/M, Z31.D

0x436304 FMUL	Z21.D, Z28.D, Z12.D

0x436308 FSUB	Z31.D, Z31.D, Z29.D

0x43630c FMLA	Z20.D, P7/M, Z6.D, Z31.D

0x436310 FMUL	Z28.D, Z20.D, Z23.D

0x436314 LD1D	{Z18.D}, P6/Z, [X11, Z16.D,LSL #3]    [2]

0x436318 LD1W	{Z26.S}, P4/Z, [X13, X1,LSL #2]    [35]

0x43631c MOVPRFX	Z29, Z5

0x436320 FMLA	Z29.D, P7/M, Z4.D, Z31.D

0x436324 SUNPKLO	Z16.D, Z26

0x436328 FMAD	Z29.D, P7/M, Z24.D, Z28.D

0x43632c ST1D	{Z21.D}, P5, [X18, Z16.D,LSL #3]    [27]

0x436330 MOVPRFX	Z28, Z1

0x436334 FMLA	Z28.D, P7/M, Z0.D, Z31.D

0x436338 MOVPRFX	Z21, Z3

0x43633c FMLA	Z21.D, P7/M, Z2.D, Z31.D

0x436340 FMUL	Z20.D, Z21.D, Z17.D

0x436344 FMAD	Z28.D, P7/M, Z18.D, Z20.D

0x436348 FADD	Z29.D, Z29.D, Z28.D

0x43634c FMUL	Z12.D, Z29.D, Z12.D

0x436350 ADD	X9, SP, #160

0x436354 SUNPKHI	Z26.D, Z26

0x436358 FDUP	Z21.D, #112

0x43635c ST1D	{Z12.D}, P6, [X18, Z26.D,LSL #3]    [30]

0x436360 LDR	Z12, [X9, #4, MUL VL]    [38]

0x436364 LDR	Z20, [X9, #1, MUL VL]    [38]

0x436368 FDIVR	Z27.D, P7/M, Z27.D, Z21.D

0x43636c LDR	Z21, [X9, #3, MUL VL]    [38]

0x436370 FMLA	Z21.D, P7/M, Z12.D, Z30.D

0x436374 LDR	Z12, [X9, #5, MUL VL]    [38]

0x436378 LDR	Z29, [X9, MUL VL]    [38]

0x43637c FMUL	Z28.D, Z30.D, Z30.D

0x436380 FMLA	Z29.D, P7/M, Z20.D, Z30.D

0x436384 FMLA	Z21.D, P7/M, Z12.D, Z28.D

0x436388 LDR	Z20, [X9, #2, MUL VL]    [38]

0x43638c LDR	Z12, [X9, #7, MUL VL]    [38]

0x436390 FMLA	Z29.D, P7/M, Z20.D, Z28.D

0x436394 ADDVL	X0, SP, #10

0x436398 FMUL	Z29.D, Z29.D, Z15.D

0x43639c LDR	Z20, [X9, #6, MUL VL]    [38]

0x4363a0 FMAD	Z21.D, P7/M, Z22.D, Z29.D

0x4363a4 FMLA	Z20.D, P7/M, Z12.D, Z30.D

0x4363a8 INCB	X9, ALL, MUL #8

0x4363ac LDR	Z29, [X9, MUL VL]    [10]

0x4363b0 ADD	X0, X0, #160

0x4363b4 LDR	Z12, [X0, MUL VL]    [22]

0x4363b8 ADDVL	X10, SP, #9

0x4363bc ADDVL	X26, SP, #11

0x4363c0 FMLA	Z20.D, P7/M, Z29.D, Z28.D

0x4363c4 ADD	X10, X10, #160

0x4363c8 LDR	Z29, [X10, MUL VL]    [37]

0x4363cc FMUL	Z20.D, Z20.D, Z13.D

0x4363d0 FMLA	Z29.D, P7/M, Z12.D, Z30.D

0x4363d4 ADD	X26, X26, #160

0x4363d8 LDR	Z12, [X26, MUL VL]    [23]

0x4363dc FMUL	Z27.D, Z27.D, Z19.D

0x4363e0 FMLA	Z29.D, P7/M, Z12.D, Z28.D

0x4363e4 FMAD	Z29.D, P7/M, Z14.D, Z20.D

0x4363e8 FADD	Z21.D, Z29.D, Z21.D

0x4363ec FMUL	Z27.D, Z21.D, Z27.D

0x4363f0 ADD	X16, SP, #160

0x4363f4 ST1D	{Z27.D}, P5, [X30, Z16.D,LSL #3]    [26]

0x4363f8 FDUP	Z29.D, #112

0x4363fc LDR	Z27, [X16, #4, MUL VL]    [8]

0x436400 LDR	Z20, [X16, #1, MUL VL]    [8]

0x436404 LDR	Z12, [X16, MUL VL]    [8]

0x436408 LDR	Z21, [X16, #3, MUL VL]    [8]

0x43640c FMLA	Z12.D, P7/M, Z20.D, Z31.D

0x436410 FMLA	Z21.D, P7/M, Z27.D, Z31.D

0x436414 LDR	Z20, [X16, #2, MUL VL]    [8]

0x436418 FDIVR	Z25.D, P7/M, Z25.D, Z29.D

0x43641c LDR	Z27, [X16, #5, MUL VL]    [8]

0x436420 FMUL	Z29.D, Z31.D, Z31.D

0x436424 FMLA	Z12.D, P7/M, Z20.D, Z29.D

0x436428 FMLA	Z21.D, P7/M, Z27.D, Z29.D

0x43642c ADDVL	X2, SP, #10

0x436430 FMUL	Z27.D, Z12.D, Z23.D

0x436434 LDR	Z12, [X16, #7, MUL VL]    [8]

0x436438 LDR	Z20, [X16, #6, MUL VL]    [8]

0x43643c FMAD	Z21.D, P7/M, Z24.D, Z27.D

0x436440 FMLA	Z20.D, P7/M, Z12.D, Z31.D

0x436444 INCB	X16, ALL, MUL #8

0x436448 LDR	Z27, [X16, MUL VL]    [36]

0x43644c ADD	X2, X2, #160

0x436450 LDR	Z12, [X2, MUL VL]    [7]

0x436454 FMLA	Z20.D, P7/M, Z27.D, Z29.D

0x436458 ADDVL	X17, SP, #9

0x43645c FMUL	Z20.D, Z20.D, Z17.D

0x436460 ADDVL	X7, SP, #11

0x436464 ADDVL	X0, SP, #17

0x436468 ADD	X17, X17, #160

0x43646c LDR	Z27, [X17, MUL VL]    [44]

0x436470 ADD	X7, X7, #160

0x436474 FMLA	Z27.D, P7/M, Z12.D, Z31.D

0x436478 LDR	Z12, [X7, MUL VL]    [9]

0x43647c ADD	X0, X0, #160

0x436480 FMLA	Z27.D, P7/M, Z12.D, Z29.D

0x436484 ADDVL	X9, SP, #22

0x436488 FMAD	Z27.D, P7/M, Z18.D, Z20.D

0x43648c ADDVL	X10, SP, #18

0x436490 FADD	Z21.D, Z27.D, Z21.D

0x436494 ADDVL	X26, SP, #16

0x436498 FMUL	Z25.D, Z25.D, Z19.D

0x43649c FMUL	Z25.D, Z21.D, Z25.D

0x4364a0 ST1D	{Z25.D}, P6, [X30, Z26.D,LSL #3]    [29]

0x4364a4 LDR	Z20, [X0, MUL VL]    [49]

0x4364a8 ADD	X9, X9, #160

0x4364ac ADD	X10, X10, #160

0x4364b0 LDR	Z27, [X10, MUL VL]    [24]

0x4364b4 ADD	X26, X26, #160

0x4364b8 FMLA	Z27.D, P7/M, Z30.D, Z20.D

0x4364bc LDR	Z20, [X26, MUL VL]    [14]

0x4364c0 ADDVL	X16, SP, #13

0x4364c4 ADDVL	X17, SP, #12

0x4364c8 ADDVL	X7, SP, #14

0x4364cc LDR	Z12, [X9, MUL VL]    [28]

0x4364d0 FMUL	Z21.D, Z28.D, Z30.D

0x4364d4 FMUL	Z25.D, Z28.D, Z12.D

0x4364d8 ADD	X16, X16, #160

0x4364dc FMLA	Z25.D, P7/M, Z21.D, Z20.D

0x4364e0 LDR	Z20, [X16, MUL VL]    [15]

0x4364e4 ADD	X17, X17, #160

0x4364e8 ADD	X7, X7, #160

0x4364ec FMUL	Z20.D, Z28.D, Z20.D

0x4364f0 FADD	Z25.D, Z27.D, Z25.D

0x4364f4 LDR	Z27, [X17, MUL VL]    [45]

0x4364f8 FMUL	Z25.D, Z25.D, Z13.D

0x4364fc LDR	Z13, [X7, MUL VL]    [16]

0x436500 FMLA	Z20.D, P7/M, Z21.D, Z27.D

0x436504 ADDVL	X2, SP, #15

0x436508 ADDVL	X9, SP, #23

0x43650c ADDVL	X10, SP, #19

0x436510 ADDVL	X0, SP, #20

0x436514 ADDVL	X26, SP, #18

0x436518 ADD	X2, X2, #160

0x43651c LDR	Z27, [X2, MUL VL]    [34]

0x436520 ADD	X9, X9, #160

0x436524 FMLA	Z27.D, P7/M, Z30.D, Z13.D

0x436528 ADD	X10, X10, #160

0x43652c ADD	X0, X0, #160

0x436530 ADD	X26, X26, #160

0x436534 FMUL	Z13.D, Z28.D, Z9.D

0x436538 FADD	Z27.D, Z27.D, Z20.D

0x43653c LDR	Z20, [X10, MUL VL]    [11]

0x436540 FMAD	Z27.D, P7/M, Z14.D, Z25.D

0x436544 LDR	Z14, [X9, MUL VL]    [21]

0x436548 MOVPRFX	Z25, Z11

0x43654c FMLA	Z25.D, P7/M, Z30.D, Z10.D

0x436550 FMUL	Z28.D, Z28.D, Z14.D

0x436554 FMLA	Z13.D, P7/M, Z21.D, Z8.D

0x436558 ADDVL	X16, SP, #17

0x43655c FMAD	Z21.D, P7/M, Z20.D, Z28.D

0x436560 ADDVL	X17, SP, #16

0x436564 LDR	Z28, [X0, MUL VL]    [47]

0x436568 FADD	Z13.D, Z25.D, Z13.D

0x43656c FMAD	Z30.D, P7/M, Z28.D, Z7.D

0x436570 FMUL	Z15.D, Z13.D, Z15.D

0x436574 FADD	Z30.D, Z30.D, Z21.D

0x436578 ADD	X16, X16, #160

0x43657c FMAD	Z22.D, P7/M, Z30.D, Z15.D

0x436580 FMUL	Z21.D, Z29.D, Z12.D

0x436584 FADD	Z22.D, Z27.D, Z22.D

0x436588 ADD	X17, X17, #160

0x43658c ST1D	{Z22.D}, P5, [X25, Z16.D,LSL #3]    [17]

0x436590 LDR	Z12, [X26, MUL VL]    [4]

0x436594 LDR	Z27, [X16, MUL VL]    [40]

0x436598 LDR	Z25, [X17, MUL VL]    [33]

0x43659c FMUL	Z16.D, Z29.D, Z31.D

0x4365a0 FMLA	Z12.D, P7/M, Z31.D, Z27.D

0x4365a4 FMLA	Z21.D, P7/M, Z16.D, Z25.D

0x4365a8 ADDVL	X2, SP, #13

0x4365ac ADDVL	X7, SP, #12

0x4365b0 FADD	Z13.D, Z12.D, Z21.D

0x4365b4 ADDVL	X9, SP, #15

0x4365b8 ADDVL	X10, SP, #14

0x4365bc FMUL	Z21.D, Z29.D, Z9.D

0x4365c0 ADDVL	X0, SP, #19

0x4365c4 ADDVL	X26, SP, #20

0x4365c8 FMLA	Z21.D, P7/M, Z16.D, Z8.D

0x4365cc ADD	X2, X2, #160

0x4365d0 LDR	Z20, [X2, MUL VL]    [31]

0x4365d4 ADD	X7, X7, #160

0x4365d8 LDR	Z28, [X7, MUL VL]    [42]

0x4365dc FMUL	Z15.D, Z29.D, Z20.D

0x4365e0 ADD	X9, X9, #160

0x4365e4 LDR	Z30, [X9, MUL VL]    [25]

0x4365e8 FMLA	Z15.D, P7/M, Z16.D, Z28.D

0x4365ec ADD	X10, X10, #160

0x4365f0 LDR	Z22, [X10, MUL VL]    [1]

0x4365f4 ADD	X0, X0, #160

0x4365f8 FMLA	Z30.D, P7/M, Z31.D, Z22.D

0x4365fc ADD	X26, X26, #160

0x436600 LDR	Z25, [X26, MUL VL]    [43]

0x436604 FMUL	Z17.D, Z17.D, Z13.D

0x436608 FADD	Z12.D, Z30.D, Z15.D

0x43660c FMAD	Z12.D, P7/M, Z18.D, Z17.D

0x436610 FMUL	Z18.D, Z29.D, Z14.D

0x436614 LDR	Z14, [X0, MUL VL]    [18]

0x436618 MOVPRFX	Z29, Z11

0x43661c FMLA	Z29.D, P7/M, Z31.D, Z10.D

0x436620 FMAD	Z16.D, P7/M, Z14.D, Z18.D

0x436624 FADD	Z27.D, Z21.D, Z29.D

0x436628 FMAD	Z31.D, P7/M, Z25.D, Z7.D

0x43662c FMUL	Z23.D, Z23.D, Z27.D

0x436630 FADD	Z31.D, Z31.D, Z16.D

0x436634 FMAD	Z24.D, P7/M, Z31.D, Z23.D

0x436638 FADD	Z24.D, Z12.D, Z24.D

0x43663c ST1D	{Z24.D}, P6, [X25, Z26.D,LSL #3]    [20]

0x436640 ADD	X1, X1, X4

0x436644 WHILELO	P4.S, W1, W8

0x436648 B.NE	436224

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:305-336,stl_vector.h:1147-1147
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.00
CQA cycles if no scalar integer	69.00
CQA cycles if FP arith vectorized	69.00
CQA cycles if fully vectorized	68.03
Front-end cycles	33.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	10.50
P2 cycles	10.25
P3 cycles	33.00
P4 cycles	10.25
P5 cycles	69.00
P6 cycles	69.00
P7 cycles	50.00
P8 cycles	50.00
P9 cycles	31.50
P10 cycles	31.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	266.00
Nb uops	266.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.93
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.22
Bytes prefetched	0.00
Bytes loaded	1824.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	86.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.86
Vector-efficiency ratio all	98.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.46

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:305-336,stl_vector.h:1147-1147
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.00
CQA cycles if no scalar integer	69.00
CQA cycles if FP arith vectorized	69.00
CQA cycles if fully vectorized	68.03
Front-end cycles	33.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	10.50
P2 cycles	10.25
P3 cycles	33.00
P4 cycles	10.25
P5 cycles	69.00
P6 cycles	69.00
P7 cycles	50.00
P8 cycles	50.00
P9 cycles	31.50
P10 cycles	31.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	266.00
Nb uops	266.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.93
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.22
Bytes prefetched	0.00
Bytes loaded	1824.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	86.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.86
Vector-efficiency ratio all	98.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.46

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 69.00 to 68.03 cycles (1.01x speedup).

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1824 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	266
loop length	1064
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	3.00	3.00	31.50	31.50	0.00	0.00	0.00
cycles	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	50.00	50.00	31.50	31.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.25
Data deps.	1.00
Overall L1	69.00

Vectorization ratios

INT

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.00 cycles. At this rate:

27% of peak load performance is reached (26.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436224

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUNPKLO P5.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
PUNPKHI P6.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z27.D}, P5/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P6/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z19.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z31.D, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z17, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z17.S, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z18.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z20, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z20.D, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
UZP1 Z21.S, Z17.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z15.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.S, Z22.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z2.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z29, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z29.S, Z29.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z23.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z24.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P5/Z, [X11, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z22.D, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z12.D, Z28.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SUNPKHI Z29.D, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.S, Z28.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X2, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z14.D}, P5/Z, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P6/Z, [X11, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z15.D}, P5/Z, [X11, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P6/Z, [X11, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKHI Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z29.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z21.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P5/Z, [X11, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z26, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P7/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ORR Z18.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z26.D, P7/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z18.D, P7/M, Z6.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z12, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z12.D, P7/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z24.D, Z18.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X7, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z12.D, P7/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z28.D, Z12.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P6/Z, [X11, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z29.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z21.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z31.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z20.D, P7/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z28.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z18.D}, P6/Z, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1W {Z26.S}, P4/Z, [X13, X1,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z4.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKLO Z16.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z29.D, P7/M, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z21.D}, P5, [X18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z28, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z0.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z21, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z21.D, P7/M, Z2.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z20.D, Z21.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z28.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z12.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X9, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUNPKHI Z26.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z12.D}, P6, [X18, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z12, [X9, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIVR Z27.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
LDR Z21, [X9, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z21.D, P7/M, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X9, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z29, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z29.D, P7/M, Z20.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X9, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X9, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P7/M, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X0, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z29.D, Z29.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z20, [X9, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z21.D, P7/M, Z22.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X9, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z29, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X10, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z20.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z29, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z20.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z29.D, P7/M, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z29.D, P7/M, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z29.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z21.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X16, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z27.D}, P5, [X30, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FDUP Z29.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z27, [X16, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X16, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z20.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z27.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X16, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIVR Z25.D, P7/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
LDR Z27, [X16, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z12.D, P7/M, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X2, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z27.D, Z12.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z12, [X16, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X16, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z21.D, P7/M, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X16, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z27, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X17, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z20.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X7, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X0, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z27, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z12.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z27.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X10, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z21.D, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X26, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z25.D, Z25.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z25.D, Z21.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z25.D}, P6, [X30, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z27, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X17, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X7, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z21.D, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z25.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z25.D, P7/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z20.D, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z25.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z27, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z25.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z13, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X2, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X10, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X0, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z27, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z13.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z27.D, Z27.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z20, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z27.D, P7/M, Z14.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z14, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P7/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z28.D, Z28.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z13.D, P7/M, Z21.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X16, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z21.D, P7/M, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X17, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z28, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z13.D, Z25.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z30.D, P7/M, Z28.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z15.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z22.D, P7/M, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z21.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z22.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z22.D}, P5, [X25, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z12, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z27, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z25, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z12.D, P7/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z16.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X2, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X7, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z13.D, Z12.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X9, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X10, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z21.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X0, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z21.D, P7/M, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z28, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z29.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z30, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z15.D, P7/M, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z22, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z30.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z25, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z12.D, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z12.D, P7/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z18.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z14, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P7/M, Z14.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z27.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z31.D, P7/M, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z31.D, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z24.D, P7/M, Z31.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z24.D, Z12.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P6, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P4.S, W1, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 436224 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1824 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	266
loop length	1064
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	3.00	3.00	31.50	31.50	0.00	0.00	0.00
cycles	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	50.00	50.00	31.50	31.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.25
Data deps.	1.00
Overall L1	69.00

Vectorization ratios

INT

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.00 cycles. At this rate:

27% of peak load performance is reached (26.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436224

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUNPKLO P5.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
PUNPKHI P6.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z27.D}, P5/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P6/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z19.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z31.D, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z17, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z17.S, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z18.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z20, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z20.D, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
UZP1 Z21.S, Z17.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z15.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.S, Z22.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z2.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z29, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z29.S, Z29.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z23.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z24.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P5/Z, [X11, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z22.D, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z12.D, Z28.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SUNPKHI Z29.D, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.S, Z28.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X2, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z14.D}, P5/Z, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P6/Z, [X11, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z15.D}, P5/Z, [X11, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P6/Z, [X11, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKHI Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z29.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z21.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P5/Z, [X11, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z26, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P7/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ORR Z18.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z26.D, P7/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z18.D, P7/M, Z6.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z12, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z12.D, P7/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z24.D, Z18.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X7, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z12.D, P7/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z28.D, Z12.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P6/Z, [X11, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z29.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z21.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z31.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z20.D, P7/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z28.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z18.D}, P6/Z, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1W {Z26.S}, P4/Z, [X13, X1,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z4.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKLO Z16.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z29.D, P7/M, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z21.D}, P5, [X18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z28, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z0.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z21, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z21.D, P7/M, Z2.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z20.D, Z21.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z28.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z12.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X9, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUNPKHI Z26.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z12.D}, P6, [X18, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z12, [X9, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIVR Z27.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
LDR Z21, [X9, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z21.D, P7/M, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X9, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z29, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z29.D, P7/M, Z20.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X9, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X9, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P7/M, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X0, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z29.D, Z29.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z20, [X9, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z21.D, P7/M, Z22.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X9, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z29, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X10, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z20.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z29, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z20.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z29.D, P7/M, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z29.D, P7/M, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z29.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z21.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X16, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z27.D}, P5, [X30, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FDUP Z29.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z27, [X16, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X16, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z20.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z27.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X16, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIVR Z25.D, P7/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
LDR Z27, [X16, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z12.D, P7/M, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X2, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z27.D, Z12.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z12, [X16, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X16, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z21.D, P7/M, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X16, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z27, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X17, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z20.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X7, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X0, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z27, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z12.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z27.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X10, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z21.D, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X26, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z25.D, Z25.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z25.D, Z21.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z25.D}, P6, [X30, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z27, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X17, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X7, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z21.D, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z25.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z25.D, P7/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z20.D, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z25.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z27, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z25.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z13, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X2, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X10, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X0, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z27, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z27.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z13.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z27.D, Z27.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z20, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z27.D, P7/M, Z14.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z14, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P7/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z28.D, Z28.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z13.D, P7/M, Z21.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X16, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z21.D, P7/M, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X17, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z28, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z13.D, Z25.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z30.D, P7/M, Z28.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z15.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z22.D, P7/M, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z21.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z22.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z22.D}, P5, [X25, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z12, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z27, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z25, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z12.D, P7/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z21.D, P7/M, Z16.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X2, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X7, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z13.D, Z12.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X9, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X10, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z21.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X0, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z21.D, P7/M, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z28, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z29.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z30, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z15.D, P7/M, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z22, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z30.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z25, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z12.D, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z12.D, P7/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z18.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z14, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P7/M, Z14.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z27.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z31.D, P7/M, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z31.D, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z24.D, P7/M, Z31.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z24.D, Z12.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P6, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P4.S, W1, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 436224 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code