OV - exec - Loop 684

	Loop Id: 684	Module: exec	Source: BsplineFunctor.h:276-336 [...]	Coverage: 0.01%

  (682) 0x435d80 LDR	X17, [X14, X5,LSL #3]

  (682) 0x435d84 LDR	W18, [X6, X5,LSL #2]

  (682) 0x435d88 ADD	X5, X5, #1

  (682) 0x435d8c LDR	W8, [X6, X5,LSL #2]

  (682) 0x435d90 LDR	D19, [X17, #568]

  (682) 0x435d94 CMP	W8, W20

  (682) 0x435d98 CSEL	W9, W8, W20, #13

  (682) 0x435d9c SUB	W10, W9, W18

  (682) 0x435da0 FMUL	D12, D19, D19

  (682) 0x435da4 CMP	W10, #0

  (682) 0x435da8 B.LE	43664c

0x435dac SBFM	X30, X10, #0, #31

0x435db0 SBFM	X25, X18, #61, #31

0x435db4 LDR	D31, [X17, #8]

0x435db8 ANDS	X11, X30, #4224

0x435dbc ADD	X26, X21, X25

0x435dc0 MOVZ	X0, #0

0x435dc4 MOVZ	W8, #0

0x435dc8 B.EQ	435f1c

  (683) 0x435f1c LDR	D6, [X26, X0,LSL #3]

  (683) 0x435f20 FCMPE	D31, D6

  (683) 0x435f24 B.LS	435f44

  (683) 0x435f28 ADD	W11, W18, W0

  (683) 0x435f2c CMP	W19, W11

  (683) 0x435f30 B.EQ	435f44

  (683) 0x435f34 ORR	W16, WZR, W8

  (683) 0x435f38 ADD	W8, W8, #1

  (683) 0x435f3c STR	W0, [X13, X16,LSL #2]

  (683) 0x435f40 STR	D6, [X12, X16,LSL #3]

  (683) 0x435f44 ADD	X0, X0, #1

  (683) 0x435f48 LDR	D7, [X26, X0,LSL #3]

  (683) 0x435f4c FCMPE	D31, D7

  (683) 0x435f50 B.LS	435f70

  (683) 0x435f54 ADD	W1, W18, W0

  (683) 0x435f58 CMP	W19, W1

  (683) 0x435f5c B.EQ	435f70

  (683) 0x435f60 ORR	W2, WZR, W8

  (683) 0x435f64 ADD	W8, W8, #1

  (683) 0x435f68 STR	W0, [X13, X2,LSL #2]

  (683) 0x435f6c STR	D7, [X12, X2,LSL #3]

  (683) 0x435f70 ADD	X7, X0, #1

  (683) 0x435f74 LDR	D8, [X26, X7,LSL #3]

  (683) 0x435f78 FCMPE	D31, D8

  (683) 0x435f7c B.LS	435f9c

  (683) 0x435f80 ADD	W9, W18, W7

  (683) 0x435f84 CMP	W19, W9

  (683) 0x435f88 B.EQ	435f9c

  (683) 0x435f8c ORR	W10, WZR, W8

  (683) 0x435f90 ADD	W8, W8, #1

  (683) 0x435f94 STR	W7, [X13, X10,LSL #2]

  (683) 0x435f98 STR	D8, [X12, X10,LSL #3]

  (683) 0x435f9c ADD	X11, X0, #2

  (683) 0x435fa0 LDR	D9, [X26, X11,LSL #3]

  (683) 0x435fa4 FCMPE	D31, D9

  (683) 0x435fa8 B.LS	435fc8

  (683) 0x435fac ADD	W16, W18, W11

  (683) 0x435fb0 CMP	W19, W16

  (683) 0x435fb4 B.EQ	435fc8

  (683) 0x435fb8 ORR	W1, WZR, W8

  (683) 0x435fbc ADD	W8, W8, #1

  (683) 0x435fc0 STR	W11, [X13, X1,LSL #2]

  (683) 0x435fc4 STR	D9, [X12, X1,LSL #3]

  (683) 0x435fc8 ADD	X2, X0, #3

  (683) 0x435fcc LDR	D10, [X26, X2,LSL #3]

  (683) 0x435fd0 FCMPE	D31, D10

  (683) 0x435fd4 B.LS	435ff4

  (683) 0x435fd8 ADD	W7, W18, W2

  (683) 0x435fdc CMP	W19, W7

  (683) 0x435fe0 B.EQ	435ff4

  (683) 0x435fe4 ORR	W9, WZR, W8

  (683) 0x435fe8 ADD	W8, W8, #1

  (683) 0x435fec STR	W2, [X13, X9,LSL #2]

  (683) 0x435ff0 STR	D10, [X12, X9,LSL #3]

  (683) 0x435ff4 ADD	X10, X0, #4

  (683) 0x435ff8 LDR	D11, [X26, X10,LSL #3]

  (683) 0x435ffc FCMPE	D31, D11

  (683) 0x436000 B.LS	436020

  (683) 0x436004 ADD	W11, W18, W10

  (683) 0x436008 CMP	W19, W11

  (683) 0x43600c B.EQ	436020

  (683) 0x436010 ORR	W16, WZR, W8

  (683) 0x436014 ADD	W8, W8, #1

  (683) 0x436018 STR	W10, [X13, X16,LSL #2]

  (683) 0x43601c STR	D11, [X12, X16,LSL #3]

  (683) 0x436020 ADD	X1, X0, #5

  (683) 0x436024 LDR	D13, [X26, X1,LSL #3]

  (683) 0x436028 FCMPE	D31, D13

  (683) 0x43602c B.LS	43604c

  (683) 0x436030 ADD	W2, W18, W1

  (683) 0x436034 CMP	W19, W2

  (683) 0x436038 B.EQ	43604c

  (683) 0x43603c ORR	W7, WZR, W8

  (683) 0x436040 ADD	W8, W8, #1

  (683) 0x436044 STR	W1, [X13, X7,LSL #2]

  (683) 0x436048 STR	D13, [X12, X7,LSL #3]

  (683) 0x43604c ADD	X9, X0, #6

  (683) 0x436050 LDR	D14, [X26, X9,LSL #3]

  (683) 0x436054 FCMPE	D31, D14

  (683) 0x436058 B.LS	436078

  (683) 0x43605c ADD	W10, W18, W9

  (683) 0x436060 CMP	W19, W10

  (683) 0x436064 B.EQ	436078

  (683) 0x436068 ORR	W11, WZR, W8

  (683) 0x43606c ADD	W8, W8, #1

  (683) 0x436070 STR	W9, [X13, X11,LSL #2]

  (683) 0x436074 STR	D14, [X12, X11,LSL #3]

  (683) 0x436078 ADD	X0, X0, #7

  (683) 0x43607c CMP	X30, X0

  (683) 0x436080 B.NE	435f1c

0x436084 CBZ	W8, 43664c

0x436088 ADDVL	X26, SP, #21

0x43608c ADDVL	X16, SP, #11

0x436090 LDR	X11, [X17, #536]

0x436094 ADD	X10, SP, #160

0x436098 ADD	X26, X26, #160

0x43609c LD1RD	{Z16.D}, P7/Z, [X17, #50]

0x4360a0 ADD	X16, X16, #160

0x4360a4 ADDVL	X2, SP, #10

0x4360a8 LD1RD	{Z17.D}, P7/Z, [X17, #20]

0x4360ac ADDVL	X7, SP, #9

0x4360b0 ADDVL	X9, SP, #8

0x4360b4 LD1RD	{Z18.D}, P7/Z, [X17, #21]

0x4360b8 LD1RD	{Z20.D}, P7/Z, [X17, #22]

0x4360bc LD1RD	{Z21.D}, P7/Z, [X17, #24]

0x4360c0 LD1RD	{Z22.D}, P7/Z, [X17, #25]

0x4360c4 LD1RD	{Z23.D}, P7/Z, [X17, #26]

0x4360c8 LD1RD	{Z24.D}, P7/Z, [X17, #28]

0x4360cc LD1RD	{Z25.D}, P7/Z, [X17, #29]

0x4360d0 LD1RD	{Z26.D}, P7/Z, [X17, #30]

0x4360d4 LD1RD	{Z27.D}, P7/Z, [X17, #32]

0x4360d8 LD1RD	{Z28.D}, P7/Z, [X17, #33]

0x4360dc ADD	X2, X2, #160

0x4360e0 ADD	X7, X7, #160

0x4360e4 LD1RD	{Z0.D}, P7/Z, [X17, #37]

0x4360e8 ADD	X9, X9, #160

0x4360ec LD1RD	{Z1.D}, P7/Z, [X17, #38]

0x4360f0 LD1RD	{Z2.D}, P7/Z, [X17, #41]

0x4360f4 LD1RD	{Z3.D}, P7/Z, [X17, #42]

0x4360f8 LD1RD	{Z4.D}, P7/Z, [X17, #45]

0x4360fc LD1RD	{Z5.D}, P7/Z, [X17, #46]

0x436100 LD1RD	{Z6.D}, P7/Z, [X17, #49]

0x436104 STR	Z22, [X10, #7, MUL VL]

0x436108 STR	Z23, [X10, #6, MUL VL]

0x43610c STR	Z24, [X10, #5, MUL VL]

0x436110 STR	Z25, [X10, #4, MUL VL]

0x436114 STR	Z26, [X10, #3, MUL VL]

0x436118 STR	Z27, [X10, #2, MUL VL]

0x43611c STR	Z28, [X10, #1, MUL VL]

0x436120 ADDVL	X0, SP, #13

0x436124 STR	Z16, [X26, MUL VL]

0x436128 ADDVL	X26, SP, #14

0x43612c STR	Z17, [X16, MUL VL]

0x436130 ADDVL	X16, SP, #15

0x436134 STR	Z18, [X2, MUL VL]

0x436138 STR	Z20, [X7, MUL VL]

0x43613c STR	Z21, [X9, MUL VL]

0x436140 LD1RD	{Z29.D}, P7/Z, [X17, #34]

0x436144 STR	Z29, [X10, MUL VL]

0x436148 INCB	X10, ALL, MUL #12

0x43614c LD1RD	{Z7.D}, P7/Z, [X17, #6]

0x436150 LD1RD	{Z8.D}, P7/Z, [X17, #7]

0x436154 LD1RD	{Z9.D}, P7/Z, [X17, #8]

0x436158 LD1RD	{Z10.D}, P7/Z, [X17, #9]

0x43615c LD1RD	{Z11.D}, P7/Z, [X17, #10]

0x436160 ADD	X0, X0, #160

0x436164 ADD	X26, X26, #160

0x436168 DUP	Z15.D, Z12.D[0]

0x43616c ADD	X16, X16, #160

0x436170 LD1RD	{Z12.D}, P7/Z, [X17, #3]

0x436174 ADD	X18, X24, X25

0x436178 ADD	X30, X23, X25

0x43617c ADDVL	X2, SP, #16

0x436180 STR	Z12, [X10, MUL VL]

0x436184 ADDVL	X7, SP, #22

0x436188 ADDVL	X9, SP, #17

0x43618c LD1RD	{Z31.D}, P7/Z, [X17, #4]

0x436190 ADDVL	X10, SP, #18

0x436194 MOVZ	X1, #0

0x436198 LD1RD	{Z30.D}, P7/Z, [X17, #5]

0x43619c ADD	X25, X22, X25

0x4361a0 LD1RD	{Z13.D}, P7/Z, [X17, #11]

0x4361a4 LD1RD	{Z14.D}, P7/Z, [X17, #12]

0x4361a8 LD1RD	{Z16.D}, P7/Z, [X17, #13]

0x4361ac ADD	X2, X2, #160

0x4361b0 ADD	X7, X7, #160

0x4361b4 ADD	X9, X9, #160

0x4361b8 ADD	X10, X10, #160

0x4361bc STR	Z7, [X16, MUL VL]

0x4361c0 LD1RD	{Z7.D}, P7/Z, [X17, #14]

0x4361c4 ADDVL	X16, SP, #20

0x4361c8 STR	Z31, [X0, MUL VL]

0x4361cc ADDVL	X0, SP, #19

0x4361d0 STR	Z30, [X26, MUL VL]

0x4361d4 ADDVL	X26, SP, #23

0x4361d8 STR	Z8, [X2, MUL VL]

0x4361dc LD1RD	{Z8.D}, P7/Z, [X17, #15]

0x4361e0 STR	Z9, [X7, MUL VL]

0x4361e4 LD1RD	{Z9.D}, P7/Z, [X17, #16]

0x4361e8 STR	Z10, [X9, MUL VL]

0x4361ec LD1RD	{Z10.D}, P7/Z, [X17, #17]

0x4361f0 STR	Z11, [X10, MUL VL]

0x4361f4 LD1RD	{Z11.D}, P7/Z, [X17, #18]

0x4361f8 ADDVL	X17, SP, #24

0x4361fc ADD	X0, X0, #160

0x436200 ADD	X26, X26, #160

0x436204 DUP	Z19.D, Z19.D[0]

0x436208 ADD	X16, X16, #160

0x43620c ADD	X17, X17, #160

0x436210 WHILELO	P4.S, WZR, W8

0x436214 STR	Z13, [X0, MUL VL]

0x436218 STR	Z14, [X26, MUL VL]

0x43621c STR	Z16, [X16, MUL VL]

0x436220 STR	Z15, [X17, MUL VL]

  (694) 0x436224 PUNPKLO	P5.H, P4.B

  (694) 0x436228 PUNPKHI	P6.H, P4.B

  (694) 0x43622c LD1D	{Z27.D}, P5/Z, [X12, X1,LSL #3]

  (694) 0x436230 LD1D	{Z25.D}, P6/Z, [X3, X1,LSL #3]

  (694) 0x436234 FMUL	Z15.D, Z19.D, Z27.D

  (694) 0x436238 FMUL	Z31.D, Z19.D, Z25.D

  (694) 0x43623c MOVPRFX	Z17, Z15

  (694) 0x436240 FCVTZS	Z17.S, P7/M, Z15.D

  (694) 0x436244 MOVPRFX	Z18, Z31

  (694) 0x436248 FCVTZS	Z18.S, P7/M, Z31.D

  (694) 0x43624c MOVPRFX	Z20, Z15

  (694) 0x436250 FRINTZ	Z20.D, P7/M, Z15.D

  (694) 0x436254 UZP1	Z21.S, Z17.S, Z18.S

  (694) 0x436258 FSUB	Z30.D, Z15.D, Z20.D

  (694) 0x43625c MOVPRFX	Z22, Z21

  (694) 0x436260 ADD	Z22.S, Z22.S, #1

  (694) 0x436264 MOVPRFX	Z28, Z3

  (694) 0x436268 FMLA	Z28.D, P7/M, Z2.D, Z30.D

  (694) 0x43626c MOVPRFX	Z29, Z21

  (694) 0x436270 ADD	Z29.S, Z29.S, #3

  (694) 0x436274 SUNPKHI	Z23.D, Z22

  (694) 0x436278 SUNPKLO	Z24.D, Z22

  (694) 0x43627c SUNPKLO	Z16.D, Z21

  (694) 0x436280 LD1D	{Z13.D}, P5/Z, [X11, Z24.D,LSL #3]

  (694) 0x436284 SUNPKLO	Z22.D, Z29

  (694) 0x436288 FMUL	Z12.D, Z28.D, Z13.D

  (694) 0x43628c SUNPKHI	Z29.D, Z29

  (694) 0x436290 MOVPRFX	Z28, Z21

  (694) 0x436294 ADD	Z28.S, Z28.S, #2

  (694) 0x436298 ADDVL	X2, SP, #21

  (694) 0x43629c LD1D	{Z14.D}, P5/Z, [X11, Z16.D,LSL #3]

  (694) 0x4362a0 LD1D	{Z17.D}, P6/Z, [X11, Z23.D,LSL #3]

  (694) 0x4362a4 LD1D	{Z15.D}, P5/Z, [X11, Z22.D,LSL #3]

  (694) 0x4362a8 LD1D	{Z23.D}, P6/Z, [X11, Z29.D,LSL #3]

  (694) 0x4362ac SUNPKHI	Z16.D, Z21

  (694) 0x4362b0 SUNPKHI	Z29.D, Z28

  (694) 0x4362b4 SUNPKLO	Z21.D, Z28

  (694) 0x4362b8 ADD	X2, X2, #160

  (694) 0x4362bc LDR	Z20, [X2, MUL VL]

  (694) 0x4362c0 LD1D	{Z22.D}, P5/Z, [X11, Z21.D,LSL #3]

  (694) 0x4362c4 MOVPRFX	Z26, Z1

  (694) 0x4362c8 FMLA	Z26.D, P7/M, Z0.D, Z30.D

  (694) 0x4362cc ORR	Z18.D, Z20.D, Z20.D

  (694) 0x4362d0 FMAD	Z26.D, P7/M, Z14.D, Z12.D

  (694) 0x4362d4 FMLA	Z18.D, P7/M, Z6.D, Z30.D

  (694) 0x4362d8 MOVPRFX	Z12, Z5

  (694) 0x4362dc FMLA	Z12.D, P7/M, Z4.D, Z30.D

  (694) 0x4362e0 FMUL	Z24.D, Z18.D, Z15.D

  (694) 0x4362e4 ADDVL	X7, SP, #24

  (694) 0x4362e8 FMAD	Z12.D, P7/M, Z22.D, Z24.D

  (694) 0x4362ec FADD	Z28.D, Z12.D, Z26.D

  (694) 0x4362f0 LD1D	{Z24.D}, P6/Z, [X11, Z29.D,LSL #3]

  (694) 0x4362f4 ADD	X7, X7, #160

  (694) 0x4362f8 LDR	Z12, [X7, MUL VL]

  (694) 0x4362fc MOVPRFX	Z29, Z31

  (694) 0x436300 FRINTZ	Z29.D, P7/M, Z31.D

  (694) 0x436304 FMUL	Z21.D, Z28.D, Z12.D

  (694) 0x436308 FSUB	Z31.D, Z31.D, Z29.D

  (694) 0x43630c FMLA	Z20.D, P7/M, Z6.D, Z31.D

  (694) 0x436310 FMUL	Z28.D, Z20.D, Z23.D

  (694) 0x436314 LD1D	{Z18.D}, P6/Z, [X11, Z16.D,LSL #3]

  (694) 0x436318 LD1W	{Z26.S}, P4/Z, [X13, X1,LSL #2]

  (694) 0x43631c MOVPRFX	Z29, Z5

  (694) 0x436320 FMLA	Z29.D, P7/M, Z4.D, Z31.D

  (694) 0x436324 SUNPKLO	Z16.D, Z26

  (694) 0x436328 FMAD	Z29.D, P7/M, Z24.D, Z28.D

  (694) 0x43632c ST1D	{Z21.D}, P5, [X18, Z16.D,LSL #3]

  (694) 0x436330 MOVPRFX	Z28, Z1

  (694) 0x436334 FMLA	Z28.D, P7/M, Z0.D, Z31.D

  (694) 0x436338 MOVPRFX	Z21, Z3

  (694) 0x43633c FMLA	Z21.D, P7/M, Z2.D, Z31.D

  (694) 0x436340 FMUL	Z20.D, Z21.D, Z17.D

  (694) 0x436344 FMAD	Z28.D, P7/M, Z18.D, Z20.D

  (694) 0x436348 FADD	Z29.D, Z29.D, Z28.D

  (694) 0x43634c FMUL	Z12.D, Z29.D, Z12.D

  (694) 0x436350 ADD	X9, SP, #160

  (694) 0x436354 SUNPKHI	Z26.D, Z26

  (694) 0x436358 FDUP	Z21.D, #112

  (694) 0x43635c ST1D	{Z12.D}, P6, [X18, Z26.D,LSL #3]

  (694) 0x436360 LDR	Z12, [X9, #4, MUL VL]

  (694) 0x436364 LDR	Z20, [X9, #1, MUL VL]

  (694) 0x436368 FDIVR	Z27.D, P7/M, Z27.D, Z21.D

  (694) 0x43636c LDR	Z21, [X9, #3, MUL VL]

  (694) 0x436370 FMLA	Z21.D, P7/M, Z12.D, Z30.D

  (694) 0x436374 LDR	Z12, [X9, #5, MUL VL]

  (694) 0x436378 LDR	Z29, [X9, MUL VL]

  (694) 0x43637c FMUL	Z28.D, Z30.D, Z30.D

  (694) 0x436380 FMLA	Z29.D, P7/M, Z20.D, Z30.D

  (694) 0x436384 FMLA	Z21.D, P7/M, Z12.D, Z28.D

  (694) 0x436388 LDR	Z20, [X9, #2, MUL VL]

  (694) 0x43638c LDR	Z12, [X9, #7, MUL VL]

  (694) 0x436390 FMLA	Z29.D, P7/M, Z20.D, Z28.D

  (694) 0x436394 ADDVL	X0, SP, #10

  (694) 0x436398 FMUL	Z29.D, Z29.D, Z15.D

  (694) 0x43639c LDR	Z20, [X9, #6, MUL VL]

  (694) 0x4363a0 FMAD	Z21.D, P7/M, Z22.D, Z29.D

  (694) 0x4363a4 FMLA	Z20.D, P7/M, Z12.D, Z30.D

  (694) 0x4363a8 INCB	X9, ALL, MUL #8

  (694) 0x4363ac LDR	Z29, [X9, MUL VL]

  (694) 0x4363b0 ADD	X0, X0, #160

  (694) 0x4363b4 LDR	Z12, [X0, MUL VL]

  (694) 0x4363b8 ADDVL	X10, SP, #9

  (694) 0x4363bc ADDVL	X26, SP, #11

  (694) 0x4363c0 FMLA	Z20.D, P7/M, Z29.D, Z28.D

  (694) 0x4363c4 ADD	X10, X10, #160

  (694) 0x4363c8 LDR	Z29, [X10, MUL VL]

  (694) 0x4363cc FMUL	Z20.D, Z20.D, Z13.D

  (694) 0x4363d0 FMLA	Z29.D, P7/M, Z12.D, Z30.D

  (694) 0x4363d4 ADD	X26, X26, #160

  (694) 0x4363d8 LDR	Z12, [X26, MUL VL]

  (694) 0x4363dc FMUL	Z27.D, Z27.D, Z19.D

  (694) 0x4363e0 FMLA	Z29.D, P7/M, Z12.D, Z28.D

  (694) 0x4363e4 FMAD	Z29.D, P7/M, Z14.D, Z20.D

  (694) 0x4363e8 FADD	Z21.D, Z29.D, Z21.D

  (694) 0x4363ec FMUL	Z27.D, Z21.D, Z27.D

  (694) 0x4363f0 ADD	X16, SP, #160

  (694) 0x4363f4 ST1D	{Z27.D}, P5, [X30, Z16.D,LSL #3]

  (694) 0x4363f8 FDUP	Z29.D, #112

  (694) 0x4363fc LDR	Z27, [X16, #4, MUL VL]

  (694) 0x436400 LDR	Z20, [X16, #1, MUL VL]

  (694) 0x436404 LDR	Z12, [X16, MUL VL]

  (694) 0x436408 LDR	Z21, [X16, #3, MUL VL]

  (694) 0x43640c FMLA	Z12.D, P7/M, Z20.D, Z31.D

  (694) 0x436410 FMLA	Z21.D, P7/M, Z27.D, Z31.D

  (694) 0x436414 LDR	Z20, [X16, #2, MUL VL]

  (694) 0x436418 FDIVR	Z25.D, P7/M, Z25.D, Z29.D

  (694) 0x43641c LDR	Z27, [X16, #5, MUL VL]

  (694) 0x436420 FMUL	Z29.D, Z31.D, Z31.D

  (694) 0x436424 FMLA	Z12.D, P7/M, Z20.D, Z29.D

  (694) 0x436428 FMLA	Z21.D, P7/M, Z27.D, Z29.D

  (694) 0x43642c ADDVL	X2, SP, #10

  (694) 0x436430 FMUL	Z27.D, Z12.D, Z23.D

  (694) 0x436434 LDR	Z12, [X16, #7, MUL VL]

  (694) 0x436438 LDR	Z20, [X16, #6, MUL VL]

  (694) 0x43643c FMAD	Z21.D, P7/M, Z24.D, Z27.D

  (694) 0x436440 FMLA	Z20.D, P7/M, Z12.D, Z31.D

  (694) 0x436444 INCB	X16, ALL, MUL #8

  (694) 0x436448 LDR	Z27, [X16, MUL VL]

  (694) 0x43644c ADD	X2, X2, #160

  (694) 0x436450 LDR	Z12, [X2, MUL VL]

  (694) 0x436454 FMLA	Z20.D, P7/M, Z27.D, Z29.D

  (694) 0x436458 ADDVL	X17, SP, #9

  (694) 0x43645c FMUL	Z20.D, Z20.D, Z17.D

  (694) 0x436460 ADDVL	X7, SP, #11

  (694) 0x436464 ADDVL	X0, SP, #17

  (694) 0x436468 ADD	X17, X17, #160

  (694) 0x43646c LDR	Z27, [X17, MUL VL]

  (694) 0x436470 ADD	X7, X7, #160

  (694) 0x436474 FMLA	Z27.D, P7/M, Z12.D, Z31.D

  (694) 0x436478 LDR	Z12, [X7, MUL VL]

  (694) 0x43647c ADD	X0, X0, #160

  (694) 0x436480 FMLA	Z27.D, P7/M, Z12.D, Z29.D

  (694) 0x436484 ADDVL	X9, SP, #22

  (694) 0x436488 FMAD	Z27.D, P7/M, Z18.D, Z20.D

  (694) 0x43648c ADDVL	X10, SP, #18

  (694) 0x436490 FADD	Z21.D, Z27.D, Z21.D

  (694) 0x436494 ADDVL	X26, SP, #16

  (694) 0x436498 FMUL	Z25.D, Z25.D, Z19.D

  (694) 0x43649c FMUL	Z25.D, Z21.D, Z25.D

  (694) 0x4364a0 ST1D	{Z25.D}, P6, [X30, Z26.D,LSL #3]

  (694) 0x4364a4 LDR	Z20, [X0, MUL VL]

  (694) 0x4364a8 ADD	X9, X9, #160

  (694) 0x4364ac ADD	X10, X10, #160

  (694) 0x4364b0 LDR	Z27, [X10, MUL VL]

  (694) 0x4364b4 ADD	X26, X26, #160

  (694) 0x4364b8 FMLA	Z27.D, P7/M, Z30.D, Z20.D

  (694) 0x4364bc LDR	Z20, [X26, MUL VL]

  (694) 0x4364c0 ADDVL	X16, SP, #13

  (694) 0x4364c4 ADDVL	X17, SP, #12

  (694) 0x4364c8 ADDVL	X7, SP, #14

  (694) 0x4364cc LDR	Z12, [X9, MUL VL]

  (694) 0x4364d0 FMUL	Z21.D, Z28.D, Z30.D

  (694) 0x4364d4 FMUL	Z25.D, Z28.D, Z12.D

  (694) 0x4364d8 ADD	X16, X16, #160

  (694) 0x4364dc FMLA	Z25.D, P7/M, Z21.D, Z20.D

  (694) 0x4364e0 LDR	Z20, [X16, MUL VL]

  (694) 0x4364e4 ADD	X17, X17, #160

  (694) 0x4364e8 ADD	X7, X7, #160

  (694) 0x4364ec FMUL	Z20.D, Z28.D, Z20.D

  (694) 0x4364f0 FADD	Z25.D, Z27.D, Z25.D

  (694) 0x4364f4 LDR	Z27, [X17, MUL VL]

  (694) 0x4364f8 FMUL	Z25.D, Z25.D, Z13.D

  (694) 0x4364fc LDR	Z13, [X7, MUL VL]

  (694) 0x436500 FMLA	Z20.D, P7/M, Z21.D, Z27.D

  (694) 0x436504 ADDVL	X2, SP, #15

  (694) 0x436508 ADDVL	X9, SP, #23

  (694) 0x43650c ADDVL	X10, SP, #19

  (694) 0x436510 ADDVL	X0, SP, #20

  (694) 0x436514 ADDVL	X26, SP, #18

  (694) 0x436518 ADD	X2, X2, #160

  (694) 0x43651c LDR	Z27, [X2, MUL VL]

  (694) 0x436520 ADD	X9, X9, #160

  (694) 0x436524 FMLA	Z27.D, P7/M, Z30.D, Z13.D

  (694) 0x436528 ADD	X10, X10, #160

  (694) 0x43652c ADD	X0, X0, #160

  (694) 0x436530 ADD	X26, X26, #160

  (694) 0x436534 FMUL	Z13.D, Z28.D, Z9.D

  (694) 0x436538 FADD	Z27.D, Z27.D, Z20.D

  (694) 0x43653c LDR	Z20, [X10, MUL VL]

  (694) 0x436540 FMAD	Z27.D, P7/M, Z14.D, Z25.D

  (694) 0x436544 LDR	Z14, [X9, MUL VL]

  (694) 0x436548 MOVPRFX	Z25, Z11

  (694) 0x43654c FMLA	Z25.D, P7/M, Z30.D, Z10.D

  (694) 0x436550 FMUL	Z28.D, Z28.D, Z14.D

  (694) 0x436554 FMLA	Z13.D, P7/M, Z21.D, Z8.D

  (694) 0x436558 ADDVL	X16, SP, #17

  (694) 0x43655c FMAD	Z21.D, P7/M, Z20.D, Z28.D

  (694) 0x436560 ADDVL	X17, SP, #16

  (694) 0x436564 LDR	Z28, [X0, MUL VL]

  (694) 0x436568 FADD	Z13.D, Z25.D, Z13.D

  (694) 0x43656c FMAD	Z30.D, P7/M, Z28.D, Z7.D

  (694) 0x436570 FMUL	Z15.D, Z13.D, Z15.D

  (694) 0x436574 FADD	Z30.D, Z30.D, Z21.D

  (694) 0x436578 ADD	X16, X16, #160

  (694) 0x43657c FMAD	Z22.D, P7/M, Z30.D, Z15.D

  (694) 0x436580 FMUL	Z21.D, Z29.D, Z12.D

  (694) 0x436584 FADD	Z22.D, Z27.D, Z22.D

  (694) 0x436588 ADD	X17, X17, #160

  (694) 0x43658c ST1D	{Z22.D}, P5, [X25, Z16.D,LSL #3]

  (694) 0x436590 LDR	Z12, [X26, MUL VL]

  (694) 0x436594 LDR	Z27, [X16, MUL VL]

  (694) 0x436598 LDR	Z25, [X17, MUL VL]

  (694) 0x43659c FMUL	Z16.D, Z29.D, Z31.D

  (694) 0x4365a0 FMLA	Z12.D, P7/M, Z31.D, Z27.D

  (694) 0x4365a4 FMLA	Z21.D, P7/M, Z16.D, Z25.D

  (694) 0x4365a8 ADDVL	X2, SP, #13

  (694) 0x4365ac ADDVL	X7, SP, #12

  (694) 0x4365b0 FADD	Z13.D, Z12.D, Z21.D

  (694) 0x4365b4 ADDVL	X9, SP, #15

  (694) 0x4365b8 ADDVL	X10, SP, #14

  (694) 0x4365bc FMUL	Z21.D, Z29.D, Z9.D

  (694) 0x4365c0 ADDVL	X0, SP, #19

  (694) 0x4365c4 ADDVL	X26, SP, #20

  (694) 0x4365c8 FMLA	Z21.D, P7/M, Z16.D, Z8.D

  (694) 0x4365cc ADD	X2, X2, #160

  (694) 0x4365d0 LDR	Z20, [X2, MUL VL]

  (694) 0x4365d4 ADD	X7, X7, #160

  (694) 0x4365d8 LDR	Z28, [X7, MUL VL]

  (694) 0x4365dc FMUL	Z15.D, Z29.D, Z20.D

  (694) 0x4365e0 ADD	X9, X9, #160

  (694) 0x4365e4 LDR	Z30, [X9, MUL VL]

  (694) 0x4365e8 FMLA	Z15.D, P7/M, Z16.D, Z28.D

  (694) 0x4365ec ADD	X10, X10, #160

  (694) 0x4365f0 LDR	Z22, [X10, MUL VL]

  (694) 0x4365f4 ADD	X0, X0, #160

  (694) 0x4365f8 FMLA	Z30.D, P7/M, Z31.D, Z22.D

  (694) 0x4365fc ADD	X26, X26, #160

  (694) 0x436600 LDR	Z25, [X26, MUL VL]

  (694) 0x436604 FMUL	Z17.D, Z17.D, Z13.D

  (694) 0x436608 FADD	Z12.D, Z30.D, Z15.D

  (694) 0x43660c FMAD	Z12.D, P7/M, Z18.D, Z17.D

  (694) 0x436610 FMUL	Z18.D, Z29.D, Z14.D

  (694) 0x436614 LDR	Z14, [X0, MUL VL]

  (694) 0x436618 MOVPRFX	Z29, Z11

  (694) 0x43661c FMLA	Z29.D, P7/M, Z31.D, Z10.D

  (694) 0x436620 FMAD	Z16.D, P7/M, Z14.D, Z18.D

  (694) 0x436624 FADD	Z27.D, Z21.D, Z29.D

  (694) 0x436628 FMAD	Z31.D, P7/M, Z25.D, Z7.D

  (694) 0x43662c FMUL	Z23.D, Z23.D, Z27.D

  (694) 0x436630 FADD	Z31.D, Z31.D, Z16.D

  (694) 0x436634 FMAD	Z24.D, P7/M, Z31.D, Z23.D

  (694) 0x436638 FADD	Z24.D, Z12.D, Z24.D

  (694) 0x43663c ST1D	{Z24.D}, P6, [X25, Z26.D,LSL #3]

  (694) 0x436640 ADD	X1, X1, X4

  (694) 0x436644 WHILELO	P4.S, W1, W8

  (694) 0x436648 B.NE	436224

  (682) 0x43664c CMP	X15, X5

  (682) 0x436650 B.NE	435d80

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 276 - 336

--------------------------------------------------------------------------------

276:   real_type dSquareDeltaRinv = DeltaRInv * DeltaRInv;

[...]

283:   int iCount                 = 0;

284:   int iLimit                 = iEnd - iStart;

[...]

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

[...]

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 269 - 271

--------------------------------------------------------------------------------

269:   for (int jg = 0; jg < NumGroups; ++jg)

270:   {

271:     const FuncType& f2(*F[igt + jg]);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.69
Bottlenecks	P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:283-283,BsplineFunctor.h:291-291,BsplineFunctor.h:294-294,BsplineFunctor.h:336-336
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.50
CQA cycles if no scalar integer	30.50
CQA cycles if FP arith vectorized	30.50
CQA cycles if fully vectorized	18.00
Front-end cycles	14.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	9.00
P2 cycles	9.00
P3 cycles	18.00
P4 cycles	9.00
P5 cycles	6.75
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	30.50
P10 cycles	30.50
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	25.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.20
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	800.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	39.13
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	54.35
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	62.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.69
Bottlenecks	P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:283-283,BsplineFunctor.h:291-291,BsplineFunctor.h:294-294,BsplineFunctor.h:336-336
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.50
CQA cycles if no scalar integer	30.50
CQA cycles if FP arith vectorized	30.50
CQA cycles if fully vectorized	18.00
Front-end cycles	14.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	9.00
P2 cycles	9.00
P3 cycles	18.00
P4 cycles	9.00
P5 cycles	6.75
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	30.50
P10 cycles	30.50
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	25.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.20
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	800.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	39.13
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	54.35
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	62.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:276-336
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:276,283-284,291-297,305-336
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:269-271
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

Analyzed code is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:283,291,294,336.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 54% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 30.50 to 18.00 cycles (1.69x speedup).

Details

39% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 304 bytes. The binary loop is storing 800 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	9.00	9.00	18.00	9.00	6.75	6.75	6.75	6.75	30.50	30.50	2.00	0.00	0.00
cycles	1.00	1.00	9.00	9.00	18.00	9.00	6.75	6.75	6.75	6.75	30.50	30.50	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Overall L1	30.50

Vectorization ratios

all	39%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

10% of peak load performance is reached (9.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
54% of peak store performance is reached (26.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436084

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SBFM X30, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X25, X18, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X17, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ANDS X11, X30, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X26, X21, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 435f1c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W8, 43664c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL X26, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X11, [X17, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X10, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z16.D}, P7/Z, [X17, #50]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADDVL X2, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z17.D}, P7/Z, [X17, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X7, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z18.D}, P7/Z, [X17, #21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z20.D}, P7/Z, [X17, #22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z21.D}, P7/Z, [X17, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z22.D}, P7/Z, [X17, #25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z23.D}, P7/Z, [X17, #26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z24.D}, P7/Z, [X17, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z25.D}, P7/Z, [X17, #29]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z26.D}, P7/Z, [X17, #30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z27.D}, P7/Z, [X17, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z28.D}, P7/Z, [X17, #33]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z0.D}, P7/Z, [X17, #37]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z1.D}, P7/Z, [X17, #38]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z2.D}, P7/Z, [X17, #41]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z3.D}, P7/Z, [X17, #42]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z4.D}, P7/Z, [X17, #45]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z5.D}, P7/Z, [X17, #46]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z6.D}, P7/Z, [X17, #49]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z22, [X10, #7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z23, [X10, #6, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z24, [X10, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z25, [X10, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z26, [X10, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z27, [X10, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z28, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X0, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z16, [X26, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X26, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z17, [X16, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X16, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z18, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z20, [X7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z21, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z29.D}, P7/Z, [X17, #34]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z29, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
INCB X10, ALL, MUL #12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z7.D}, P7/Z, [X17, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z8.D}, P7/Z, [X17, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z9.D}, P7/Z, [X17, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z10.D}, P7/Z, [X17, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z11.D}, P7/Z, [X17, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
DUP Z15.D, Z12.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z12.D}, P7/Z, [X17, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X18, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X30, X23, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADDVL X2, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z12, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X7, SP, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z31.D}, P7/Z, [X17, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X10, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z30.D}, P7/Z, [X17, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X25, X22, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z13.D}, P7/Z, [X17, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z14.D}, P7/Z, [X17, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z16.D}, P7/Z, [X17, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR Z7, [X16, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z7.D}, P7/Z, [X17, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X16, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X0, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z30, [X26, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X26, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z8, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z8.D}, P7/Z, [X17, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z9, [X7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z9.D}, P7/Z, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z10, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z10.D}, P7/Z, [X17, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z11, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z11.D}, P7/Z, [X17, #18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X17, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
DUP Z19.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
WHILELO P4.S, WZR, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2
STR Z13, [X0, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z14, [X26, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z15, [X17, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:276-336
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:276,283-284,291-297,305-336
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:269-271
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

Analyzed code is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:283,291,294,336.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

39% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 304 bytes. The binary loop is storing 800 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	9.00	9.00	18.00	9.00	6.75	6.75	6.75	6.75	30.50	30.50	2.00	0.00	0.00
cycles	1.00	1.00	9.00	9.00	18.00	9.00	6.75	6.75	6.75	6.75	30.50	30.50	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Overall L1	30.50

Vectorization ratios

all	39%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

10% of peak load performance is reached (9.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
54% of peak store performance is reached (26.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436084

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SBFM X30, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X25, X18, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X17, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ANDS X11, X30, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X26, X21, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 435f1c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W8, 43664c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL X26, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X11, [X17, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X10, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z16.D}, P7/Z, [X17, #50]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADDVL X2, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z17.D}, P7/Z, [X17, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X7, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z18.D}, P7/Z, [X17, #21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z20.D}, P7/Z, [X17, #22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z21.D}, P7/Z, [X17, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z22.D}, P7/Z, [X17, #25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z23.D}, P7/Z, [X17, #26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z24.D}, P7/Z, [X17, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z25.D}, P7/Z, [X17, #29]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z26.D}, P7/Z, [X17, #30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z27.D}, P7/Z, [X17, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z28.D}, P7/Z, [X17, #33]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z0.D}, P7/Z, [X17, #37]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z1.D}, P7/Z, [X17, #38]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z2.D}, P7/Z, [X17, #41]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z3.D}, P7/Z, [X17, #42]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z4.D}, P7/Z, [X17, #45]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z5.D}, P7/Z, [X17, #46]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z6.D}, P7/Z, [X17, #49]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z22, [X10, #7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z23, [X10, #6, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z24, [X10, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z25, [X10, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z26, [X10, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z27, [X10, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z28, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X0, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z16, [X26, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X26, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z17, [X16, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X16, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z18, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z20, [X7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z21, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z29.D}, P7/Z, [X17, #34]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z29, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
INCB X10, ALL, MUL #12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z7.D}, P7/Z, [X17, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z8.D}, P7/Z, [X17, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z9.D}, P7/Z, [X17, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z10.D}, P7/Z, [X17, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z11.D}, P7/Z, [X17, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
DUP Z15.D, Z12.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z12.D}, P7/Z, [X17, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X18, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X30, X23, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADDVL X2, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z12, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X7, SP, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1RD {Z31.D}, P7/Z, [X17, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X10, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z30.D}, P7/Z, [X17, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X25, X22, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1RD {Z13.D}, P7/Z, [X17, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z14.D}, P7/Z, [X17, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z16.D}, P7/Z, [X17, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD X2, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR Z7, [X16, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z7.D}, P7/Z, [X17, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X16, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X0, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z30, [X26, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
ADDVL X26, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR Z8, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z8.D}, P7/Z, [X17, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z9, [X7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z9.D}, P7/Z, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z10, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z10.D}, P7/Z, [X17, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
STR Z11, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1RD {Z11.D}, P7/Z, [X17, #18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADDVL X17, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
DUP Z19.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
WHILELO P4.S, WZR, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2
STR Z13, [X0, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z14, [X26, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
STR Z15, [X17, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50

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Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code