OV - exec - Loop 66

	Loop Id: 66	Module: exec	Source: NonLocalPP.hpp:126-135 [...]	Coverage: 0.08%

0x408168 ADD	X27, X27, #1

0x40816c CMP	X27, X6

0x408170 B.CS	408338

0x408174 LDR	X26, [X24, #24]

0x408178 ORR	W7, WZR, W27

0x40817c UBFM	X9, X7, #61, #60

0x408180 LDR	D2, [X28, #64]

0x408184 LDR	D29, [X26, X9]

0x408188 ADD	X10, X26, X9

0x40818c FCMPE	D29, D2

0x408190 B.GE	408168

0x408194 LDP	X15, X0, [X23, #40]

0x408198 ORR	X17, XZR, #3841

0x40819c MOVK	X17, #43691

0x4081a0 SUB	X6, X0, X15

0x4081a4 SBFM	X13, X6, #3, #63

0x4081a8 MADD	X30, X13, X17, XZR

0x4081ac CMP	W30, #0

0x4081b0 B.LE	4082e8

0x4081b4 LDR	X14, [SP, #208]

0x4081b8 SUB	W11, W30, #1

0x4081bc ORR	X2, XZR, X19

0x4081c0 ADD	X1, X11, #1

0x4081c4 LDR	X4, [X21, #64]

0x4081c8 ADD	X5, X1, X1,LSL #1

0x4081cc LDR	X1, [SP, #160]

0x4081d0 ADD	X16, X19, X5,LSL #3

0x4081d4 LDRSW	X8, [X14, #8]

0x4081d8 LDR	X17, [X14, #24]

0x4081dc ADD	X14, X4, X1

0x4081e0 LDR	X0, [SP, #400]

0x4081e4 ADD	X3, X8, X27

0x4081e8 ADD	X18, X8, X3

0x4081ec UBFM	X6, X3, #61, #60

0x4081f0 UBFM	X15, X18, #61, #60

0x4081f4 ADD	X13, X17, X6

0x4081f8 ADD	X30, X17, X15

0x4081fc ADD	X11, X17, X9

0x408200 TBNZ	W5, #0, 40829c

0x408204 LDR	X5, [SP, #160]

0x408208 ADD	X0, X0, #24

0x40820c LDR	D31, [X17, X9]

0x408210 LDR	D7, [X17, X6]

0x408214 LDR	D3, [X4, X5]

0x408218 LDP	D28, D22, [X14, #8]

0x40821c LDR	D24, [X17, X15]

0x408220 FADD	D12, D31, D3

0x408224 LDR	D16, [X19, #16]

0x408228 FADD	D20, D28, D7

0x40822c LDR	Q21, [X2], #24

0x408230 FADD	D30, D24, D22

0x408234 MOV	V12.D[1], V20.D[0]

0x408238 FMADD	D11, D16, D29, D30

0x40823c FMLA	V12.2D, V21.2D, V29.D[0]

0x408240 STUR	D11, [X0, #504]

0x408244 STUR	Q12, [X0, #488]

0x408248 LDR	D29, [X26, X9]

0x40824c B	40829c

  (67) 0x408250 LDR	D31, [X11]

  (67) 0x408254 ADD	X2, X2, #48

  (67) 0x408258 ADD	X0, X0, #48

  (67) 0x40825c LDR	D16, [X13]

  (67) 0x408260 LDP	D23, D2, [X14]

  (67) 0x408264 LDR	D28, [X30]

  (67) 0x408268 LDR	D25, [X14, #16]

  (67) 0x40826c FADD	D7, D31, D23

  (67) 0x408270 FADD	D3, D2, D16

  (67) 0x408274 LDUR	Q24, [X2, #488]

  (67) 0x408278 LDR	D12, [X10]

  (67) 0x40827c LDR	D26, [X9, #16]

  (67) 0x408280 FADD	D22, D28, D25

  (67) 0x408284 MOV	V7.D[1], V3.D[0]

  (67) 0x408288 FMADD	D20, D26, D12, D22

  (67) 0x40828c FMLA	V7.2D, V24.2D, V12.D[0]

  (67) 0x408290 STUR	Q7, [X0, #488]

  (67) 0x408294 STR	D20, [X26, #16]

  (67) 0x408298 LDR	D29, [X10]

  (67) 0x40829c ORR	X9, XZR, X2

  (67) 0x4082a0 ADD	X26, X0, #24

  (67) 0x4082a4 LDR	D0, [X11]

  (67) 0x4082a8 LDR	D4, [X13]

  (67) 0x4082ac LDP	D19, D1, [X14]

  (67) 0x4082b0 LDR	D5, [X30]

  (67) 0x4082b4 LDR	D10, [X14, #16]

  (67) 0x4082b8 FADD	D13, D0, D19

  (67) 0x4082bc FADD	D14, D1, D4

  (67) 0x4082c0 LDR	D6, [X2, #16]

  (67) 0x4082c4 LDR	Q18, [X9], #24

  (67) 0x4082c8 FADD	D17, D5, D10

  (67) 0x4082cc MOV	V13.D[1], V14.D[0]

  (67) 0x4082d0 FMADD	D27, D6, D29, D17

  (67) 0x4082d4 FMLA	V13.2D, V18.2D, V29.D[0]

  (67) 0x4082d8 STR	Q13, [X0]

  (67) 0x4082dc STR	D27, [X0, #16]

  (67) 0x4082e0 CMP	X9, X16

  (67) 0x4082e4 B.NE	408250

0x4082e8 LDR	X12, [X12, #24]

0x4082ec ORR	W5, WZR, W27

0x4082f0 MOVZ	W4, #1

0x4082f4 ADD	X3, SP, #400

0x4082f8 ORR	X1, XZR, X21

0x4082fc LDR	X10, [X23, #64]

0x408300 LDR	W2, [SP, #192]

0x408304 LDRSW	X7, [X12, X7,LSL #2]

0x408308 LDR	X26, [X10, X7,LSL #3]

0x40830c ORR	X0, XZR, X26

0x408310 BL	495540

0x408314 ADD	X2, SP, #432

0x408318 ORR	X1, XZR, X26

0x40831c ORR	X0, XZR, X22

0x408320 BL	40fd30

0x408324 LDR	X12, [X28, #5208]

0x408328 ADD	X27, X27, #1

0x40832c LDR	X6, [X12, #608]

0x408330 CMP	X27, X6

0x408334 B.CC	408174

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 126 - 135

--------------------------------------------------------------------------------

126:       for (int iat = 0; iat < ions_ref.getTotalNum(); ++iat)

127:       {

128:         //due to < Rmax condition, the actually iteration iat is [0,2] in a real simulation

129:         if (dist[iat] < Rmax)

130:         {

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

133:           auto& VP = *VPs[ions_ref.GroupID[iat]];

134:           VP.makeMoves(els, jel, virtualPos, true, iat);

135:           wf.evaluateRatios(VP, ratios);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 277 - 277

--------------------------------------------------------------------------------

277:   inline size_t getTotalNum() const { return TotalNum; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 992 - 1131

--------------------------------------------------------------------------------

992:       size() const _GLIBCXX_NOEXCEPT

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	1.46
CQA speedup if fully vectorized	5.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main._omp_fn.1
Source	unique_ptr.h:193-193,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,ParticleSet.h:277-277,VectorSoAContainer.h:231-231,OhmmsVector.h:229-229,OperatorTags.h:43-43,OperatorTags.h:63-63,TinyVector.h:145-145,stl_vector.h:993-993,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.75
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.92
Front-end cycles	9.75
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	2.25
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	78.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.92
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.03
Bytes prefetched	0.00
Bytes loaded	220.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	20.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.68
Vector-efficiency ratio load	30.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	37.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.50

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	1.46
CQA speedup if fully vectorized	5.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main._omp_fn.1
Source	unique_ptr.h:193-193,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,ParticleSet.h:277-277,VectorSoAContainer.h:231-231,OhmmsVector.h:229-229,OperatorTags.h:43-43,OperatorTags.h:63-63,TinyVector.h:145-145,stl_vector.h:993-993,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.75
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.92
Front-end cycles	9.75
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	2.25
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	78.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.92
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.03
Bytes prefetched	0.00
Bytes loaded	220.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	20.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.68
Vector-efficiency ratio load	30.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	37.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:992-993,1131

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.75 to 4.33 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.75 to 1.92 cycles (5.09x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
50% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.75 to 1.00 cycles (9.75x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 220 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	9.33	9.33	9.33	0.00	0.00
cycles	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.75
Overall L1	9.75

Vectorization ratios

INT

all	11%
load	20%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	20%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.75 cycles. At this rate:

23% of peak load performance is reached (22.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408174

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CS 408338 <main._omp_fn.1+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W7, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X9, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X28, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D29, [X26, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X26, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D29, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 408168 <main._omp_fn.1+0x107c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X15, X0, [X23, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ORR X17, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVK X17, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X6, X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X13, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X30, X13, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4082e8 <main._omp_fn.1+0x11fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W11, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X5, X1, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X19, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X14, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X3, X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X6, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X15, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X30, X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
TBNZ W5, #0, 40829c <main._omp_fn.1+0x11b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X17, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X17, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D28, D22, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D24, [X17, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D12, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D16, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D20, D28, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q21, [X2], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D30, D24, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOV V12.D[1], V20.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D11, D16, D29, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V12.2D, V21.2D, V29.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STUR D11, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STUR Q12, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D29, [X26, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 40829c <main._omp_fn.1+0x11b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X12, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W5, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X23, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR W2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDRSW X7, [X12, X7,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X26, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 495540 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40fd30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X28, #5208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [X12, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CC 408174 <main._omp_fn.1+0x1088>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	main._omp_fn.1
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:992-993,1131

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.75 to 4.33 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
50% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.75 to 1.00 cycles (9.75x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 220 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	9.33	9.33	9.33	0.00	0.00
cycles	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.75
Overall L1	9.75

Vectorization ratios

INT

all	11%
load	20%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	20%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.75 cycles. At this rate:

23% of peak load performance is reached (22.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408174

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CS 408338 <main._omp_fn.1+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W7, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X9, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X28, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D29, [X26, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X26, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D29, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 408168 <main._omp_fn.1+0x107c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X15, X0, [X23, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ORR X17, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVK X17, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X6, X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X13, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X30, X13, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4082e8 <main._omp_fn.1+0x11fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W11, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X5, X1, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X19, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X14, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X3, X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X6, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X15, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X30, X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
TBNZ W5, #0, 40829c <main._omp_fn.1+0x11b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X17, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X17, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D28, D22, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D24, [X17, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D12, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D16, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D20, D28, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q21, [X2], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D30, D24, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOV V12.D[1], V20.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D11, D16, D29, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V12.2D, V21.2D, V29.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STUR D11, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STUR Q12, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D29, [X26, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 40829c <main._omp_fn.1+0x11b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X12, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W5, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X23, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR W2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDRSW X7, [X12, X7,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X26, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 495540 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40fd30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X28, #5208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [X12, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CC 408174 <main._omp_fn.1+0x1088>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code