OV - exec - Loop 395

	Loop Id: 395	Module: exec	Source: BsplineFunctor.h:246-260 [...]	Coverage: 0.05%

0x41fe28 LD1D	{Z29.D}, P5/Z, [X6, X27,LSL #3]    [9]

0x41fe2c LD1D	{Z30.D}, P6/Z, [X4, X27,LSL #3]    [8]

0x41fe30 FMUL	Z31.D, Z3.D, Z29.D

0x41fe34 FMUL	Z13.D, Z3.D, Z30.D

0x41fe38 MOVPRFX	Z8, Z31

0x41fe3c FCVTZS	Z8.S, P7/M, Z31.D

0x41fe40 MOVPRFX	Z9, Z13

0x41fe44 FCVTZS	Z9.S, P7/M, Z13.D

0x41fe48 MOVPRFX	Z0, Z31

0x41fe4c FRINTZ	Z0.D, P7/M, Z31.D

0x41fe50 UZP1	Z30.S, Z9.S, Z8.S

0x41fe54 FSUB	Z31.D, Z31.D, Z0.D

0x41fe58 MOVPRFX	Z12, Z30

0x41fe5c ADD	Z12.S, Z12.S, #1

0x41fe60 FMUL	Z29.D, Z31.D, Z31.D

0x41fe64 SUNPKHI	Z8.D, Z12

0x41fe68 FMUL	Z14.D, Z29.D, Z31.D

0x41fe6c LD1D	{Z9.D}, P5/Z, [X16, Z8.D,LSL #3]    [5]

0x41fe70 FMUL	Z10.D, Z17.D, Z29.D

0x41fe74 FMLA	Z10.D, P7/M, Z16.D, Z14.D

0x41fe78 MOVPRFX	Z11, Z19

0x41fe7c FMLA	Z11.D, P7/M, Z18.D, Z31.D

0x41fe80 FADD	Z0.D, Z10.D, Z11.D

0x41fe84 FMUL	Z10.D, Z5.D, Z29.D

0x41fe88 FMUL	Z0.D, Z0.D, Z9.D

0x41fe8c FMLA	Z10.D, P7/M, Z4.D, Z14.D

0x41fe90 SUNPKHI	Z9.D, Z30

0x41fe94 LD1D	{Z8.D}, P5/Z, [X16, Z9.D,LSL #3]    [7]

0x41fe98 MOVPRFX	Z11, Z7

0x41fe9c FMLA	Z11.D, P7/M, Z6.D, Z31.D

0x41fea0 FADD	Z11.D, Z11.D, Z10.D

0x41fea4 FMUL	Z10.D, Z21.D, Z29.D

0x41fea8 FMAD	Z11.D, P7/M, Z8.D, Z0.D

0x41feac FMLA	Z10.D, P7/M, Z14.D, Z20.D

0x41feb0 MOVPRFX	Z0, Z23

0x41feb4 FMLA	Z0.D, P7/M, Z31.D, Z22.D

0x41feb8 FMUL	Z29.D, Z29.D, Z25.D

0x41febc FADD	Z8.D, Z10.D, Z0.D

0x41fec0 FMAD	Z14.D, P7/M, Z24.D, Z29.D

0x41fec4 MOVPRFX	Z10, Z30

0x41fec8 ADD	Z10.S, Z10.S, #2

0x41fecc FADD	Z1.D, P5/M, Z1.D, Z11.D

0x41fed0 FMAD	Z31.D, P7/M, Z26.D, Z27.D

0x41fed4 MOVPRFX	Z11, Z30

0x41fed8 ADD	Z11.S, Z11.S, #3

0x41fedc FADD	Z31.D, Z31.D, Z14.D

0x41fee0 SUNPKHI	Z0.D, Z11

0x41fee4 SUNPKHI	Z14.D, Z10

0x41fee8 LD1D	{Z29.D}, P5/Z, [X16, Z0.D,LSL #3]    [10]

0x41feec LD1D	{Z9.D}, P5/Z, [X16, Z14.D,LSL #3]    [6]

0x41fef0 SUNPKLO	Z30.D, Z30

0x41fef4 FMLA	Z1.D, P5/M, Z9.D, Z8.D

0x41fef8 SUNPKLO	Z8.D, Z10

0x41fefc FMLA	Z1.D, P5/M, Z29.D, Z31.D

0x41ff00 LD1D	{Z14.D}, P6/Z, [X16, Z8.D,LSL #3]    [4]

0x41ff04 SUNPKLO	Z31.D, Z11

0x41ff08 MOVPRFX	Z9, Z13

0x41ff0c FRINTZ	Z9.D, P7/M, Z13.D

0x41ff10 LD1D	{Z11.D}, P6/Z, [X16, Z30.D,LSL #3]    [1]

0x41ff14 FSUB	Z8.D, Z13.D, Z9.D

0x41ff18 SUNPKLO	Z12.D, Z12

0x41ff1c FMUL	Z29.D, Z8.D, Z8.D

0x41ff20 FMUL	Z30.D, Z29.D, Z8.D

0x41ff24 FMUL	Z13.D, Z17.D, Z29.D

0x41ff28 FMLA	Z13.D, P7/M, Z16.D, Z30.D

0x41ff2c LD1D	{Z10.D}, P6/Z, [X16, Z12.D,LSL #3]    [3]

0x41ff30 ADD	X27, X27, X7

0x41ff34 MOVPRFX	Z12, Z19

0x41ff38 FMLA	Z12.D, P7/M, Z18.D, Z8.D

0x41ff3c WHILELO	P5.D, W27, W15

0x41ff40 FADD	Z9.D, Z12.D, Z13.D

0x41ff44 MOVPRFX	Z13, Z7

0x41ff48 FMLA	Z13.D, P7/M, Z6.D, Z8.D

0x41ff4c LD1D	{Z0.D}, P6/Z, [X16, Z31.D,LSL #3]    [2]

0x41ff50 FMUL	Z12.D, Z9.D, Z10.D

0x41ff54 FMUL	Z31.D, Z5.D, Z29.D

0x41ff58 FMUL	Z10.D, Z21.D, Z29.D

0x41ff5c FMLA	Z31.D, P7/M, Z4.D, Z30.D

0x41ff60 MOVPRFX	Z9, Z23

0x41ff64 FMLA	Z9.D, P7/M, Z8.D, Z22.D

0x41ff68 FADD	Z31.D, Z13.D, Z31.D

0x41ff6c FMUL	Z29.D, Z29.D, Z25.D

0x41ff70 FMAD	Z31.D, P7/M, Z11.D, Z12.D

0x41ff74 FMAD	Z8.D, P7/M, Z26.D, Z27.D

0x41ff78 MOVPRFX	Z11, Z10

0x41ff7c FMLA	Z11.D, P7/M, Z30.D, Z20.D

0x41ff80 FADD	Z28.D, P6/M, Z28.D, Z31.D

0x41ff84 FMAD	Z30.D, P7/M, Z24.D, Z29.D

0x41ff88 FADD	Z13.D, Z9.D, Z11.D

0x41ff8c FMLA	Z28.D, P6/M, Z14.D, Z13.D

0x41ff90 FADD	Z14.D, Z30.D, Z8.D

0x41ff94 FMLA	Z28.D, P6/M, Z0.D, Z14.D

0x41ff98 WHILELO	P6.D, W27, W2

0x41ff9c B.NE	41fe28

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260,stl_vector.h:1147-1147
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	40.00
CQA cycles if FP arith vectorized	40.00
CQA cycles if fully vectorized	40.00
Front-end cycles	11.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	2.00
P4 cycles	0.25
P5 cycles	40.00
P6 cycles	40.00
P7 cycles	25.00
P8 cycles	25.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	48.00
Nb FLOP mul	64.00
Nb FLOP fma	88.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.56
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.52
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260,stl_vector.h:1147-1147
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	40.00
CQA cycles if FP arith vectorized	40.00
CQA cycles if fully vectorized	40.00
Front-end cycles	11.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	2.00
P4 cycles	0.25
P5 cycles	40.00
P6 cycles	40.00
P7 cycles	25.00
P8 cycles	25.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	48.00
Nb FLOP mul	64.00
Nb FLOP fma	88.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.56
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.52
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (88 inside FMA instructions)
152: multiply (88 inside FMA instructions)

The binary loop is loading 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	94
loop length	376
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	0.00	0.00	5.00	5.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	25.00	25.00	5.00	5.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	11.75
Data deps.	8.00
Overall L1	40.00

Vectorization ratios

INT

all	38%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fe28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z29.D}, P5/Z, [X6, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P6/Z, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z13.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FCVTZS Z8.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FCVTZS Z9.S, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FRINTZ Z0.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1
UZP1 Z30.S, Z9.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FSUB Z31.D, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z12.S, Z12.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
SUNPKHI Z8.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z14.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z9.D}, P5/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z10.D, P7/M, Z16.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z11, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z11.D, P7/M, Z18.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z0.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z10.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z0.D, Z0.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z10.D, P7/M, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
SUNPKHI Z9.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z8.D}, P5/Z, [X16, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z11.D, P7/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z11.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z11.D, P7/M, Z8.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z10.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z0, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z0.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADD Z8.D, Z10.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMAD Z14.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z10.S, Z10.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z1.D, P5/M, Z1.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMAD Z31.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z11, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z11.S, Z11.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z31.D, Z31.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SUNPKHI Z0.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SUNPKHI Z14.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z29.D}, P5/Z, [X16, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P5/Z, [X16, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z30.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z1.D, P5/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
SUNPKLO Z8.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z1.D, P5/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z14.D}, P6/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z31.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FRINTZ Z9.D, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1
LD1D {Z11.D}, P6/Z, [X16, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z8.D, Z13.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SUNPKLO Z12.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z29.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z30.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z13.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z13.D, P7/M, Z16.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z10.D}, P6/Z, [X16, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X27, X27, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVPRFX Z12, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z12.D, P7/M, Z18.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P5.D, W27, W15	1	0	0	0	0	1	0	0	0	0	0	3	2
FADD Z9.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z13, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z13.D, P7/M, Z6.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z0.D}, P6/Z, [X16, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z12.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z31.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z31.D, P7/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z9.D, P7/M, Z8.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z31.D, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z31.D, P7/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z8.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z11.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z28.D, P6/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMAD Z30.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z13.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z28.D, P6/M, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z14.D, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z28.D, P6/M, Z0.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P6.D, W27, W2	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 41fe28 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (88 inside FMA instructions)
152: multiply (88 inside FMA instructions)

The binary loop is loading 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	94
loop length	376
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	0.00	0.00	5.00	5.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	25.00	25.00	5.00	5.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	11.75
Data deps.	8.00
Overall L1	40.00

Vectorization ratios

INT

all	38%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fe28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z29.D}, P5/Z, [X6, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P6/Z, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z13.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FCVTZS Z8.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FCVTZS Z9.S, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FRINTZ Z0.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1
UZP1 Z30.S, Z9.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FSUB Z31.D, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z12.S, Z12.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
SUNPKHI Z8.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z14.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z9.D}, P5/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z10.D, P7/M, Z16.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z11, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z11.D, P7/M, Z18.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z0.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z10.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z0.D, Z0.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z10.D, P7/M, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
SUNPKHI Z9.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z8.D}, P5/Z, [X16, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z11.D, P7/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z11.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z11.D, P7/M, Z8.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z10.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z0, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z0.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADD Z8.D, Z10.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMAD Z14.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z10.S, Z10.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z1.D, P5/M, Z1.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMAD Z31.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z11, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z11.S, Z11.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z31.D, Z31.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SUNPKHI Z0.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SUNPKHI Z14.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z29.D}, P5/Z, [X16, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P5/Z, [X16, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z30.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z1.D, P5/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
SUNPKLO Z8.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z1.D, P5/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z14.D}, P6/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z31.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FRINTZ Z9.D, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1
LD1D {Z11.D}, P6/Z, [X16, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z8.D, Z13.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SUNPKLO Z12.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z29.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z30.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z13.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z13.D, P7/M, Z16.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z10.D}, P6/Z, [X16, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X27, X27, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVPRFX Z12, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z12.D, P7/M, Z18.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P5.D, W27, W15	1	0	0	0	0	1	0	0	0	0	0	3	2
FADD Z9.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z13, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z13.D, P7/M, Z6.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z0.D}, P6/Z, [X16, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z12.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z31.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z31.D, P7/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z9.D, P7/M, Z8.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z31.D, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z31.D, P7/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z8.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z11.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z28.D, P6/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMAD Z30.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z13.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z28.D, P6/M, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z14.D, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z28.D, P6/M, Z0.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P6.D, W27, W2	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 41fe28 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code