OV - exec - Loop 392

	Loop Id: 392	Module: exec	Source: TwoBodyJastrowRef.h:107-132 [...]	Coverage: 0.02%

0x41fac0 LDR	W24, [X19, #672]

0x41fac4 LDR	X3, [X23, #24]

0x41fac8 LDRB	W2, [X22, #8]

0x41facc SBFM	X27, X24, #0, #31

0x41fad0 LDR	D15, [X3, X27,LSL #3]

0x41fad4 TBZ	W2, #0, 420008

0x41fad8 ORR	X0, XZR, X19

0x41fadc LDR	X28, [X19, #656]

0x41fae0 LDR	W1, [X26, #584]

0x41fae4 BL	484780

0x41fae8 LDR	X5, [X0, #72]

0x41faec ADD	X4, X25, X25,LSL #2

0x41faf0 LDR	X7, [X28, #24]

0x41faf4 LDR	X13, [X26, #160]

0x41faf8 ADD	X6, X5, X4

0x41fafc LDR	X14, [X6, #24]

0x41fb00 LDR	W8, [X7, X27,LSL #2]

0x41fb04 MADD	W9, W8, W13, WZR

0x41fb08 CBZ	X13, 41ffb8

0x41fb0c LDR	X11, [X28, #616]

0x41fb10 MOVI	D2, #0

0x41fb14 MOVZ	X8, #0

0x41fb18 CNTW	X7, ALL

0x41fb1c PTRUE	P7.B, ALL

0x41fb20 LDR	X4, [X26, #464]

0x41fb24 LDR	X10, [X26, #512]

0x41fb28 ADD	X12, X10, W9,SXTW #3

0x41fb2c LDR	X11, [X11, #24]

0x41fb30 ADDVL	X6, X4, #1

0x41fb34 HINT	#0

0x41fb38 HINT	#0

0x41fb3c HINT	#0

  (393) 0x41fb40 LDR	X16, [X12, X8,LSL #3]

  (393) 0x41fb44 LDR	W17, [X11, X8,LSL #2]

  (393) 0x41fb48 ADD	X8, X8, #1

  (393) 0x41fb4c LDR	W18, [X11, X8,LSL #2]

  (393) 0x41fb50 CMP	W18, W17

  (393) 0x41fb54 B.LE	41ffac

  (393) 0x41fb58 SUB	W30, W18, W17

  (393) 0x41fb5c SBFM	X15, X17, #61, #31

  (393) 0x41fb60 LDR	D31, [X16, #8]

  (393) 0x41fb64 ANDS	W27, W30, #128

  (393) 0x41fb68 ADD	X0, X14, X15

  (393) 0x41fb6c MOVZ	W2, #0

  (393) 0x41fb70 ORR	W30, WZR, W17

  (393) 0x41fb74 B.EQ	41fcac

  (393) 0x41fb78 CMP	W27, #1

  (393) 0x41fb7c B.EQ	41fc80

  (393) 0x41fb80 CMP	W27, #2

  (393) 0x41fb84 B.EQ	41fc5c

  (393) 0x41fb88 CMP	W27, #3

  (393) 0x41fb8c B.EQ	41fc38

  (393) 0x41fb90 CMP	W27, #4

  (393) 0x41fb94 B.EQ	41fc14

  (393) 0x41fb98 CMP	W27, #5

  (393) 0x41fb9c B.EQ	41fbf0

  (393) 0x41fba0 CMP	W27, #6

  (393) 0x41fba4 B.EQ	41fbcc

  (393) 0x41fba8 LDR	D30, [X14, X15]

  (393) 0x41fbac FCMPE	D31, D30

  (393) 0x41fbb0 B.LS	41fbc4

  (393) 0x41fbb4 CMP	W24, W17

  (393) 0x41fbb8 B.EQ	41fbc4

  (393) 0x41fbbc MOVZ	W2, #1

  (393) 0x41fbc0 STR	D30, [X4]

  (393) 0x41fbc4 ADD	X0, X0, #8

  (393) 0x41fbc8 ADD	W30, W17, #1

  (393) 0x41fbcc LDR	D0, [X0]

  (393) 0x41fbd0 FCMPE	D31, D0

  (393) 0x41fbd4 B.LS	41fbe8

  (393) 0x41fbd8 CMP	W24, W30

  (393) 0x41fbdc B.EQ	41fbe8

  (393) 0x41fbe0 STR	D0, [X4, X2,UXTW #3]

  (393) 0x41fbe4 ADD	W2, W2, #1

  (393) 0x41fbe8 ADD	X0, X0, #8

  (393) 0x41fbec ADD	W30, W30, #1

  (393) 0x41fbf0 LDR	D1, [X0]

  (393) 0x41fbf4 FCMPE	D31, D1

  (393) 0x41fbf8 B.LS	41fc0c

  (393) 0x41fbfc CMP	W24, W30

  (393) 0x41fc00 B.EQ	41fc0c

  (393) 0x41fc04 STR	D1, [X4, X2,UXTW #3]

  (393) 0x41fc08 ADD	W2, W2, #1

  (393) 0x41fc0c ADD	X0, X0, #8

  (393) 0x41fc10 ADD	W30, W30, #1

  (393) 0x41fc14 LDR	D3, [X0]

  (393) 0x41fc18 FCMPE	D31, D3

  (393) 0x41fc1c B.LS	41fc30

  (393) 0x41fc20 CMP	W24, W30

  (393) 0x41fc24 B.EQ	41fc30

  (393) 0x41fc28 STR	D3, [X4, X2,UXTW #3]

  (393) 0x41fc2c ADD	W2, W2, #1

  (393) 0x41fc30 ADD	X0, X0, #8

  (393) 0x41fc34 ADD	W30, W30, #1

  (393) 0x41fc38 LDR	D4, [X0]

  (393) 0x41fc3c FCMPE	D31, D4

  (393) 0x41fc40 B.LS	41fc54

  (393) 0x41fc44 CMP	W24, W30

  (393) 0x41fc48 B.EQ	41fc54

  (393) 0x41fc4c STR	D4, [X4, X2,UXTW #3]

  (393) 0x41fc50 ADD	W2, W2, #1

  (393) 0x41fc54 ADD	X0, X0, #8

  (393) 0x41fc58 ADD	W30, W30, #1

  (393) 0x41fc5c LDR	D5, [X0]

  (393) 0x41fc60 FCMPE	D31, D5

  (393) 0x41fc64 B.LS	41fc78

  (393) 0x41fc68 CMP	W24, W30

  (393) 0x41fc6c B.EQ	41fc78

  (393) 0x41fc70 STR	D5, [X4, X2,UXTW #3]

  (393) 0x41fc74 ADD	W2, W2, #1

  (393) 0x41fc78 ADD	X0, X0, #8

  (393) 0x41fc7c ADD	W30, W30, #1

  (393) 0x41fc80 LDR	D6, [X0]

  (393) 0x41fc84 FCMPE	D31, D6

  (393) 0x41fc88 B.LS	41fc9c

  (393) 0x41fc8c CMP	W24, W30

  (393) 0x41fc90 B.EQ	41fc9c

  (393) 0x41fc94 STR	D6, [X4, X2,UXTW #3]

  (393) 0x41fc98 ADD	W2, W2, #1

  (393) 0x41fc9c ADD	W30, W30, #1

  (393) 0x41fca0 ADD	X0, X0, #8

  (393) 0x41fca4 CMP	W18, W30

  (393) 0x41fca8 B.EQ	41fdbc

    (394) 0x41fcac LDR	D7, [X0]

    (394) 0x41fcb0 FCMPE	D31, D7

    (394) 0x41fcb4 B.LS	41fcc8

    (394) 0x41fcb8 CMP	W24, W30

    (394) 0x41fcbc B.EQ	41fcc8

    (394) 0x41fcc0 STR	D7, [X4, X2,UXTW #3]

    (394) 0x41fcc4 ADD	W2, W2, #1

    (394) 0x41fcc8 LDR	D8, [X0, #8]

    (394) 0x41fccc ADD	W1, W30, #1

    (394) 0x41fcd0 ADD	X0, X0, #8

    (394) 0x41fcd4 FCMPE	D31, D8

    (394) 0x41fcd8 B.LS	41fcec

    (394) 0x41fcdc CMP	W24, W1

    (394) 0x41fce0 B.EQ	41fcec

    (394) 0x41fce4 STR	D8, [X4, X2,UXTW #3]

    (394) 0x41fce8 ADD	W2, W2, #1

    (394) 0x41fcec LDR	D9, [X0, #8]

    (394) 0x41fcf0 ADD	W3, W1, #1

    (394) 0x41fcf4 FCMPE	D31, D9

    (394) 0x41fcf8 B.LS	41fd0c

    (394) 0x41fcfc CMP	W24, W3

    (394) 0x41fd00 B.EQ	41fd0c

    (394) 0x41fd04 STR	D9, [X4, X2,UXTW #3]

    (394) 0x41fd08 ADD	W2, W2, #1

    (394) 0x41fd0c LDR	D10, [X0, #16]

    (394) 0x41fd10 ADD	W28, W1, #2

    (394) 0x41fd14 FCMPE	D31, D10

    (394) 0x41fd18 B.LS	41fd2c

    (394) 0x41fd1c CMP	W24, W28

    (394) 0x41fd20 B.EQ	41fd2c

    (394) 0x41fd24 STR	D10, [X4, X2,UXTW #3]

    (394) 0x41fd28 ADD	W2, W2, #1

    (394) 0x41fd2c LDR	D11, [X0, #24]

    (394) 0x41fd30 ADD	W5, W1, #3

    (394) 0x41fd34 FCMPE	D31, D11

    (394) 0x41fd38 B.LS	41fd4c

    (394) 0x41fd3c CMP	W24, W5

    (394) 0x41fd40 B.EQ	41fd4c

    (394) 0x41fd44 STR	D11, [X4, X2,UXTW #3]

    (394) 0x41fd48 ADD	W2, W2, #1

    (394) 0x41fd4c LDR	D12, [X0, #32]

    (394) 0x41fd50 ADD	W9, W1, #4

    (394) 0x41fd54 FCMPE	D31, D12

    (394) 0x41fd58 B.LS	41fd6c

    (394) 0x41fd5c CMP	W24, W9

    (394) 0x41fd60 B.EQ	41fd6c

    (394) 0x41fd64 STR	D12, [X4, X2,UXTW #3]

    (394) 0x41fd68 ADD	W2, W2, #1

    (394) 0x41fd6c LDR	D13, [X0, #40]

    (394) 0x41fd70 ADD	W10, W1, #5

    (394) 0x41fd74 FCMPE	D31, D13

    (394) 0x41fd78 B.LS	41fd8c

    (394) 0x41fd7c CMP	W24, W10

    (394) 0x41fd80 B.EQ	41fd8c

    (394) 0x41fd84 STR	D13, [X4, X2,UXTW #3]

    (394) 0x41fd88 ADD	W2, W2, #1

    (394) 0x41fd8c LDR	D14, [X0, #48]

    (394) 0x41fd90 ADD	W17, W1, #6

    (394) 0x41fd94 FCMPE	D31, D14

    (394) 0x41fd98 B.LS	41fdac

    (394) 0x41fd9c CMP	W24, W17

    (394) 0x41fda0 B.EQ	41fdac

    (394) 0x41fda4 STR	D14, [X4, X2,UXTW #3]

    (394) 0x41fda8 ADD	W2, W2, #1

    (394) 0x41fdac ADD	W30, W1, #7

    (394) 0x41fdb0 ADD	X0, X0, #56

    (394) 0x41fdb4 CMP	W18, W30

    (394) 0x41fdb8 B.NE	41fcac

  (393) 0x41fdbc CBZ	W2, 41ffac

  (393) 0x41fdc0 ADD	X18, X16, #568

  (393) 0x41fdc4 LD1RD	{Z4.D}, P7/Z, [X16, #3]

  (393) 0x41fdc8 LD1RD	{Z5.D}, P7/Z, [X16, #4]

  (393) 0x41fdcc LD1RD	{Z6.D}, P7/Z, [X16, #5]

  (393) 0x41fdd0 LD1RD	{Z7.D}, P7/Z, [X16, #6]

  (393) 0x41fdd4 LD1RD	{Z16.D}, P7/Z, [X16, #7]

  (393) 0x41fdd8 LD1RD	{Z17.D}, P7/Z, [X16, #8]

  (393) 0x41fddc LD1RD	{Z18.D}, P7/Z, [X16, #9]

  (393) 0x41fde0 LD1RD	{Z19.D}, P7/Z, [X16, #10]

  (393) 0x41fde4 LD1RD	{Z20.D}, P7/Z, [X16, #11]

  (393) 0x41fde8 LD1RD	{Z21.D}, P7/Z, [X16, #12]

  (393) 0x41fdec LD1RD	{Z22.D}, P7/Z, [X16, #13]

  (393) 0x41fdf0 LD1RD	{Z23.D}, P7/Z, [X16, #14]

  (393) 0x41fdf4 LD1RD	{Z24.D}, P7/Z, [X16, #15]

  (393) 0x41fdf8 LD1RD	{Z25.D}, P7/Z, [X16, #16]

  (393) 0x41fdfc LD1RD	{Z26.D}, P7/Z, [X16, #17]

  (393) 0x41fe00 LD1RD	{Z27.D}, P7/Z, [X16, #18]

  (393) 0x41fe04 LDR	X16, [X16, #536]

  (393) 0x41fe08 MOVZ	X27, #0

  (393) 0x41fe0c ORR	W15, WZR, W2

  (393) 0x41fe10 DUP	Z1.D, #0

  (393) 0x41fe14 UQDECD	W15, ALL

  (393) 0x41fe18 LD1RD	{Z3.D}, P7/Z, [X18]

  (393) 0x41fe1c WHILELO	P5.D, WZR, W15

  (393) 0x41fe20 ORR	Z28.D, Z1.D, Z1.D

  (393) 0x41fe24 WHILELO	P6.D, WZR, W2

    (395) 0x41fe28 LD1D	{Z29.D}, P5/Z, [X6, X27,LSL #3]

    (395) 0x41fe2c LD1D	{Z30.D}, P6/Z, [X4, X27,LSL #3]

    (395) 0x41fe30 FMUL	Z31.D, Z3.D, Z29.D

    (395) 0x41fe34 FMUL	Z13.D, Z3.D, Z30.D

    (395) 0x41fe38 MOVPRFX	Z8, Z31

    (395) 0x41fe3c FCVTZS	Z8.S, P7/M, Z31.D

    (395) 0x41fe40 MOVPRFX	Z9, Z13

    (395) 0x41fe44 FCVTZS	Z9.S, P7/M, Z13.D

    (395) 0x41fe48 MOVPRFX	Z0, Z31

    (395) 0x41fe4c FRINTZ	Z0.D, P7/M, Z31.D

    (395) 0x41fe50 UZP1	Z30.S, Z9.S, Z8.S

    (395) 0x41fe54 FSUB	Z31.D, Z31.D, Z0.D

    (395) 0x41fe58 MOVPRFX	Z12, Z30

    (395) 0x41fe5c ADD	Z12.S, Z12.S, #1

    (395) 0x41fe60 FMUL	Z29.D, Z31.D, Z31.D

    (395) 0x41fe64 SUNPKHI	Z8.D, Z12

    (395) 0x41fe68 FMUL	Z14.D, Z29.D, Z31.D

    (395) 0x41fe6c LD1D	{Z9.D}, P5/Z, [X16, Z8.D,LSL #3]

    (395) 0x41fe70 FMUL	Z10.D, Z17.D, Z29.D

    (395) 0x41fe74 FMLA	Z10.D, P7/M, Z16.D, Z14.D

    (395) 0x41fe78 MOVPRFX	Z11, Z19

    (395) 0x41fe7c FMLA	Z11.D, P7/M, Z18.D, Z31.D

    (395) 0x41fe80 FADD	Z0.D, Z10.D, Z11.D

    (395) 0x41fe84 FMUL	Z10.D, Z5.D, Z29.D

    (395) 0x41fe88 FMUL	Z0.D, Z0.D, Z9.D

    (395) 0x41fe8c FMLA	Z10.D, P7/M, Z4.D, Z14.D

    (395) 0x41fe90 SUNPKHI	Z9.D, Z30

    (395) 0x41fe94 LD1D	{Z8.D}, P5/Z, [X16, Z9.D,LSL #3]

    (395) 0x41fe98 MOVPRFX	Z11, Z7

    (395) 0x41fe9c FMLA	Z11.D, P7/M, Z6.D, Z31.D

    (395) 0x41fea0 FADD	Z11.D, Z11.D, Z10.D

    (395) 0x41fea4 FMUL	Z10.D, Z21.D, Z29.D

    (395) 0x41fea8 FMAD	Z11.D, P7/M, Z8.D, Z0.D

    (395) 0x41feac FMLA	Z10.D, P7/M, Z14.D, Z20.D

    (395) 0x41feb0 MOVPRFX	Z0, Z23

    (395) 0x41feb4 FMLA	Z0.D, P7/M, Z31.D, Z22.D

    (395) 0x41feb8 FMUL	Z29.D, Z29.D, Z25.D

    (395) 0x41febc FADD	Z8.D, Z10.D, Z0.D

    (395) 0x41fec0 FMAD	Z14.D, P7/M, Z24.D, Z29.D

    (395) 0x41fec4 MOVPRFX	Z10, Z30

    (395) 0x41fec8 ADD	Z10.S, Z10.S, #2

    (395) 0x41fecc FADD	Z1.D, P5/M, Z1.D, Z11.D

    (395) 0x41fed0 FMAD	Z31.D, P7/M, Z26.D, Z27.D

    (395) 0x41fed4 MOVPRFX	Z11, Z30

    (395) 0x41fed8 ADD	Z11.S, Z11.S, #3

    (395) 0x41fedc FADD	Z31.D, Z31.D, Z14.D

    (395) 0x41fee0 SUNPKHI	Z0.D, Z11

    (395) 0x41fee4 SUNPKHI	Z14.D, Z10

    (395) 0x41fee8 LD1D	{Z29.D}, P5/Z, [X16, Z0.D,LSL #3]

    (395) 0x41feec LD1D	{Z9.D}, P5/Z, [X16, Z14.D,LSL #3]

    (395) 0x41fef0 SUNPKLO	Z30.D, Z30

    (395) 0x41fef4 FMLA	Z1.D, P5/M, Z9.D, Z8.D

    (395) 0x41fef8 SUNPKLO	Z8.D, Z10

    (395) 0x41fefc FMLA	Z1.D, P5/M, Z29.D, Z31.D

    (395) 0x41ff00 LD1D	{Z14.D}, P6/Z, [X16, Z8.D,LSL #3]

    (395) 0x41ff04 SUNPKLO	Z31.D, Z11

    (395) 0x41ff08 MOVPRFX	Z9, Z13

    (395) 0x41ff0c FRINTZ	Z9.D, P7/M, Z13.D

    (395) 0x41ff10 LD1D	{Z11.D}, P6/Z, [X16, Z30.D,LSL #3]

    (395) 0x41ff14 FSUB	Z8.D, Z13.D, Z9.D

    (395) 0x41ff18 SUNPKLO	Z12.D, Z12

    (395) 0x41ff1c FMUL	Z29.D, Z8.D, Z8.D

    (395) 0x41ff20 FMUL	Z30.D, Z29.D, Z8.D

    (395) 0x41ff24 FMUL	Z13.D, Z17.D, Z29.D

    (395) 0x41ff28 FMLA	Z13.D, P7/M, Z16.D, Z30.D

    (395) 0x41ff2c LD1D	{Z10.D}, P6/Z, [X16, Z12.D,LSL #3]

    (395) 0x41ff30 ADD	X27, X27, X7

    (395) 0x41ff34 MOVPRFX	Z12, Z19

    (395) 0x41ff38 FMLA	Z12.D, P7/M, Z18.D, Z8.D

    (395) 0x41ff3c WHILELO	P5.D, W27, W15

    (395) 0x41ff40 FADD	Z9.D, Z12.D, Z13.D

    (395) 0x41ff44 MOVPRFX	Z13, Z7

    (395) 0x41ff48 FMLA	Z13.D, P7/M, Z6.D, Z8.D

    (395) 0x41ff4c LD1D	{Z0.D}, P6/Z, [X16, Z31.D,LSL #3]

    (395) 0x41ff50 FMUL	Z12.D, Z9.D, Z10.D

    (395) 0x41ff54 FMUL	Z31.D, Z5.D, Z29.D

    (395) 0x41ff58 FMUL	Z10.D, Z21.D, Z29.D

    (395) 0x41ff5c FMLA	Z31.D, P7/M, Z4.D, Z30.D

    (395) 0x41ff60 MOVPRFX	Z9, Z23

    (395) 0x41ff64 FMLA	Z9.D, P7/M, Z8.D, Z22.D

    (395) 0x41ff68 FADD	Z31.D, Z13.D, Z31.D

    (395) 0x41ff6c FMUL	Z29.D, Z29.D, Z25.D

    (395) 0x41ff70 FMAD	Z31.D, P7/M, Z11.D, Z12.D

    (395) 0x41ff74 FMAD	Z8.D, P7/M, Z26.D, Z27.D

    (395) 0x41ff78 MOVPRFX	Z11, Z10

    (395) 0x41ff7c FMLA	Z11.D, P7/M, Z30.D, Z20.D

    (395) 0x41ff80 FADD	Z28.D, P6/M, Z28.D, Z31.D

    (395) 0x41ff84 FMAD	Z30.D, P7/M, Z24.D, Z29.D

    (395) 0x41ff88 FADD	Z13.D, Z9.D, Z11.D

    (395) 0x41ff8c FMLA	Z28.D, P6/M, Z14.D, Z13.D

    (395) 0x41ff90 FADD	Z14.D, Z30.D, Z8.D

    (395) 0x41ff94 FMLA	Z28.D, P6/M, Z0.D, Z14.D

    (395) 0x41ff98 WHILELO	P6.D, W27, W2

    (395) 0x41ff9c B.NE	41fe28

  (393) 0x41ffa0 FADD	Z3.D, Z28.D, Z1.D

  (393) 0x41ffa4 FADDV	D1, P7, Z3.D

  (393) 0x41ffa8 FADD	D2, D2, D1

  (393) 0x41ffac CMP	X13, X8

  (393) 0x41ffb0 B.NE	41fb40

0x41ffb4 FSUB	D15, D15, S2

0x41ffb8 FMOV	D0, D15

0x41ffbc ADD	X20, X20, #1

0x41ffc0 BL	403a70

0x41ffc4 LDP	X1, X3, [X21]

0x41ffc8 SUB	X28, X3, X1

0x41ffcc STR	D0, [X1, X25]

0x41ffd0 ADD	X25, X25, #8

0x41ffd4 CMP	X20, X28,ASR #3

0x41ffd8 B.CC	41fac0

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 231 - 260

--------------------------------------------------------------------------------

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 107 - 132

--------------------------------------------------------------------------------

107:     for (int k = 0; k < ratios.size(); ++k)

108:       ratios[k] = std::exp(Uat[VP.refPtcl] - computeU(VP.getRefPS(), VP.refPtcl, VP.getDistTableAB(myTableID).getDistRow(k).data()));

[...]

125:     valT curUat(0);

126:     const int igt = P.GroupID[iat] * NumGroups;

127:     for (int jg = 0; jg < NumGroups; ++jg)

128:     {

129:       const FuncType& f2(*F[igt + jg]);

130:       int iStart = P.first(jg);

131:       int iEnd   = P.last(jg);

132:       curUat += f2.evaluateV(iat, iStart, iEnd, dist, DistCompressed.data());

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 1147

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/optional: 991 - 991

--------------------------------------------------------------------------------

991: 	if (this->_M_is_engaged())

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	5.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:231-231,BsplineFunctor.h:246-246,refwrap.h:347-347,TwoBodyJastrowRef.h:107-108,TwoBodyJastrowRef.h:125-127,OhmmsVector.h:223-223,OhmmsVector.h:249-249,stl_vector.h:993-993,optional:991-991
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	1.17
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	5.21
Front-end cycles	4.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	39.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.17
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.43
Bytes prefetched	0.00
Bytes loaded	117.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.81
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	5.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:231-231,BsplineFunctor.h:246-246,refwrap.h:347-347,TwoBodyJastrowRef.h:107-108,TwoBodyJastrowRef.h:125-127,OhmmsVector.h:223-223,OhmmsVector.h:249-249,stl_vector.h:993-993,optional:991-991
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	1.17
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	5.21
Front-end cycles	4.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	39.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.17
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.43
Bytes prefetched	0.00
Bytes loaded	117.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.81
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	TwoBodyJastrowRef.h:107-132
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107-108,125-132
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1147
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/optional:991

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 1.17 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.83 to 5.21 cycles (1.12x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 1.00 cycles (5.83x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 117 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.00	4.00	4.00	4.00	1.00	1.00	1.00	1.00	5.83	5.50	5.67	0.00	0.00
cycles	2.50	2.50	4.00	4.00	4.00	4.00	1.00	1.00	1.00	1.00	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

20% of peak load performance is reached (20.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W24, [X19, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRB W2, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X27, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D15, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
TBZ W2, #0, 420008 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X19, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X26, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 484780 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X25, X25,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X28, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X26, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X7, X27,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W9, W8, W13, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CBZ X13, 41ffb8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X28, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X4, [X26, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X26, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X10, W9,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X11, [X11, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDVL X6, X4, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
HINT #0
FSUB D15, D15, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D0, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X20, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a70 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X3, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X28, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X1, X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X25, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X28,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.CC 41fac0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	TwoBodyJastrowRef.h:107-132
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107-108,125-132
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1147
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/optional:991

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 1.17 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 1.00 cycles (5.83x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 117 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.00	4.00	4.00	4.00	1.00	1.00	1.00	1.00	5.83	5.50	5.67	0.00	0.00
cycles	2.50	2.50	4.00	4.00	4.00	4.00	1.00	1.00	1.00	1.00	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

20% of peak load performance is reached (20.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W24, [X19, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRB W2, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X27, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D15, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
TBZ W2, #0, 420008 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X19, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X26, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 484780 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X25, X25,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X28, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X26, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X7, X27,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W9, W8, W13, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CBZ X13, 41ffb8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X28, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X4, [X26, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X26, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X10, W9,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X11, [X11, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADDVL X6, X4, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
HINT #0
FSUB D15, D15, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D0, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X20, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a70 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X3, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X28, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X1, X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X25, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X28,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.CC 41fac0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code