OV - exec - Loop 3411

	Loop Id: 3411	Module: exec	Source: ParticleBConds3DSoa.h:237-255	Coverage: 0.05%

0x4f47d0 LD1D	{Z27.D}, P6/Z, [X10, X30,LSL #3]    [1]

0x4f47d4 LD1D	{Z28.D}, P6/Z, [X9, X30,LSL #3]    [6]

0x4f47d8 LD1D	{Z26.D}, P6/Z, [X0, X30,LSL #3]    [2]

0x4f47dc LD1RD	{Z1.D}, P7/Z, [X19, #13]    [8]

0x4f47e0 LD1RD	{Z2.D}, P7/Z, [X19, #12]    [8]

0x4f47e4 LD1RD	{Z24.D}, P7/Z, [X19, #10]    [8]

0x4f47e8 LD1RD	{Z25.D}, P7/Z, [X19, #9]    [8]

0x4f47ec LD1RD	{Z17.D}, P7/Z, [X19, #16]    [8]

0x4f47f0 LD1RD	{Z18.D}, P7/Z, [X19, #15]    [8]

0x4f47f4 FSUB	Z3.D, Z27.D, Z30.D

0x4f47f8 FSUB	Z5.D, Z28.D, Z31.D

0x4f47fc FSUB	Z6.D, Z26.D, Z29.D

0x4f4800 LD1RD	{Z0.D}, P7/Z, [X19, #14]    [8]

0x4f4804 LD1RD	{Z23.D}, P7/Z, [X19, #11]    [8]

0x4f4808 LD1RD	{Z16.D}, P7/Z, [X19, #17]    [8]

0x4f480c FMUL	Z4.D, Z1.D, Z3.D

0x4f4810 FMUL	Z7.D, Z24.D, Z3.D

0x4f4814 FMLA	Z4.D, P7/M, Z2.D, Z5.D

0x4f4818 FMLA	Z7.D, P7/M, Z25.D, Z5.D

0x4f481c FMAD	Z0.D, P7/M, Z6.D, Z4.D

0x4f4820 FMAD	Z23.D, P7/M, Z6.D, Z7.D

0x4f4824 FMUL	Z19.D, Z17.D, Z3.D

0x4f4828 FMLA	Z19.D, P7/M, Z18.D, Z5.D

0x4f482c FMAD	Z16.D, P7/M, Z6.D, Z19.D

0x4f4830 LD1RD	{Z20.D}, P7/Z, [X19, #1]    [8]

0x4f4834 LD1RD	{Z3.D}, P7/Z, [X19]    [8]

0x4f4838 LD1RD	{Z5.D}, P7/Z, [X19, #2]    [8]

0x4f483c MOVPRFX	Z21, Z0

0x4f4840 FRINTA	Z21.D, P7/M, Z0.D

0x4f4844 MOVPRFX	Z22, Z23

0x4f4848 FRINTA	Z22.D, P7/M, Z23.D

0x4f484c FSUB	Z27.D, Z0.D, Z21.D

0x4f4850 FSUB	Z28.D, Z23.D, Z22.D

0x4f4854 MOVPRFX	Z4, Z16

0x4f4858 FRINTA	Z4.D, P7/M, Z16.D

0x4f485c FMUL	Z1.D, Z20.D, Z27.D

0x4f4860 FSUB	Z26.D, Z16.D, Z4.D

0x4f4864 FMLA	Z1.D, P7/M, Z3.D, Z28.D

0x4f4868 FMAD	Z5.D, P7/M, Z26.D, Z1.D

0x4f486c ST1D	{Z5.D}, P6, [X15, X30,LSL #3]    [7]

0x4f4870 LD1RD	{Z6.D}, P7/Z, [X19, #3]    [8]

0x4f4874 LD1RD	{Z0.D}, P7/Z, [X19, #4]    [8]

0x4f4878 LD1RD	{Z2.D}, P7/Z, [X19, #5]    [8]

0x4f487c FMUL	Z24.D, Z0.D, Z27.D

0x4f4880 FMLA	Z24.D, P7/M, Z6.D, Z28.D

0x4f4884 FMAD	Z2.D, P7/M, Z26.D, Z24.D

0x4f4888 ST1D	{Z2.D}, P6, [X17, X30,LSL #3]    [5]

0x4f488c LD1RD	{Z7.D}, P7/Z, [X19, #7]    [8]

0x4f4890 LD1RD	{Z25.D}, P7/Z, [X19, #6]    [8]

0x4f4894 LD1RD	{Z17.D}, P7/Z, [X19, #8]    [8]

0x4f4898 FMUL	Z23.D, Z7.D, Z27.D

0x4f489c FMLA	Z23.D, P7/M, Z25.D, Z28.D

0x4f48a0 FMAD	Z17.D, P7/M, Z26.D, Z23.D

0x4f48a4 ST1D	{Z17.D}, P6, [X18, X30,LSL #3]    [4]

0x4f48a8 LD1D	{Z18.D}, P6/Z, [X17, X30,LSL #3]    [5]

0x4f48ac LD1D	{Z19.D}, P6/Z, [X15, X30,LSL #3]    [7]

0x4f48b0 FMUL	Z16.D, Z18.D, Z18.D

0x4f48b4 FMLA	Z16.D, P7/M, Z19.D, Z19.D

0x4f48b8 FMLA	Z16.D, P7/M, Z17.D, Z17.D

0x4f48bc FSQRT	Z16.D, P7/M, Z16.D

0x4f48c0 ST1D	{Z16.D}, P6, [X16, X30,LSL #3]    [3]

0x4f48c4 ADD	X30, X30, X21

0x4f48c8 WHILELO	P6.D, W30, W7

0x4f48cc B.NE	4f47d0

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 237 - 255

--------------------------------------------------------------------------------

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	8.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	17.00
P6 cycles	17.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.41
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	65.57
Vectorization ratio load	21.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	77.87
Vector-efficiency ratio load	41.30
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	8.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	17.00
P6 cycles	17.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.41
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	65.57
Vectorization ratio load	21.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	77.87
Vector-efficiency ratio load	41.30
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 77% of vector register length is used (average across all VPU instructions).

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	17.00	17.00	2.00	2.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	17.00	17.00	13.50	13.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	30%
load	21%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	65%
load	21%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

18% of peak load performance is reached (17.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f47d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z27.D}, P6/Z, [X10, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P6/Z, [X9, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P6/Z, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z1.D}, P7/Z, [X19, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z2.D}, P7/Z, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z24.D}, P7/Z, [X19, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z25.D}, P7/Z, [X19, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z17.D}, P7/Z, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z18.D}, P7/Z, [X19, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z3.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z5.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z6.D, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z0.D}, P7/Z, [X19, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z23.D}, P7/Z, [X19, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z16.D}, P7/Z, [X19, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z4.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z7.D, Z24.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z4.D, P7/M, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z7.D, P7/M, Z25.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z0.D, P7/M, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z23.D, P7/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z19.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z19.D, P7/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P7/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z20.D}, P7/Z, [X19, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z3.D}, P7/Z, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z5.D}, P7/Z, [X19, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z21.D, P7/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z22, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z22.D, P7/M, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z27.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z28.D, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z4.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z1.D, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z26.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z1.D, P7/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z5.D, P7/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z5.D}, P6, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z6.D}, P7/Z, [X19, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z0.D}, P7/Z, [X19, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z2.D}, P7/Z, [X19, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z24.D, Z0.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z24.D, P7/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z2.D, P7/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z2.D}, P6, [X17, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z7.D}, P7/Z, [X19, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z25.D}, P7/Z, [X19, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z17.D}, P7/Z, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z23.D, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z23.D, P7/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z17.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z17.D}, P6, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z18.D}, P6/Z, [X17, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P6/Z, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z16.D, P7/M, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z16.D, P7/M, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z16.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08
ST1D {Z16.D}, P6, [X16, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X30, X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P6.D, W30, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 4f47d0 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 77% of vector register length is used (average across all VPU instructions).

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	17.00	17.00	2.00	2.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	17.00	17.00	13.50	13.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	30%
load	21%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	65%
load	21%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

18% of peak load performance is reached (17.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f47d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z27.D}, P6/Z, [X10, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P6/Z, [X9, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P6/Z, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z1.D}, P7/Z, [X19, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z2.D}, P7/Z, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z24.D}, P7/Z, [X19, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z25.D}, P7/Z, [X19, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z17.D}, P7/Z, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z18.D}, P7/Z, [X19, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z3.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z5.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z6.D, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z0.D}, P7/Z, [X19, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z23.D}, P7/Z, [X19, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z16.D}, P7/Z, [X19, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z4.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z7.D, Z24.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z4.D, P7/M, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z7.D, P7/M, Z25.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z0.D, P7/M, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z23.D, P7/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z19.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z19.D, P7/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P7/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z20.D}, P7/Z, [X19, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z3.D}, P7/Z, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z5.D}, P7/Z, [X19, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z21.D, P7/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z22, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z22.D, P7/M, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z27.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z28.D, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z4.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z1.D, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z26.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z1.D, P7/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z5.D, P7/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z5.D}, P6, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z6.D}, P7/Z, [X19, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z0.D}, P7/Z, [X19, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z2.D}, P7/Z, [X19, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z24.D, Z0.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z24.D, P7/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z2.D, P7/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z2.D}, P6, [X17, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z7.D}, P7/Z, [X19, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z25.D}, P7/Z, [X19, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z17.D}, P7/Z, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z23.D, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z23.D, P7/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z17.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z17.D}, P6, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z18.D}, P6/Z, [X17, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P6/Z, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z16.D, P7/M, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z16.D, P7/M, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z16.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08
ST1D {Z16.D}, P6, [X16, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X30, X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P6.D, W30, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 4f47d0 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code