OV - exec - Loop 322

	Loop Id: 322	Module: exec	Source: BsplineFunctor.h:305-336 [...]	Coverage: 0.02%

0x41a430 PUNPKLO	P5.H, P4.B

0x41a434 PUNPKHI	P6.H, P4.B

0x41a438 LD1D	{Z27.D}, P5/Z, [X11, X5,LSL #3]    [13]

0x41a43c LD1D	{Z24.D}, P6/Z, [X13, X5,LSL #3]    [33]

0x41a440 FMUL	Z15.D, Z27.D, Z19.D

0x41a444 FMUL	Z31.D, Z24.D, Z19.D

0x41a448 MOVPRFX	Z17, Z15

0x41a44c FCVTZS	Z17.S, P7/M, Z15.D

0x41a450 MOVPRFX	Z18, Z31

0x41a454 FCVTZS	Z18.S, P7/M, Z31.D

0x41a458 MOVPRFX	Z20, Z15

0x41a45c FRINTZ	Z20.D, P7/M, Z15.D

0x41a460 UZP1	Z21.S, Z17.S, Z18.S

0x41a464 FSUB	Z30.D, Z15.D, Z20.D

0x41a468 MOVPRFX	Z22, Z21

0x41a46c ADD	Z22.S, Z22.S, #1

0x41a470 MOVPRFX	Z28, Z3

0x41a474 FMLA	Z28.D, P7/M, Z30.D, Z2.D

0x41a478 SUNPKLO	Z25.D, Z22

0x41a47c LD1D	{Z13.D}, P5/Z, [X4, Z25.D,LSL #3]    [38]

0x41a480 FMUL	Z12.D, Z13.D, Z28.D

0x41a484 MOVPRFX	Z26, Z21

0x41a488 ADD	Z26.S, Z26.S, #3

0x41a48c SUNPKHI	Z23.D, Z22

0x41a490 SUNPKLO	Z16.D, Z21

0x41a494 SUNPKLO	Z22.D, Z26

0x41a498 LD1D	{Z14.D}, P5/Z, [X4, Z16.D,LSL #3]    [40]

0x41a49c MOVPRFX	Z28, Z21

0x41a4a0 ADD	Z28.S, Z28.S, #2

0x41a4a4 MOVPRFX	Z29, Z1

0x41a4a8 FMLA	Z29.D, P7/M, Z30.D, Z0.D

0x41a4ac SUNPKHI	Z26.D, Z26

0x41a4b0 FMAD	Z29.D, P7/M, Z14.D, Z12.D

0x41a4b4 SUNPKHI	Z12.D, Z21

0x41a4b8 SUNPKLO	Z21.D, Z28

0x41a4bc LD1D	{Z15.D}, P5/Z, [X4, Z22.D,LSL #3]    [28]

0x41a4c0 ADDVL	X16, SP, #21

0x41a4c4 LD1D	{Z22.D}, P6/Z, [X4, Z26.D,LSL #3]    [43]

0x41a4c8 LD1D	{Z26.D}, P5/Z, [X4, Z21.D,LSL #3]    [25]

0x41a4cc MOVPRFX	Z21, Z31

0x41a4d0 FRINTZ	Z21.D, P7/M, Z31.D

0x41a4d4 LD1D	{Z17.D}, P6/Z, [X4, Z23.D,LSL #3]    [32]

0x41a4d8 FSUB	Z31.D, Z31.D, Z21.D

0x41a4dc SUNPKHI	Z16.D, Z28

0x41a4e0 MOVPRFX	Z21, Z3

0x41a4e4 FMLA	Z21.D, P7/M, Z31.D, Z2.D

0x41a4e8 ADD	X16, X16, #176

0x41a4ec LDR	Z20, [X16, MUL VL]    [23]

0x41a4f0 MOVPRFX	Z25, Z5

0x41a4f4 FMLA	Z25.D, P7/M, Z30.D, Z4.D

0x41a4f8 ORR	Z18.D, Z20.D, Z20.D

0x41a4fc ADDVL	X8, SP, #24

0x41a500 FMLA	Z18.D, P7/M, Z30.D, Z6.D

0x41a504 FMLA	Z20.D, P7/M, Z31.D, Z6.D

0x41a508 FMUL	Z23.D, Z15.D, Z18.D

0x41a50c FMAD	Z25.D, P7/M, Z26.D, Z23.D

0x41a510 FADD	Z29.D, Z29.D, Z25.D

0x41a514 LD1D	{Z18.D}, P6/Z, [X4, Z12.D,LSL #3]    [27]

0x41a518 LD1D	{Z23.D}, P6/Z, [X4, Z16.D,LSL #3]    [39]

0x41a51c LD1W	{Z25.S}, P4/Z, [X12, X5,LSL #2]    [1]

0x41a520 ADD	X8, X8, #176

0x41a524 LDR	Z12, [X8, MUL VL]    [49]

0x41a528 SUNPKLO	Z16.D, Z25

0x41a52c FMUL	Z28.D, Z29.D, Z12.D

0x41a530 ADDVL	X17, SP, #10

0x41a534 ST1D	{Z28.D}, P5, [X10, Z16.D,LSL #3]    [31]

0x41a538 FMUL	Z29.D, Z22.D, Z20.D

0x41a53c FMUL	Z20.D, Z17.D, Z21.D

0x41a540 FDUP	Z21.D, #112

0x41a544 SUNPKHI	Z25.D, Z25

0x41a548 ADD	X17, X17, #176

0x41a54c ADD	X16, SP, #176

0x41a550 MOVPRFX	Z28, Z5

0x41a554 FMLA	Z28.D, P7/M, Z31.D, Z4.D

0x41a558 FDIVR	Z27.D, P7/M, Z27.D, Z21.D

0x41a55c FMAD	Z28.D, P7/M, Z23.D, Z29.D

0x41a560 ADDVL	X9, SP, #11

0x41a564 MOVPRFX	Z29, Z1

0x41a568 FMLA	Z29.D, P7/M, Z31.D, Z0.D

0x41a56c ADDVL	X6, SP, #8

0x41a570 FMAD	Z29.D, P7/M, Z18.D, Z20.D

0x41a574 FADD	Z28.D, Z29.D, Z28.D

0x41a578 FMUL	Z12.D, Z28.D, Z12.D

0x41a57c ST1D	{Z12.D}, P6, [X10, Z25.D,LSL #3]    [29]

0x41a580 LDR	Z20, [X17, MUL VL]    [21]

0x41a584 LDR	Z21, [X16, #7, MUL VL]    [8]

0x41a588 FMUL	Z28.D, Z30.D, Z30.D

0x41a58c ADD	X8, SP, #176

0x41a590 ADD	X9, X9, #176

0x41a594 LDR	Z12, [X9, MUL VL]    [17]

0x41a598 ADD	X6, X6, #176

0x41a59c LDR	Z29, [X6, MUL VL]    [18]

0x41a5a0 FMLA	Z12.D, P7/M, Z30.D, Z20.D

0x41a5a4 FMLA	Z29.D, P7/M, Z30.D, Z21.D

0x41a5a8 INCB	X16, ALL, MUL #9

0x41a5ac LDR	Z20, [X16, MUL VL]    [46]

0x41a5b0 LDR	Z21, [X8, #6, MUL VL]    [5]

0x41a5b4 FMLA	Z12.D, P7/M, Z28.D, Z20.D

0x41a5b8 FMLA	Z29.D, P7/M, Z28.D, Z21.D

0x41a5bc FMUL	Z21.D, Z15.D, Z12.D

0x41a5c0 LDR	Z12, [X8, #4, MUL VL]    [5]

0x41a5c4 LDR	Z20, [X8, #5, MUL VL]    [5]

0x41a5c8 FMAD	Z29.D, P7/M, Z26.D, Z21.D

0x41a5cc FMLA	Z20.D, P7/M, Z30.D, Z12.D

0x41a5d0 LDR	Z21, [X8, #3, MUL VL]    [5]

0x41a5d4 LDR	Z12, [X8, #1, MUL VL]    [5]

0x41a5d8 FMLA	Z20.D, P7/M, Z28.D, Z21.D

0x41a5dc ADDVL	X9, SP, #10

0x41a5e0 LDR	Z21, [X8, #2, MUL VL]    [5]

0x41a5e4 FMUL	Z20.D, Z13.D, Z20.D

0x41a5e8 FMLA	Z21.D, P7/M, Z30.D, Z12.D

0x41a5ec LDR	Z12, [X8, MUL VL]    [5]

0x41a5f0 FMUL	Z27.D, Z27.D, Z19.D

0x41a5f4 FMLA	Z21.D, P7/M, Z28.D, Z12.D

0x41a5f8 FMAD	Z21.D, P7/M, Z14.D, Z20.D

0x41a5fc FADD	Z29.D, Z29.D, Z21.D

0x41a600 FMUL	Z27.D, Z29.D, Z27.D

0x41a604 ADD	X9, X9, #176

0x41a608 ST1D	{Z27.D}, P5, [X18, Z16.D,LSL #3]    [37]

0x41a60c LDR	Z20, [X9, MUL VL]    [14]

0x41a610 ADD	X6, SP, #176

0x41a614 FDUP	Z21.D, #112

0x41a618 LDR	Z27, [X6, #7, MUL VL]    [42]

0x41a61c ADDVL	X17, SP, #8

0x41a620 FMUL	Z29.D, Z31.D, Z31.D

0x41a624 ADD	X16, SP, #176

0x41a628 INCB	X8, ALL, MUL #11

0x41a62c LDR	Z12, [X8, MUL VL]    [34]

0x41a630 ADD	X17, X17, #176

0x41a634 FMLA	Z12.D, P7/M, Z31.D, Z20.D

0x41a638 INCB	X6, ALL, MUL #9

0x41a63c FDIVR	Z24.D, P7/M, Z24.D, Z21.D

0x41a640 LDR	Z21, [X17, MUL VL]    [2]

0x41a644 LDR	Z20, [X6, MUL VL]    [24]

0x41a648 FMLA	Z21.D, P7/M, Z31.D, Z27.D

0x41a64c FMLA	Z12.D, P7/M, Z29.D, Z20.D

0x41a650 LDR	Z27, [X16, #6, MUL VL]    [6]

0x41a654 FMLA	Z21.D, P7/M, Z29.D, Z27.D

0x41a658 LDR	Z20, [X16, #5, MUL VL]    [6]

0x41a65c FMUL	Z27.D, Z22.D, Z12.D

0x41a660 LDR	Z12, [X16, #4, MUL VL]    [6]

0x41a664 FMAD	Z21.D, P7/M, Z23.D, Z27.D

0x41a668 FMLA	Z20.D, P7/M, Z31.D, Z12.D

0x41a66c LDR	Z27, [X16, #3, MUL VL]    [6]

0x41a670 LDR	Z12, [X16, #1, MUL VL]    [6]

0x41a674 FMLA	Z20.D, P7/M, Z29.D, Z27.D

0x41a678 ADDVL	X17, SP, #17

0x41a67c LDR	Z27, [X16, #2, MUL VL]    [6]

0x41a680 FMUL	Z20.D, Z17.D, Z20.D

0x41a684 FMLA	Z27.D, P7/M, Z31.D, Z12.D

0x41a688 LDR	Z12, [X16, MUL VL]    [6]

0x41a68c FMLA	Z27.D, P7/M, Z29.D, Z12.D

0x41a690 FMAD	Z27.D, P7/M, Z18.D, Z20.D

0x41a694 FADD	Z21.D, Z27.D, Z21.D

0x41a698 ADDVL	X8, X16, #22

0x41a69c ADD	X17, X17, #176

0x41a6a0 FMUL	Z24.D, Z24.D, Z19.D

0x41a6a4 ADDVL	X9, SP, #18

0x41a6a8 FMUL	Z24.D, Z21.D, Z24.D

0x41a6ac ADDVL	X6, SP, #16

0x41a6b0 ST1D	{Z24.D}, P6, [X18, Z25.D,LSL #3]    [35]

0x41a6b4 LDR	Z21, [X17, MUL VL]    [12]

0x41a6b8 ADDVL	X16, SP, #13

0x41a6bc ADD	X9, X9, #176

0x41a6c0 LDR	Z20, [X9, MUL VL]    [50]

0x41a6c4 ADD	X6, X6, #176

0x41a6c8 FMLA	Z20.D, P7/M, Z30.D, Z21.D

0x41a6cc LDR	Z21, [X6, MUL VL]    [51]

0x41a6d0 ADD	X16, X16, #176

0x41a6d4 LDR	Z12, [X8, MUL VL]    [48]

0x41a6d8 FMUL	Z27.D, Z30.D, Z28.D

0x41a6dc FMUL	Z24.D, Z28.D, Z12.D

0x41a6e0 ADDVL	X8, SP, #12

0x41a6e4 FMLA	Z24.D, P7/M, Z27.D, Z21.D

0x41a6e8 LDR	Z21, [X16, MUL VL]    [36]

0x41a6ec ADDVL	X9, SP, #15

0x41a6f0 ADDVL	X17, SP, #14

0x41a6f4 FMUL	Z21.D, Z28.D, Z21.D

0x41a6f8 ADDVL	X6, SP, #23

0x41a6fc ADDVL	X16, SP, #19

0x41a700 FADD	Z24.D, Z20.D, Z24.D

0x41a704 ADD	X8, X8, #176

0x41a708 LDR	Z20, [X8, MUL VL]    [44]

0x41a70c ADD	X9, X9, #176

0x41a710 FMLA	Z21.D, P7/M, Z27.D, Z20.D

0x41a714 ADD	X17, X17, #176

0x41a718 ADD	X6, X6, #176

0x41a71c ADD	X16, X16, #176

0x41a720 LDR	Z20, [X9, MUL VL]    [26]

0x41a724 FMUL	Z24.D, Z24.D, Z13.D

0x41a728 LDR	Z13, [X17, MUL VL]    [10]

0x41a72c ADDVL	X8, SP, #20

0x41a730 FMLA	Z20.D, P7/M, Z30.D, Z13.D

0x41a734 ADDVL	X9, SP, #18

0x41a738 FADD	Z20.D, Z20.D, Z21.D

0x41a73c LDR	Z21, [X16, MUL VL]    [11]

0x41a740 FMAD	Z20.D, P7/M, Z14.D, Z24.D

0x41a744 LDR	Z14, [X6, MUL VL]    [15]

0x41a748 ADDVL	X17, SP, #17

0x41a74c ADDVL	X6, SP, #16

0x41a750 ADDVL	X16, SP, #13

0x41a754 MOVPRFX	Z24, Z11

0x41a758 FMLA	Z24.D, P7/M, Z30.D, Z10.D

0x41a75c ADD	X8, X8, #176

0x41a760 ADD	X9, X9, #176

0x41a764 FMUL	Z13.D, Z28.D, Z9.D

0x41a768 ADD	X17, X17, #176

0x41a76c FMUL	Z28.D, Z28.D, Z14.D

0x41a770 ADD	X6, X6, #176

0x41a774 ADD	X16, X16, #176

0x41a778 FMLA	Z13.D, P7/M, Z27.D, Z8.D

0x41a77c FMAD	Z27.D, P7/M, Z21.D, Z28.D

0x41a780 LDR	Z28, [X8, MUL VL]    [19]

0x41a784 FADD	Z13.D, Z13.D, Z24.D

0x41a788 FMAD	Z30.D, P7/M, Z28.D, Z7.D

0x41a78c FMUL	Z15.D, Z13.D, Z15.D

0x41a790 FADD	Z30.D, Z27.D, Z30.D

0x41a794 ADDVL	X8, SP, #12

0x41a798 FMAD	Z26.D, P7/M, Z30.D, Z15.D

0x41a79c FMUL	Z27.D, Z29.D, Z12.D

0x41a7a0 FADD	Z26.D, Z26.D, Z20.D

0x41a7a4 ST1D	{Z26.D}, P5, [X30, Z16.D,LSL #3]    [9]

0x41a7a8 LDR	Z20, [X17, MUL VL]    [20]

0x41a7ac LDR	Z24, [X6, MUL VL]    [30]

0x41a7b0 LDR	Z12, [X9, MUL VL]    [45]

0x41a7b4 LDR	Z21, [X16, MUL VL]    [16]

0x41a7b8 FMUL	Z16.D, Z31.D, Z29.D

0x41a7bc FMLA	Z12.D, P7/M, Z31.D, Z20.D

0x41a7c0 FMLA	Z27.D, P7/M, Z16.D, Z24.D

0x41a7c4 ADDVL	X9, SP, #15

0x41a7c8 ADDVL	X17, SP, #14

0x41a7cc ADDVL	X6, SP, #19

0x41a7d0 FADD	Z13.D, Z12.D, Z27.D

0x41a7d4 ADDVL	X16, SP, #20

0x41a7d8 FMUL	Z15.D, Z29.D, Z21.D

0x41a7dc FMUL	Z12.D, Z29.D, Z9.D

0x41a7e0 ADD	X8, X8, #176

0x41a7e4 LDR	Z28, [X8, MUL VL]    [22]

0x41a7e8 FMLA	Z12.D, P7/M, Z16.D, Z8.D

0x41a7ec FMLA	Z15.D, P7/M, Z16.D, Z28.D

0x41a7f0 ADD	X9, X9, #176

0x41a7f4 LDR	Z30, [X9, MUL VL]    [3]

0x41a7f8 ADD	X17, X17, #176

0x41a7fc LDR	Z26, [X17, MUL VL]    [4]

0x41a800 ADD	X6, X6, #176

0x41a804 FMLA	Z30.D, P7/M, Z31.D, Z26.D

0x41a808 ADD	X16, X16, #176

0x41a80c LDR	Z24, [X16, MUL VL]    [47]

0x41a810 FMUL	Z17.D, Z17.D, Z13.D

0x41a814 FADD	Z20.D, Z30.D, Z15.D

0x41a818 FMAD	Z20.D, P7/M, Z18.D, Z17.D

0x41a81c FMUL	Z18.D, Z29.D, Z14.D

0x41a820 LDR	Z14, [X6, MUL VL]    [41]

0x41a824 MOVPRFX	Z29, Z11

0x41a828 FMLA	Z29.D, P7/M, Z31.D, Z10.D

0x41a82c FMAD	Z16.D, P7/M, Z14.D, Z18.D

0x41a830 FADD	Z27.D, Z29.D, Z12.D

0x41a834 FMAD	Z31.D, P7/M, Z24.D, Z7.D

0x41a838 FMUL	Z22.D, Z22.D, Z27.D

0x41a83c FADD	Z31.D, Z16.D, Z31.D

0x41a840 FMAD	Z23.D, P7/M, Z31.D, Z22.D

0x41a844 FADD	Z23.D, Z20.D, Z23.D

0x41a848 ST1D	{Z23.D}, P6, [X30, Z25.D,LSL #3]    [7]

0x41a84c ADD	X5, X5, X0

0x41a850 WHILELO	P4.S, W5, W7

0x41a854 B.NE	41a430

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	BsplineFunctor.h:305-336,stl_vector.h:1147-1147
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.00
CQA cycles if no scalar integer	69.00
CQA cycles if FP arith vectorized	69.00
CQA cycles if fully vectorized	68.03
Front-end cycles	33.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	10.50
P2 cycles	10.25
P3 cycles	33.00
P4 cycles	10.25
P5 cycles	69.00
P6 cycles	69.00
P7 cycles	50.00
P8 cycles	50.00
P9 cycles	31.50
P10 cycles	31.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	266.00
Nb uops	266.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.93
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.22
Bytes prefetched	0.00
Bytes loaded	1824.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	86.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.86
Vector-efficiency ratio all	98.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.46

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	BsplineFunctor.h:305-336,stl_vector.h:1147-1147
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.00
CQA cycles if no scalar integer	69.00
CQA cycles if FP arith vectorized	69.00
CQA cycles if fully vectorized	68.03
Front-end cycles	33.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	10.50
P2 cycles	10.25
P3 cycles	33.00
P4 cycles	10.25
P5 cycles	69.00
P6 cycles	69.00
P7 cycles	50.00
P8 cycles	50.00
P9 cycles	31.50
P10 cycles	31.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	266.00
Nb uops	266.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.93
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.22
Bytes prefetched	0.00
Bytes loaded	1824.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	86.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.86
Vector-efficiency ratio all	98.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.46

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 69.00 to 68.03 cycles (1.01x speedup).

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1824 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	266
loop length	1064
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	3.00	3.00	31.50	31.50	0.00	0.00	0.00
cycles	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	50.00	50.00	31.50	31.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.25
Data deps.	1.00
Overall L1	69.00

Vectorization ratios

INT

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.00 cycles. At this rate:

27% of peak load performance is reached (26.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41a430

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUNPKLO P5.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
PUNPKHI P6.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z27.D}, P5/Z, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P6/Z, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z31.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z17, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z17.S, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z18.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z20, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z20.D, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
UZP1 Z21.S, Z17.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z15.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.S, Z22.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z30.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKLO Z25.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P5/Z, [X4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z12.D, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z26, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z26.S, Z26.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z23.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z22.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z14.D}, P5/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z28, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.S, Z28.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z30.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKHI Z26.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z29.D, P7/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKHI Z12.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z21.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z15.D}, P5/Z, [X4, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z22.D}, P6/Z, [X4, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P5/Z, [X4, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z21, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z21.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
LD1D {Z17.D}, P6/Z, [X4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z31.D, Z31.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z16.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z21, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z21.D, P7/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P7/M, Z30.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ORR Z18.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X8, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z18.D, P7/M, Z30.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z31.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z15.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z25.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P6/Z, [X4, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P6/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1W {Z25.S}, P4/Z, [X12, X5,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z16.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X17, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ST1D {Z28.D}, P5, [X10, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z29.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z20.D, Z17.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z25.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z27.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
FMAD Z28.D, P7/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X6, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z29.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z12.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z12.D}, P6, [X10, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X16, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X8, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z29, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X16, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X8, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z21.D, Z15.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z12, [X8, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X8, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z29.D, P7/M, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z21, [X8, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z21, [X8, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z21.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z21.D, P7/M, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z21.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z27.D}, P5, [X18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z27, [X6, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X17, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X16, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
INCB X8, ALL, MUL #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X6, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FDIVR Z24.D, P7/M, Z24.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z21.D, P7/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z12.D, P7/M, Z29.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z27, [X16, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z21.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X16, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z12, [X16, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z21.D, P7/M, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z27, [X16, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z27, [X16, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z17.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z27.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z27.D, P7/M, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z27.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z21.D, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X8, X16, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z24.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X9, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z24.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ST1D {Z24.D}, P6, [X18, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z20.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z21, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z24.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z24.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z21, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X9, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z21.D, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X6, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z24.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z21.D, P7/M, Z27.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z24.D, Z24.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z13, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X8, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z20.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z21, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z20.D, P7/M, Z14.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MOVPRFX Z24, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z24.D, P7/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z13.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z28.D, Z28.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z13.D, P7/M, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z27.D, P7/M, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z13.D, Z13.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z30.D, P7/M, Z28.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z15.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z26.D, P7/M, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z26.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z26.D}, P5, [X30, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z24, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z27.D, P7/M, Z16.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X6, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z13.D, Z12.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X16, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z15.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z12.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z15.D, P7/M, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z30, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z26, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z30.D, P7/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z24, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z20.D, P7/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z18.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P7/M, Z14.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z31.D, P7/M, Z24.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z22.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z31.D, Z16.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z23.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z23.D}, P6, [X30, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X5, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P4.S, W5, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 41a430 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1147

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1824 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	266
loop length	1064
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	3.00	3.00	31.50	31.50	0.00	0.00	0.00
cycles	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	50.00	50.00	31.50	31.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.25
Data deps.	1.00
Overall L1	69.00

Vectorization ratios

INT

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.00 cycles. At this rate:

27% of peak load performance is reached (26.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41a430

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUNPKLO P5.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
PUNPKHI P6.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z27.D}, P5/Z, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P6/Z, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z31.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z17, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z17.S, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z18.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z20, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z20.D, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
UZP1 Z21.S, Z17.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z15.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.S, Z22.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z30.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKLO Z25.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P5/Z, [X4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z12.D, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z26, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z26.S, Z26.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z23.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z22.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z14.D}, P5/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z28, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.S, Z28.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z30.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKHI Z26.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z29.D, P7/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKHI Z12.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z21.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z15.D}, P5/Z, [X4, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z22.D}, P6/Z, [X4, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P5/Z, [X4, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z21, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTZ Z21.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
LD1D {Z17.D}, P6/Z, [X4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z31.D, Z31.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z16.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z21, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z21.D, P7/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P7/M, Z30.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ORR Z18.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X8, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z18.D, P7/M, Z30.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z31.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z15.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z25.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P6/Z, [X4, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P6/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1W {Z25.S}, P4/Z, [X12, X5,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z16.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X17, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ST1D {Z28.D}, P5, [X10, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z29.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z20.D, Z17.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z25.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z28.D, P7/M, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z27.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
FMAD Z28.D, P7/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X6, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z29.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z12.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z12.D}, P6, [X10, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X16, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X8, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z29, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X16, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X8, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z21.D, Z15.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z12, [X8, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X8, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z29.D, P7/M, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z21, [X8, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z21, [X8, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z21.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z21.D, P7/M, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z21.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z27.D}, P5, [X18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z27, [X6, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X17, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X16, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
INCB X8, ALL, MUL #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X6, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FDIVR Z24.D, P7/M, Z24.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z20, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z21.D, P7/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z12.D, P7/M, Z29.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z27, [X16, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z21.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z20, [X16, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z12, [X16, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z21.D, P7/M, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z20.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z27, [X16, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z20.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z27, [X16, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z17.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z27.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z27.D, P7/M, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z27.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z21.D, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X8, X16, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z24.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X9, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z24.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ST1D {Z24.D}, P6, [X18, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z20.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z21, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z24.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z24.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z21, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X9, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z21.D, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X6, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z24.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z21.D, P7/M, Z27.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z20, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z24.D, Z24.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z13, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X8, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z20.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z21, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z20.D, P7/M, Z14.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MOVPRFX Z24, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z24.D, P7/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z13.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z28.D, Z28.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z13.D, P7/M, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z27.D, P7/M, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z13.D, Z13.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z30.D, P7/M, Z28.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z15.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z26.D, P7/M, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z26.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z26.D}, P5, [X30, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z24, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z21, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z27.D, P7/M, Z16.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X9, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X6, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z13.D, Z12.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X16, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z15.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z12.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z12.D, P7/M, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z15.D, P7/M, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X9, X9, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z30, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z26, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z30.D, P7/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z24, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z20.D, P7/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z18.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P7/M, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P7/M, Z14.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z31.D, P7/M, Z24.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z22.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z31.D, Z16.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z23.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z23.D}, P6, [X30, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X5, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P4.S, W5, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 41a430 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code