OV - exec - Loop 32

	Loop Id: 32	Module: exec	Source: miniqmc.cpp:429-458 [...]	Coverage: 0.01%

0x40862c LDR	X8, [X20, #8]    [5]

0x408630 LDR	X12, [X8]    [2]

0x408634 LDR	X0, [X12, #40]    [1]

0x408638 BL	4c43c0

0x40863c ORR	W2, WZR, W19

0x408640 ORR	X1, XZR, X21

0x408644 ORR	X0, XZR, X22

0x408648 BL	40f500

0x40864c LDR	X18, [X20, #8]    [5]

0x408650 LDR	X7, [X18]    [2]

0x408654 LDR	X0, [X7, #40]    [1]

0x408658 STP	D0, D1, [SP, #432]    [4]

0x40865c STR	D2, [SP, #448]    [4]

0x408660 BL	4c4660

0x408664 ORR	X2, XZR, X23

0x408668 ORR	W1, WZR, W19

0x40866c MOVZ	W3, #1

0x408670 ORR	X0, XZR, X21

0x408674 BL	484e00

0x408678 LDR	X15, [X20, #8]    [5]

0x40867c LDR	X4, [X15]    [2]

0x408680 LDR	X0, [X4, #48]    [1]

0x408684 BL	4c43c0

0x408688 ADD	X3, SP, #400

0x40868c ORR	W2, WZR, W19

0x408690 STP	D12, D12, [SP, #400]    [4]

0x408694 ORR	X1, XZR, X21

0x408698 ORR	X0, XZR, X22

0x40869c STR	D12, [SP, #416]    [4]

0x4086a0 BL	40f648

0x4086a4 LDR	X3, [X20, #8]    [5]

0x4086a8 LDR	X5, [X3]    [2]

0x4086ac LDR	X0, [X5, #48]    [1]

0x4086b0 BL	4c4660

0x4086b4 LDR	D3, [X25, X19,LSL #3]    [3]

0x4086b8 FCMPE	D15, D3

0x4086bc B.GT	40899c

0x4086c0 ORR	W1, WZR, W19

0x4086c4 ORR	X0, XZR, X21

0x4086c8 BL	4871c4

0x4086cc ORR	W1, WZR, W19

0x4086d0 ORR	X0, XZR, X22

0x4086d4 BL	40fa00

0x4086d8 LDR	X6, [SP, #144]    [4]

0x4086dc ADD	X19, X19, #1

0x4086e0 ADD	X23, X23, #24

0x4086e4 CMP	X6, X19

0x4086e8 B.NE	40862c

0x40899c LDR	X16, [X20, #8]    [5]

0x4089a0 ADD	X23, X23, #24

0x4089a4 LDR	X17, [X16]    [2]

0x4089a8 LDR	X0, [X17, #56]    [1]

0x4089ac BL	4c43c0

0x4089b0 ORR	W2, WZR, W19

0x4089b4 ORR	X1, XZR, X21

0x4089b8 ORR	X0, XZR, X22

0x4089bc BL	40f860

0x4089c0 LDR	X1, [X20, #8]    [5]

0x4089c4 LDR	X0, [X1]    [2]

0x4089c8 LDR	X0, [X0, #56]    [1]

0x4089cc BL	4c4660

0x4089d0 ORR	W1, WZR, W19

0x4089d4 ADD	X19, X19, #1

0x4089d8 ORR	X0, XZR, X21

0x4089dc BL	486cf0

0x4089e0 LDR	W13, [SP, #156]    [4]

0x4089e4 LDR	X14, [SP, #144]    [4]

0x4089e8 ADD	W2, W13, #1

0x4089ec STR	W2, [SP, #156]    [4]

0x4089f0 CMP	X14, X19

0x4089f4 B.NE	40862c

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp: 429 - 458

--------------------------------------------------------------------------------

429:         for (int iel = 0; iel < nels; ++iel)

430:         {

431:           // Compute gradient at the current position

432:           Timers[Timer_evalGrad].get().start();

433:           PosType grad_now = wavefunction.evalGrad(els, iel);

434:           Timers[Timer_evalGrad].get().stop();

435:

436:           // Construct trial move

437:           els.makeMove(iel, delta[iel]);

438:

439:           // Compute gradient at the trial position

440:           Timers[Timer_ratioGrad].get().start();

441:           PosType grad_new;

442:           wavefunction.ratioGrad(els, iel, grad_new);

443:           Timers[Timer_ratioGrad].get().stop();

444:

445:           // Accept/reject the trial move

446:           if (ur[iel] < accept) // MC

447:           {

448:             // Update position, and update temporary storage

449:             Timers[Timer_Update].get().start();

450:             wavefunction.acceptMove(els, iel);

451:             Timers[Timer_Update].get().stop();

452:             els.acceptMove(iel);

453:             my_accepted++;

454:           }

455:           else

456:           {

457:             els.rejectMove(iel);

458:             wavefunction.restore(iel);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1131 - 1131

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	3.90
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.98
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks
Function	main._omp_fn.1
Source	miniqmc.cpp:429-458,refwrap.h:347-347,TinyVector.h:62-62,stl_vector.h:1131-1131
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.79
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	7.79
CQA cycles if fully vectorized	1.30
Front-end cycles	6.75
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.42
P10 cycles	7.25
P11 cycles	7.33
P12 cycles	0.25
P13 cycles	0.25
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	4.50
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.08
Bytes prefetched	0.00
Bytes loaded	138.00
Bytes stored	50.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.35
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.67
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.91

Metric	Value
CQA speedup if no scalar integer	3.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P2, P3, P4, P5,
Function	main._omp_fn.1
Source	miniqmc.cpp:429-458,refwrap.h:347-347,TinyVector.h:62-62,stl_vector.h:1131-1131
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.13
Front-end cycles	6.00
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.70
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.53
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.34
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.19

Metric	Value
CQA speedup if no scalar integer	4.42
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.97
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	main._omp_fn.1
Source	miniqmc.cpp:429-458,refwrap.h:347-347,TinyVector.h:62-62,stl_vector.h:1131-1131
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	1.48
Front-end cycles	7.50
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	7.75
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.83
P10 cycles	8.50
P11 cycles	8.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.45
Bytes prefetched	0.00
Bytes loaded	164.00
Bytes stored	52.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	18.18
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:429-458
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429-458
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1131

The related source loop is multi-versionned.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.79 to 1.30 cycles (5.98x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.79 to 5.00 cycles (1.56x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 138 bytes. The binary loop is storing 50 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

front end

6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.25	7.25	7.25	7.25	2.50	2.50	0.00	0.00	7.42	7.25	7.33	0.25	0.25
cycles	6.00	6.00	7.25	7.25	7.25	7.25	2.50	2.50	0.00	0.00	7.42	7.25	7.33	0.25	0.25

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Data deps.	1.00
Overall L1	7.79

Vectorization ratios

all	14%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.79 cycles. At this rate:

18% of peak load performance is reached (17.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:429-458
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429-458
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1131

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.75 to 2.00 cycles (3.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.75 to 4.50 cycles (1.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	6.75	6.75	6.75	6.75	2.50	2.50	0.00	0.00	6.00	6.00	6.00	0.00	0.00
cycles	5.50	5.50	6.75	6.75	6.75	6.75	2.50	2.50	0.00	0.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.00
Data deps.	1.00
Overall L1	6.75

Vectorization ratios

all	10%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

17% of peak load performance is reached (16.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40862c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X12, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f500 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X18, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X7, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STP D0, D1, [SP, #432]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D2, [SP, #448]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 484e00 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X15]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X4, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X3, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP D12, D12, [SP, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D12, [SP, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
BL 40f648 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X3, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X5, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR D3, [X25, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D15, D3	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.GT 40899c <main._omp_fn.1+0x18b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4871c4 <_ZN11qmcplusplus11ParticleSet10rejectMoveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40fa00 <_ZN11qmcplusplus12WaveFunction7restoreEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X6, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 40862c <main._omp_fn.1+0x1540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:429-458
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429-458
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1131

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.83 to 2.00 cycles (4.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.83 to 1.48 cycles (5.97x speedup).

Details

18% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.83 to 5.50 cycles (1.61x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 164 bytes. The binary loop is storing 52 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	7.75	7.75	7.75	7.75	2.50	2.50	0.00	0.00	8.83	8.50	8.67	0.50	0.50
cycles	6.50	6.50	7.75	7.75	7.75	7.75	2.50	2.50	0.00	0.00	8.83	8.50	8.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.50
Data deps.	1.00
Overall L1	8.83

Vectorization ratios

all	18%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles. At this rate:

19% of peak load performance is reached (18.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40862c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X12, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40f500 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X7, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D0, D1, [SP, #432]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
STR D2, [SP, #448]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 484e00 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X15]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X4, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP D12, D12, [SP, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D12, [SP, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
BL 40f648 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X5, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X25, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D15, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 40899c <main._omp_fn.1+0x18b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X17, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40f860 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 486cf0 <_ZN11qmcplusplus11ParticleSet10acceptMoveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W13, [SP, #156]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W2, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W2, [SP, #156]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 40862c <main._omp_fn.1+0x1540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code