OV - exec - Loop 281

0x416b70 LDR	X2, [X23, #24]

0x416b74 ORR	X0, XZR, X22

0x416b78 LDRSW	X3, [X22, #672]

0x416b7c LDR	W1, [X26, #168]

0x416b80 LDR	D15, [X2, X3,LSL #3]

0x416b84 BL	484780

0x416b88 LDR	X4, [X0, #72]

0x416b8c LDR	W10, [X26, #152]

0x416b90 ADD	X5, X4, X20

0x416b94 LDR	X27, [X5, #24]

0x416b98 CMP	W10, #0

0x416b9c B.LE	4170ac

0x416ba0 LDR	X11, [X26, #456]

0x416ba4 MOVI	D1, #0

0x416ba8 MOVZ	X7, #0

0x416bac UBFM	X10, X10, #62, #31

0x416bb0 CNTW	X9, ALL

0x416bb4 PTRUE	P7.B, ALL

0x416bb8 HINT	#0

0x416bbc HINT	#0

  (280) 0x416bc0 UBFM	X17, X7, #63, #62

  (280) 0x416bc4 LDR	X30, [X11, X17]

  (280) 0x416bc8 CBZ	X30, 417048

  (280) 0x416bcc LDR	X5, [X26, #160]

  (280) 0x416bd0 LDR	X28, [X26, #328]

  (280) 0x416bd4 LDR	X6, [X5, #616]

  (280) 0x416bd8 LDR	X21, [X6, #24]

  (280) 0x416bdc ADD	X8, X21, X7

  (280) 0x416be0 LDR	W13, [X21, X7]

  (280) 0x416be4 LDR	W14, [X8, #4]

  (280) 0x416be8 CMP	W14, W13

  (280) 0x416bec B.LE	417048

  (280) 0x416bf0 SUB	W15, W14, W13

  (280) 0x416bf4 SBFM	X12, X13, #61, #31

  (280) 0x416bf8 LDR	D6, [X30, #8]

  (280) 0x416bfc ANDS	W18, W15, #128

  (280) 0x416c00 ADD	X6, X27, X12

  (280) 0x416c04 MOVZ	W17, #0

  (280) 0x416c08 ORR	W5, WZR, W13

  (280) 0x416c0c B.EQ	416d44

  (280) 0x416c10 CMP	W18, #1

  (280) 0x416c14 B.EQ	416d18

  (280) 0x416c18 CMP	W18, #2

  (280) 0x416c1c B.EQ	416cf4

  (280) 0x416c20 CMP	W18, #3

  (280) 0x416c24 B.EQ	416cd0

  (280) 0x416c28 CMP	W18, #4

  (280) 0x416c2c B.EQ	416cac

  (280) 0x416c30 CMP	W18, #5

  (280) 0x416c34 B.EQ	416c88

  (280) 0x416c38 CMP	W18, #6

  (280) 0x416c3c B.EQ	416c64

  (280) 0x416c40 LDR	D7, [X27, X12]

  (280) 0x416c44 FCMPE	D6, D7

  (280) 0x416c48 B.LS	416c5c

  (280) 0x416c4c CMN	W13, #1

  (280) 0x416c50 B.EQ	416c5c

  (280) 0x416c54 MOVZ	W17, #1

  (280) 0x416c58 STR	D7, [X28]

  (280) 0x416c5c ADD	X6, X6, #8

  (280) 0x416c60 ADD	W5, W13, #1

  (280) 0x416c64 LDR	D8, [X6]

  (280) 0x416c68 FCMPE	D6, D8

  (280) 0x416c6c B.LS	416c80

  (280) 0x416c70 CMN	W5, #1

  (280) 0x416c74 B.EQ	416c80

  (280) 0x416c78 STR	D8, [X28, X17,UXTW #3]

  (280) 0x416c7c ADD	W17, W17, #1

  (280) 0x416c80 ADD	X6, X6, #8

  (280) 0x416c84 ADD	W5, W5, #1

  (280) 0x416c88 LDR	D26, [X6]

  (280) 0x416c8c FCMPE	D6, D26

  (280) 0x416c90 B.LS	416ca4

  (280) 0x416c94 CMN	W5, #1

  (280) 0x416c98 B.EQ	416ca4

  (280) 0x416c9c STR	D26, [X28, X17,UXTW #3]

  (280) 0x416ca0 ADD	W17, W17, #1

  (280) 0x416ca4 ADD	X6, X6, #8

  (280) 0x416ca8 ADD	W5, W5, #1

  (280) 0x416cac LDR	D9, [X6]

  (280) 0x416cb0 FCMPE	D6, D9

  (280) 0x416cb4 B.LS	416cc8

  (280) 0x416cb8 CMN	W5, #1

  (280) 0x416cbc B.EQ	416cc8

  (280) 0x416cc0 STR	D9, [X28, X17,UXTW #3]

  (280) 0x416cc4 ADD	W17, W17, #1

  (280) 0x416cc8 ADD	X6, X6, #8

  (280) 0x416ccc ADD	W5, W5, #1

  (280) 0x416cd0 LDR	D10, [X6]

  (280) 0x416cd4 FCMPE	D6, D10

  (280) 0x416cd8 B.LS	416cec

  (280) 0x416cdc CMN	W5, #1

  (280) 0x416ce0 B.EQ	416cec

  (280) 0x416ce4 STR	D10, [X28, X17,UXTW #3]

  (280) 0x416ce8 ADD	W17, W17, #1

  (280) 0x416cec ADD	X6, X6, #8

  (280) 0x416cf0 ADD	W5, W5, #1

  (280) 0x416cf4 LDR	D20, [X6]

  (280) 0x416cf8 FCMPE	D6, D20

  (280) 0x416cfc B.LS	416d10

  (280) 0x416d00 CMN	W5, #1

  (280) 0x416d04 B.EQ	416d10

  (280) 0x416d08 STR	D20, [X28, X17,UXTW #3]

  (280) 0x416d0c ADD	W17, W17, #1

  (280) 0x416d10 ADD	X6, X6, #8

  (280) 0x416d14 ADD	W5, W5, #1

  (280) 0x416d18 LDR	D11, [X6]

  (280) 0x416d1c FCMPE	D6, D11

  (280) 0x416d20 B.LS	416d34

  (280) 0x416d24 CMN	W5, #1

  (280) 0x416d28 B.EQ	416d34

  (280) 0x416d2c STR	D11, [X28, X17,UXTW #3]

  (280) 0x416d30 ADD	W17, W17, #1

  (280) 0x416d34 ADD	W5, W5, #1

  (280) 0x416d38 ADD	X6, X6, #8

  (280) 0x416d3c CMP	W14, W5

  (280) 0x416d40 B.EQ	416e54

    (282) 0x416d44 LDR	D12, [X6]

    (282) 0x416d48 FCMPE	D6, D12

    (282) 0x416d4c B.LS	416d60

    (282) 0x416d50 CMN	W5, #1

    (282) 0x416d54 B.EQ	416d60

    (282) 0x416d58 STR	D12, [X28, X17,UXTW #3]

    (282) 0x416d5c ADD	W17, W17, #1

    (282) 0x416d60 LDR	D13, [X6, #8]

    (282) 0x416d64 ADD	W1, W5, #1

    (282) 0x416d68 ADD	X16, X6, #8

    (282) 0x416d6c FCMPE	D6, D13

    (282) 0x416d70 B.LS	416d84

    (282) 0x416d74 CMN	W1, #1

    (282) 0x416d78 B.EQ	416d84

    (282) 0x416d7c STR	D13, [X28, X17,UXTW #3]

    (282) 0x416d80 ADD	W17, W17, #1

    (282) 0x416d84 LDR	D16, [X16, #8]

    (282) 0x416d88 ADD	W25, W1, #1

    (282) 0x416d8c FCMPE	D6, D16

    (282) 0x416d90 B.LS	416da4

    (282) 0x416d94 CMN	W25, #1

    (282) 0x416d98 B.EQ	416da4

    (282) 0x416d9c STR	D16, [X28, X17,UXTW #3]

    (282) 0x416da0 ADD	W17, W17, #1

    (282) 0x416da4 LDR	D17, [X16, #16]

    (282) 0x416da8 ADD	W3, W1, #2

    (282) 0x416dac FCMPE	D6, D17

    (282) 0x416db0 B.LS	416dc4

    (282) 0x416db4 CMN	W3, #1

    (282) 0x416db8 B.EQ	416dc4

    (282) 0x416dbc STR	D17, [X28, X17,UXTW #3]

    (282) 0x416dc0 ADD	W17, W17, #1

    (282) 0x416dc4 LDR	D18, [X16, #24]

    (282) 0x416dc8 ADD	W0, W1, #3

    (282) 0x416dcc FCMPE	D6, D18

    (282) 0x416dd0 B.LS	416de4

    (282) 0x416dd4 CMN	W0, #1

    (282) 0x416dd8 B.EQ	416de4

    (282) 0x416ddc STR	D18, [X28, X17,UXTW #3]

    (282) 0x416de0 ADD	W17, W17, #1

    (282) 0x416de4 LDR	D22, [X16, #32]

    (282) 0x416de8 ADD	W4, W1, #4

    (282) 0x416dec FCMPE	D6, D22

    (282) 0x416df0 B.LS	416e04

    (282) 0x416df4 CMN	W4, #1

    (282) 0x416df8 B.EQ	416e04

    (282) 0x416dfc STR	D22, [X28, X17,UXTW #3]

    (282) 0x416e00 ADD	W17, W17, #1

    (282) 0x416e04 LDR	D30, [X16, #40]

    (282) 0x416e08 ADD	W2, W1, #5

    (282) 0x416e0c FCMPE	D6, D30

    (282) 0x416e10 B.LS	416e24

    (282) 0x416e14 CMN	W2, #1

    (282) 0x416e18 B.EQ	416e24

    (282) 0x416e1c STR	D30, [X28, X17,UXTW #3]

    (282) 0x416e20 ADD	W17, W17, #1

    (282) 0x416e24 LDR	D31, [X16, #48]

    (282) 0x416e28 ADD	W24, W1, #6

    (282) 0x416e2c FCMPE	D6, D31

    (282) 0x416e30 B.LS	416e44

    (282) 0x416e34 CMN	W24, #1

    (282) 0x416e38 B.EQ	416e44

    (282) 0x416e3c STR	D31, [X28, X17,UXTW #3]

    (282) 0x416e40 ADD	W17, W17, #1

    (282) 0x416e44 ADD	W5, W1, #7

    (282) 0x416e48 ADD	X6, X16, #56

    (282) 0x416e4c CMP	W14, W5

    (282) 0x416e50 B.NE	416d44

  (280) 0x416e54 CBZ	W17, 417048

  (280) 0x416e58 ADD	X8, X30, #568

  (280) 0x416e5c LD1RD	{Z3.D}, P7/Z, [X30, #3]

  (280) 0x416e60 LD1RD	{Z4.D}, P7/Z, [X30, #4]

  (280) 0x416e64 LD1RD	{Z5.D}, P7/Z, [X30, #5]

  (280) 0x416e68 LD1RD	{Z6.D}, P7/Z, [X30, #6]

  (280) 0x416e6c LD1RD	{Z7.D}, P7/Z, [X30, #7]

  (280) 0x416e70 LD1RD	{Z16.D}, P7/Z, [X30, #8]

  (280) 0x416e74 LD1RD	{Z17.D}, P7/Z, [X30, #9]

  (280) 0x416e78 LD1RD	{Z18.D}, P7/Z, [X30, #10]

  (280) 0x416e7c LD1RD	{Z19.D}, P7/Z, [X30, #11]

  (280) 0x416e80 LD1RD	{Z20.D}, P7/Z, [X30, #12]

  (280) 0x416e84 LD1RD	{Z21.D}, P7/Z, [X30, #13]

  (280) 0x416e88 LD1RD	{Z22.D}, P7/Z, [X30, #14]

  (280) 0x416e8c LD1RD	{Z23.D}, P7/Z, [X30, #15]

  (280) 0x416e90 LD1RD	{Z24.D}, P7/Z, [X30, #16]

  (280) 0x416e94 LD1RD	{Z25.D}, P7/Z, [X30, #17]

  (280) 0x416e98 LD1RD	{Z26.D}, P7/Z, [X30, #18]

  (280) 0x416e9c LDR	X30, [X30, #536]

  (280) 0x416ea0 MOVZ	X14, #0

  (280) 0x416ea4 ADDVL	X21, X28, #1

  (280) 0x416ea8 DUP	Z28.D, #0

  (280) 0x416eac ORR	W13, WZR, W17

  (280) 0x416eb0 LD1RD	{Z2.D}, P7/Z, [X8]

  (280) 0x416eb4 UQDECD	W13, ALL

  (280) 0x416eb8 ORR	Z29.D, Z28.D, Z28.D

  (280) 0x416ebc WHILELO	P5.D, WZR, W13

  (280) 0x416ec0 WHILELO	P6.D, WZR, W17

    (283) 0x416ec4 LD1D	{Z0.D}, P5/Z, [X21, X14,LSL #3]

    (283) 0x416ec8 LD1D	{Z27.D}, P6/Z, [X28, X14,LSL #3]

    (283) 0x416ecc FMUL	Z8.D, Z2.D, Z0.D

    (283) 0x416ed0 FMUL	Z14.D, Z2.D, Z27.D

    (283) 0x416ed4 MOVPRFX	Z9, Z8

    (283) 0x416ed8 FRINTZ	Z9.D, P7/M, Z8.D

    (283) 0x416edc MOVPRFX	Z10, Z8

    (283) 0x416ee0 FCVTZS	Z10.S, P7/M, Z8.D

    (283) 0x416ee4 FSUB	Z31.D, Z8.D, Z9.D

    (283) 0x416ee8 MOVPRFX	Z11, Z14

    (283) 0x416eec FCVTZS	Z11.S, P7/M, Z14.D

    (283) 0x416ef0 FMUL	Z27.D, Z31.D, Z31.D

    (283) 0x416ef4 MOVPRFX	Z8, Z18

    (283) 0x416ef8 FMLA	Z8.D, P7/M, Z17.D, Z31.D

    (283) 0x416efc FMUL	Z0.D, Z27.D, Z31.D

    (283) 0x416f00 FMUL	Z12.D, Z16.D, Z27.D

    (283) 0x416f04 FMLA	Z12.D, P7/M, Z7.D, Z0.D

    (283) 0x416f08 UZP1	Z30.S, Z11.S, Z10.S

    (283) 0x416f0c FADD	Z11.D, Z8.D, Z12.D

    (283) 0x416f10 MOVPRFX	Z13, Z30

    (283) 0x416f14 ADD	Z13.S, Z13.S, #1

    (283) 0x416f18 MOVPRFX	Z8, Z6

    (283) 0x416f1c FMLA	Z8.D, P7/M, Z5.D, Z31.D

    (283) 0x416f20 SUNPKHI	Z9.D, Z13

    (283) 0x416f24 LD1D	{Z12.D}, P5/Z, [X30, Z9.D,LSL #3]

    (283) 0x416f28 FMUL	Z10.D, Z4.D, Z27.D

    (283) 0x416f2c FMUL	Z11.D, Z11.D, Z12.D

    (283) 0x416f30 FMLA	Z10.D, P7/M, Z3.D, Z0.D

    (283) 0x416f34 SUNPKHI	Z9.D, Z30

    (283) 0x416f38 FADD	Z12.D, Z8.D, Z10.D

    (283) 0x416f3c LD1D	{Z8.D}, P5/Z, [X30, Z9.D,LSL #3]

    (283) 0x416f40 FMUL	Z10.D, Z20.D, Z27.D

    (283) 0x416f44 FMAD	Z12.D, P7/M, Z8.D, Z11.D

    (283) 0x416f48 FMLA	Z10.D, P7/M, Z19.D, Z0.D

    (283) 0x416f4c MOVPRFX	Z11, Z22

    (283) 0x416f50 FMLA	Z11.D, P7/M, Z21.D, Z31.D

    (283) 0x416f54 FMUL	Z27.D, Z27.D, Z24.D

    (283) 0x416f58 FADD	Z8.D, Z11.D, Z10.D

    (283) 0x416f5c FMAD	Z0.D, P7/M, Z23.D, Z27.D

    (283) 0x416f60 FADD	Z28.D, P5/M, Z28.D, Z12.D

    (283) 0x416f64 MOVPRFX	Z27, Z30

    (283) 0x416f68 ADD	Z27.S, Z27.S, #3

    (283) 0x416f6c MOVPRFX	Z12, Z30

    (283) 0x416f70 ADD	Z12.S, Z12.S, #2

    (283) 0x416f74 SUNPKHI	Z10.D, Z27

    (283) 0x416f78 SUNPKLO	Z30.D, Z30

    (283) 0x416f7c LD1D	{Z11.D}, P5/Z, [X30, Z10.D,LSL #3]

    (283) 0x416f80 FMAD	Z31.D, P7/M, Z25.D, Z26.D

    (283) 0x416f84 FADD	Z31.D, Z31.D, Z0.D

    (283) 0x416f88 SUNPKHI	Z0.D, Z12

    (283) 0x416f8c LD1D	{Z9.D}, P5/Z, [X30, Z0.D,LSL #3]

    (283) 0x416f90 FMLA	Z28.D, P5/M, Z8.D, Z9.D

    (283) 0x416f94 SUNPKLO	Z8.D, Z12

    (283) 0x416f98 FMLA	Z28.D, P5/M, Z11.D, Z31.D

    (283) 0x416f9c LD1D	{Z0.D}, P6/Z, [X30, Z8.D,LSL #3]

    (283) 0x416fa0 LD1D	{Z11.D}, P6/Z, [X30, Z30.D,LSL #3]

    (283) 0x416fa4 SUNPKLO	Z12.D, Z27

    (283) 0x416fa8 MOVPRFX	Z31, Z14

    (283) 0x416fac FRINTZ	Z31.D, P7/M, Z14.D

    (283) 0x416fb0 SUNPKLO	Z13.D, Z13

    (283) 0x416fb4 FSUB	Z8.D, Z14.D, Z31.D

    (283) 0x416fb8 FMUL	Z30.D, Z8.D, Z8.D

    (283) 0x416fbc FMUL	Z27.D, Z30.D, Z8.D

    (283) 0x416fc0 FMUL	Z14.D, Z16.D, Z30.D

    (283) 0x416fc4 FMLA	Z14.D, P7/M, Z7.D, Z27.D

    (283) 0x416fc8 LD1D	{Z10.D}, P6/Z, [X30, Z13.D,LSL #3]

    (283) 0x416fcc ADD	X14, X14, X9

    (283) 0x416fd0 LD1D	{Z13.D}, P6/Z, [X30, Z12.D,LSL #3]

    (283) 0x416fd4 WHILELO	P5.D, W14, W13

    (283) 0x416fd8 MOVPRFX	Z12, Z18

    (283) 0x416fdc FMLA	Z12.D, P7/M, Z17.D, Z8.D

    (283) 0x416fe0 FADD	Z31.D, Z12.D, Z14.D

    (283) 0x416fe4 MOVPRFX	Z14, Z6

    (283) 0x416fe8 FMLA	Z14.D, P7/M, Z5.D, Z8.D

    (283) 0x416fec FMUL	Z12.D, Z31.D, Z10.D

    (283) 0x416ff0 FMUL	Z9.D, Z4.D, Z30.D

    (283) 0x416ff4 FMUL	Z10.D, Z20.D, Z30.D

    (283) 0x416ff8 FMLA	Z9.D, P7/M, Z3.D, Z27.D

    (283) 0x416ffc MOVPRFX	Z31, Z22

    (283) 0x417000 FMLA	Z31.D, P7/M, Z21.D, Z8.D

    (283) 0x417004 FADD	Z9.D, Z14.D, Z9.D

    (283) 0x417008 FMUL	Z30.D, Z30.D, Z24.D

    (283) 0x41700c FMAD	Z9.D, P7/M, Z11.D, Z12.D

    (283) 0x417010 FMAD	Z8.D, P7/M, Z25.D, Z26.D

    (283) 0x417014 MOVPRFX	Z11, Z10

    (283) 0x417018 FMLA	Z11.D, P7/M, Z19.D, Z27.D

    (283) 0x41701c FADD	Z29.D, P6/M, Z29.D, Z9.D

    (283) 0x417020 FMAD	Z27.D, P7/M, Z23.D, Z30.D

    (283) 0x417024 FADD	Z14.D, Z31.D, Z11.D

    (283) 0x417028 FMLA	Z29.D, P6/M, Z14.D, Z0.D

    (283) 0x41702c FADD	Z0.D, Z8.D, Z27.D

    (283) 0x417030 FMLA	Z29.D, P6/M, Z13.D, Z0.D

    (283) 0x417034 WHILELO	P6.D, W14, W17

    (283) 0x417038 B.NE	416ec4

  (280) 0x41703c FADD	Z2.D, Z29.D, Z28.D

  (280) 0x417040 FADDV	D28, P7, Z2.D

  (280) 0x417044 FADD	D1, D1, D28

  (280) 0x417048 ADD	X7, X7, #4

  (280) 0x41704c CMP	X10, X7

  (280) 0x417050 B.NE	416bc0

0x417054 FSUB	D15, D15, S1

0x417058 FMOV	D0, D15

0x41705c ADD	X20, X20, #40

0x417060 BL	403a70

0x417064 LDR	X28, [SP, #160]

0x417068 LDP	X15, X12, [X28]

0x41706c SUB	X18, X12, X15

0x417070 STR	D0, [X15, X19,UXTW #3]

0x417074 ADD	X19, X19, #1

0x417078 CMP	X19, X18,ASR #3

0x41707c B.CC	416b70

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h: 134 - 146

--------------------------------------------------------------------------------

134:     for (int k = 0; k < ratios.size(); ++k)

135:       ratios[k] = std::exp(Vat[VP.refPtcl] - computeU(VP.getDistTableAB(myTableID).getDistRow(k).data()));

136:   }

137:

138:   inline valT computeU(const valT* dist)

139:   {

140:     valT curVat(0);

141:     if (NumGroups > 0)

142:     {

143:       for (int jg = 0; jg < NumGroups; ++jg)

144:       {

145:         if (F[jg] != nullptr)

146:           curVat += F[jg]->evaluateV(-1, Ions.first(jg), Ions.last(jg), dist, DistCompressed.data());

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 231 - 260

--------------------------------------------------------------------------------

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 1131

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	3.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	OneBodyJastrowRef.h:134-135,OneBodyJastrowRef.h:140-141,BsplineFunctor.h:246-246,OhmmsVector.h:223-223,OhmmsVector.h:249-249,stl_vector.h:993-993,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	3.21
Front-end cycles	3.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	3.83
P10 cycles	3.50
P11 cycles	3.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.26
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.91
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.81
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Metric	Value
CQA speedup if no scalar integer	3.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	OneBodyJastrowRef.h:134-135,OneBodyJastrowRef.h:140-141,BsplineFunctor.h:246-246,OhmmsVector.h:223-223,OhmmsVector.h:249-249,stl_vector.h:993-993,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	3.21
Front-end cycles	3.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	3.83
P10 cycles	3.50
P11 cycles	3.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.26
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.91
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.81
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	OneBodyJastrowRef.h:134-146
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:134-146
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1131
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/shared_ptr_base.h:1667

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 3.21 cycles (1.19x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 76 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00
cycles	2.00	2.00	3.25	3.25	3.25	3.25	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

20% of peak load performance is reached (19.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 417058

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X2, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X3, [X22, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X26, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D15, [X2, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
BL 484780 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X4, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4170ac <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X26, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
FSUB D15, D15, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D0, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X20, X20, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a70 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X12, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X18, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X15, X19,UXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X18,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.CC 416b70 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	OneBodyJastrowRef.h:134-146
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:134-146
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1131
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/shared_ptr_base.h:1667

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 3.21 cycles (1.19x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 76 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00
cycles	2.00	2.00	3.25	3.25	3.25	3.25	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

20% of peak load performance is reached (19.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 417058

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X2, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X3, [X22, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X26, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D15, [X2, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
BL 484780 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X4, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4170ac <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X26, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
FSUB D15, D15, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D0, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X20, X20, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a70 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X12, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X18, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X15, X19,UXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X18,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.CC 416b70 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code