OV - exec - Loop 197

	Loop Id: 197	Module: exec	Source: WaveFunction.cpp:269-276 [...]	Coverage: 0.01%

0x40fe00 LDR	X21, [X23]

0x40fe04 UBFM	X25, X19, #61, #60

0x40fe08 LDR	X21, [X21, X25]

0x40fe0c ORR	X0, XZR, X21

0x40fe10 BL	4c43c0

0x40fe14 LDR	X30, [X20]

0x40fe18 ADD	X2, SP, #80

0x40fe1c ORR	X1, XZR, X24

0x40fe20 LDR	X0, [X30, X25]

0x40fe24 LDR	X3, [X0]

0x40fe28 LDR	X4, [X3, #72]

0x40fe2c BLR	X4

0x40fe30 LDP	X12, X5, [X22]

0x40fe34 SUB	X6, X5, X12

0x40fe38 SBFM	X11, X6, #3, #63

0x40fe3c CMP	X12, X5

0x40fe40 B.EQ	41000c

0x40fe44 LDR	X13, [SP, #80]

0x40fe48 CMP	X6, #8

0x40fe4c B.LS	41005c

0x40fe50 ADD	X7, X13, #8

0x40fe54 CMP	X12, X7

0x40fe58 B.EQ	41005c

0x40fe5c CMP	X6, #0

0x40fe60 CSINC	X14, X11, XZR, #1

0x40fe64 UBFM	X2, X14, #1, #63

0x40fe68 UBFM	X1, X2, #60, #59

0x40fe6c MOVZ	X18, #0

0x40fe70 SUB	X8, X1, #16

0x40fe74 UBFM	X9, X8, #4, #63

0x40fe78 ADD	X10, X9, #1

0x40fe7c ANDS	X15, X10, #4224

0x40fe80 B.EQ	40ff48

0x40fe84 CMP	X15, #1

0x40fe88 B.EQ	40ff2c

0x40fe8c CMP	X15, #2

0x40fe90 B.EQ	40ff18

0x40fe94 CMP	X15, #3

0x40fe98 B.EQ	40ff04

0x40fe9c CMP	X15, #4

0x40fea0 B.EQ	40fef0

0x40fea4 CMP	X15, #5

0x40fea8 B.EQ	40fedc

0x40feac CMP	X15, #6

0x40feb0 B.EQ	40fec8

0x40feb4 LDR	Q30, [X12]

0x40feb8 MOVZ	X18, #16

0x40febc LDR	Q31, [X13]

0x40fec0 FMUL	V0.2D, V31.2D, V30.2D

0x40fec4 STR	Q0, [X12]

0x40fec8 LDR	Q29, [X13, X18]

0x40fecc LDR	Q28, [X12, X18]

0x40fed0 FMUL	V1.2D, V29.2D, V28.2D

0x40fed4 STR	Q1, [X12, X18]

0x40fed8 ADD	X18, X18, #16

0x40fedc LDR	Q27, [X13, X18]

0x40fee0 LDR	Q26, [X12, X18]

0x40fee4 FMUL	V2.2D, V27.2D, V26.2D

0x40fee8 STR	Q2, [X12, X18]

0x40feec ADD	X18, X18, #16

0x40fef0 LDR	Q25, [X13, X18]

0x40fef4 LDR	Q24, [X12, X18]

0x40fef8 FMUL	V3.2D, V25.2D, V24.2D

0x40fefc STR	Q3, [X12, X18]

0x40ff00 ADD	X18, X18, #16

0x40ff04 LDR	Q23, [X13, X18]

0x40ff08 LDR	Q22, [X12, X18]

0x40ff0c FMUL	V4.2D, V23.2D, V22.2D

0x40ff10 STR	Q4, [X12, X18]

0x40ff14 ADD	X18, X18, #16

0x40ff18 LDR	Q21, [X13, X18]

0x40ff1c LDR	Q20, [X12, X18]

0x40ff20 FMUL	V5.2D, V21.2D, V20.2D

0x40ff24 STR	Q5, [X12, X18]

0x40ff28 ADD	X18, X18, #16

0x40ff2c LDR	Q19, [X13, X18]

0x40ff30 LDR	Q18, [X12, X18]

0x40ff34 FMUL	V6.2D, V19.2D, V18.2D

0x40ff38 STR	Q6, [X12, X18]

0x40ff3c ADD	X18, X18, #16

0x40ff40 CMP	X1, X18

0x40ff44 B.EQ	40fff0

  (200) 0x40ff48 LDR	Q7, [X13, X18]

  (200) 0x40ff4c ADD	X0, X18, #16

  (200) 0x40ff50 ADD	X17, X18, #32

  (200) 0x40ff54 ADD	X16, X18, #48

  (200) 0x40ff58 ADD	X25, X18, #64

  (200) 0x40ff5c LDR	Q16, [X12, X18]

  (200) 0x40ff60 ADD	X30, X18, #80

  (200) 0x40ff64 ADD	X3, X18, #96

  (200) 0x40ff68 ADD	X4, X18, #112

  (200) 0x40ff6c FMUL	V17.2D, V7.2D, V16.2D

  (200) 0x40ff70 STR	Q17, [X12, X18]

  (200) 0x40ff74 ADD	X18, X18, #128

  (200) 0x40ff78 LDR	Q30, [X13, X0]

  (200) 0x40ff7c LDR	Q31, [X12, X0]

  (200) 0x40ff80 FMUL	V0.2D, V30.2D, V31.2D

  (200) 0x40ff84 STR	Q0, [X12, X0]

  (200) 0x40ff88 LDR	Q29, [X13, X17]

  (200) 0x40ff8c LDR	Q28, [X12, X17]

  (200) 0x40ff90 FMUL	V1.2D, V29.2D, V28.2D

  (200) 0x40ff94 STR	Q1, [X12, X17]

  (200) 0x40ff98 LDR	Q27, [X13, X16]

  (200) 0x40ff9c LDR	Q26, [X12, X16]

  (200) 0x40ffa0 FMUL	V2.2D, V27.2D, V26.2D

  (200) 0x40ffa4 STR	Q2, [X12, X16]

  (200) 0x40ffa8 LDR	Q25, [X13, X25]

  (200) 0x40ffac LDR	Q24, [X12, X25]

  (200) 0x40ffb0 FMUL	V3.2D, V25.2D, V24.2D

  (200) 0x40ffb4 STR	Q3, [X12, X25]

  (200) 0x40ffb8 LDR	Q23, [X13, X30]

  (200) 0x40ffbc LDR	Q22, [X12, X30]

  (200) 0x40ffc0 FMUL	V4.2D, V23.2D, V22.2D

  (200) 0x40ffc4 STR	Q4, [X12, X30]

  (200) 0x40ffc8 LDR	Q21, [X13, X3]

  (200) 0x40ffcc LDR	Q20, [X12, X3]

  (200) 0x40ffd0 FMUL	V5.2D, V21.2D, V20.2D

  (200) 0x40ffd4 STR	Q5, [X12, X3]

  (200) 0x40ffd8 LDR	Q19, [X13, X4]

  (200) 0x40ffdc LDR	Q18, [X12, X4]

  (200) 0x40ffe0 FMUL	V6.2D, V19.2D, V18.2D

  (200) 0x40ffe4 STR	Q6, [X12, X4]

  (200) 0x40ffe8 CMP	X1, X18

  (200) 0x40ffec B.NE	40ff48

0x40fff0 TBZ	W14, #0, 41000c

0x40fff4 AND	X5, X14, #8127

0x40fff8 UBFM	X6, X5, #61, #60

0x40fffc LDR	D7, [X12, X6]

0x410000 LDR	D16, [X13, X6]

0x410004 FMUL	D17, D7, D16

0x410008 STR	D17, [X12, X6]

  (198) 0x41000c ORR	X0, XZR, X21

  (198) 0x410010 ADD	X19, X19, #1

  (198) 0x410014 BL	4c4660

  (198) 0x410018 LDP	X21, X12, [X20]

  (198) 0x41001c SUB	X11, X12, X21

  (198) 0x410020 CMP	X19, X11,ASR #3

  (198) 0x410024 B.CC	40fe00

  (198) 0x410028 LDR	X21, [SP, #80]

  (198) 0x41002c CBZ	X21, 410044

  (198) 0x410030 LDR	X13, [SP, #96]

  (198) 0x410034 SUB	X19, X13, X21

  (198) 0x410038 ORR	X1, XZR, X19

  (198) 0x41003c ORR	X0, XZR, X21

  (198) 0x410040 BL	403d70

  (198) 0x410044 LDR	X25, [SP, #64]

  (198) 0x410048 LDP	X19, X20, [SP, #16]

  (198) 0x41004c LDP	X21, X22, [SP, #32]

  (198) 0x410050 LDP	X23, X24, [SP, #48]

  (198) 0x410054 LDP	X29, X30, [SP], #112

  (198) 0x410058 RET

  (198) 0x41005c LDR	D30, [X12]

  (198) 0x410060 SUB	X7, X11, #1

  (198) 0x410064 MOVZ	X1, #1

  (198) 0x410068 AND	X14, X7, #4224

  (198) 0x41006c LDR	D31, [X13]

  (198) 0x410070 FMUL	D0, D30, D31

  (198) 0x410074 STR	D0, [X12]

  (198) 0x410078 CMP	X11, X1

  (198) 0x41007c B.LS	41000c

  (198) 0x410080 CBZ	X14, 410134

  (198) 0x410084 CMP	X14, #1

  (198) 0x410088 B.EQ	410118

  (198) 0x41008c CMP	X14, #2

  (198) 0x410090 B.EQ	410104

  (198) 0x410094 CMP	X14, #3

  (198) 0x410098 B.EQ	4100f0

  (198) 0x41009c CMP	X14, #4

  (198) 0x4100a0 B.EQ	4100dc

  (198) 0x4100a4 CMP	X14, #5

  (198) 0x4100a8 B.EQ	4100c8

  (198) 0x4100ac CMP	X14, #6

  (198) 0x4100b0 B.NE	410234

  (198) 0x4100b4 LDR	D27, [X12, X1,LSL #3]

  (198) 0x4100b8 LDR	D26, [X13, X1,LSL #3]

  (198) 0x4100bc FMUL	D2, D27, D26

  (198) 0x4100c0 STR	D2, [X12, X1,LSL #3]

  (198) 0x4100c4 ADD	X1, X1, #1

  (198) 0x4100c8 LDR	D25, [X12, X1,LSL #3]

  (198) 0x4100cc LDR	D24, [X13, X1,LSL #3]

  (198) 0x4100d0 FMUL	D3, D25, D24

  (198) 0x4100d4 STR	D3, [X12, X1,LSL #3]

  (198) 0x4100d8 ADD	X1, X1, #1

  (198) 0x4100dc LDR	D23, [X12, X1,LSL #3]

  (198) 0x4100e0 LDR	D22, [X13, X1,LSL #3]

  (198) 0x4100e4 FMUL	D4, D23, D22

  (198) 0x4100e8 STR	D4, [X12, X1,LSL #3]

  (198) 0x4100ec ADD	X1, X1, #1

  (198) 0x4100f0 LDR	D21, [X12, X1,LSL #3]

  (198) 0x4100f4 LDR	D20, [X13, X1,LSL #3]

  (198) 0x4100f8 FMUL	D5, D21, D20

  (198) 0x4100fc STR	D5, [X12, X1,LSL #3]

  (198) 0x410100 ADD	X1, X1, #1

  (198) 0x410104 LDR	D19, [X12, X1,LSL #3]

  (198) 0x410108 LDR	D18, [X13, X1,LSL #3]

  (198) 0x41010c FMUL	D6, D19, D18

  (198) 0x410110 STR	D6, [X12, X1,LSL #3]

  (198) 0x410114 ADD	X1, X1, #1

  (198) 0x410118 LDR	D7, [X12, X1,LSL #3]

  (198) 0x41011c LDR	D16, [X13, X1,LSL #3]

  (198) 0x410120 FMUL	D17, D7, D16

  (198) 0x410124 STR	D17, [X12, X1,LSL #3]

  (198) 0x410128 ADD	X1, X1, #1

  (198) 0x41012c CMP	X11, X1

  (198) 0x410130 B.LS	41000c

    (199) 0x410134 LDR	D30, [X12, X1,LSL #3]

    (199) 0x410138 ADD	X2, X1, #1

    (199) 0x41013c ADD	X10, X1, #2

    (199) 0x410140 ADD	X9, X1, #3

    (199) 0x410144 ADD	X8, X1, #4

    (199) 0x410148 LDR	D31, [X13, X1,LSL #3]

    (199) 0x41014c ADD	X15, X1, #5

    (199) 0x410150 ADD	X18, X1, #6

    (199) 0x410154 ADD	X0, X1, #7

    (199) 0x410158 FMUL	D0, D30, D31

    (199) 0x41015c STR	D0, [X12, X1,LSL #3]

    (199) 0x410160 ADD	X1, X1, #8

    (199) 0x410164 LDR	D29, [X12, X2,LSL #3]

    (199) 0x410168 LDR	D28, [X13, X2,LSL #3]

    (199) 0x41016c FMUL	D1, D29, D28

    (199) 0x410170 STR	D1, [X12, X2,LSL #3]

    (199) 0x410174 LDR	D27, [X12, X10,LSL #3]

    (199) 0x410178 LDR	D26, [X13, X10,LSL #3]

    (199) 0x41017c FMUL	D2, D27, D26

    (199) 0x410180 STR	D2, [X12, X10,LSL #3]

    (199) 0x410184 LDR	D25, [X12, X9,LSL #3]

    (199) 0x410188 LDR	D24, [X13, X9,LSL #3]

    (199) 0x41018c FMUL	D3, D25, D24

    (199) 0x410190 STR	D3, [X12, X9,LSL #3]

    (199) 0x410194 LDR	D23, [X12, X8,LSL #3]

    (199) 0x410198 LDR	D22, [X13, X8,LSL #3]

    (199) 0x41019c FMUL	D4, D23, D22

    (199) 0x4101a0 STR	D4, [X12, X8,LSL #3]

    (199) 0x4101a4 LDR	D21, [X12, X15,LSL #3]

    (199) 0x4101a8 LDR	D20, [X13, X15,LSL #3]

    (199) 0x4101ac FMUL	D5, D21, D20

    (199) 0x4101b0 STR	D5, [X12, X15,LSL #3]

    (199) 0x4101b4 LDR	D19, [X12, X18,LSL #3]

    (199) 0x4101b8 LDR	D18, [X13, X18,LSL #3]

    (199) 0x4101bc FMUL	D6, D19, D18

    (199) 0x4101c0 STR	D6, [X12, X18,LSL #3]

    (199) 0x4101c4 LDR	D7, [X12, X0,LSL #3]

    (199) 0x4101c8 LDR	D16, [X13, X0,LSL #3]

    (199) 0x4101cc FMUL	D17, D7, D16

    (199) 0x4101d0 STR	D17, [X12, X0,LSL #3]

    (199) 0x4101d4 CMP	X11, X1

    (199) 0x4101d8 B.HI	410134

  (198) 0x4101dc B	41000c

  (198) 0x410234 LDR	D29, [X12, X1,LSL #3]

  (198) 0x410238 LDR	D28, [X13, X1,LSL #3]

  (198) 0x41023c FMUL	D1, D29, D28

  (198) 0x410240 STR	D1, [X12, X1,LSL #3]

  (198) 0x410244 MOVZ	X1, #2

  (198) 0x410248 B	4100b4

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 269 - 276

--------------------------------------------------------------------------------

269:   for (size_t i = 0; i < Jastrows.size(); i++)

270:   {

271:     ScopedTimer local_timer(jastrow_timers[i]);

272:     Jastrows[i]->evaluateRatios(VP, t);

273:     for (int j = 0; j < ratios.size(); ++j)

274:       ratios[j] *= t[j];

275:   }

276: }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h: 172 - 172

--------------------------------------------------------------------------------

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 368 - 1131

--------------------------------------------------------------------------------

368: 	_M_deallocate(_M_impl._M_start,

369: 		      _M_impl._M_end_of_storage - _M_impl._M_start);

[...]

388: 	if (__p)

[...]

992:       size() const _GLIBCXX_NOEXCEPT

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.39
CQA speedup if FP arith vectorized	1.19
CQA speedup if fully vectorized	2.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	NewTimer.h:242-242,refwrap.h:347-347,WaveFunction.cpp:272-274,stl_vector.h:992-993,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.13
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	4.46
Front-end cycles	11.13
DIV/SQRT cycles	7.00
P0 cycles	7.00
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	10.67
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.35
Nb FLOP add-sub	0.00
Nb FLOP mul	15.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.83
Bytes prefetched	0.00
Bytes loaded	312.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	59.57
Vectorization ratio load	87.50
Vectorization ratio store	87.50
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	39.89
Vector-efficiency ratio load	46.88
Vector-efficiency ratio store	46.88
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.39
CQA speedup if FP arith vectorized	1.19
CQA speedup if fully vectorized	2.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	NewTimer.h:242-242,refwrap.h:347-347,WaveFunction.cpp:272-274,stl_vector.h:992-993,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.13
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	4.46
Front-end cycles	11.13
DIV/SQRT cycles	7.00
P0 cycles	7.00
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	10.67
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.35
Nb FLOP add-sub	0.00
Nb FLOP mul	15.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.83
Bytes prefetched	0.00
Bytes loaded	312.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	59.57
Vectorization ratio load	87.50
Vectorization ratio store	87.50
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	39.89
Vector-efficiency ratio load	46.88
Vector-efficiency ratio store	46.88
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	WaveFunction.cpp:269-276
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:269-276
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h:172
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:368-369,388,992-993,1128-1131

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 8.00 cycles (1.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 39% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.13 to 4.46 cycles (2.50x speedup).

Details

59% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU loads are used in vector version.
87% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.13 to 1.00 cycles (11.12x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

15: multiply

The binary loop is loading 312 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	9.25	9.25	9.25	9.25	4.00	4.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00
cycles	7.00	7.00	9.25	9.25	9.25	9.25	4.00	4.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Overall L1	11.13

Vectorization ratios

INT

all	52%
load	87%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	59%
load	87%
store	87%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.13 cycles. At this rate:

29% of peak load performance is reached (28.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40fe00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X21, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X25, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [X21, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X2, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X30, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X3, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BLR X4	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X6, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X11, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 41000c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LS 41005c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X7, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 41005c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSINC X14, X11, XZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X2, X14, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X1, X2, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X8, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X9, X8, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X15, X10, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff48 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff2c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff18 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff04 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fef0 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fedc <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fec8 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR Q30, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q31, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V0.2D, V31.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q0, [X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR Q29, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q28, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V1.2D, V29.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q1, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q27, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q26, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V2.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q2, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q25, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q24, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V3.2D, V25.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q3, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q23, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q22, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V4.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q4, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q21, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q20, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V5.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q5, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q19, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q18, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V6.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q6, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fff0 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBZ W14, #0, 41000c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X5, X14, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X6, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X12, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X13, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D17, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D17, [X12, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50

Function	qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	WaveFunction.cpp:269-276
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:269-276
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h:172
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:368-369,388,992-993,1128-1131

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 8.00 cycles (1.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

59% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU loads are used in vector version.
87% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.13 to 1.00 cycles (11.12x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

15: multiply

The binary loop is loading 312 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	9.25	9.25	9.25	9.25	4.00	4.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00
cycles	7.00	7.00	9.25	9.25	9.25	9.25	4.00	4.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Overall L1	11.13

Vectorization ratios

INT

all	52%
load	87%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	59%
load	87%
store	87%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.13 cycles. At this rate:

29% of peak load performance is reached (28.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40fe00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X21, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X25, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [X21, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X2, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X30, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X3, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BLR X4	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X6, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X11, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 41000c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LS 41005c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X7, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 41005c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSINC X14, X11, XZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X2, X14, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X1, X2, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X8, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X9, X8, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X15, X10, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff48 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff2c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff18 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40ff04 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fef0 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fedc <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fec8 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR Q30, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q31, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V0.2D, V31.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q0, [X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR Q29, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q28, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V1.2D, V29.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q1, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q27, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q26, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V2.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q2, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q25, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q24, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V3.2D, V25.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q3, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q23, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q22, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V4.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q4, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q21, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q20, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V5.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q5, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR Q19, [X13, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q18, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V6.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR Q6, [X12, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 40fff0 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBZ W14, #0, 41000c <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X5, X14, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X6, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X12, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X13, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D17, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D17, [X12, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code