OV - exec - Loop 188

0x40f6c0 LDR	X3, [X22]    [4]

0x40f6c4 UBFM	X26, X19, #61, #60

0x40f6c8 LDR	X21, [X3, X26]    [6]

0x40f6cc ORR	X0, XZR, X21

0x40f6d0 BL	4c43c0

0x40f6d4 LDR	X8, [X20]    [3]

0x40f6d8 ORR	X3, XZR, X23

0x40f6dc ORR	W2, WZR, W24

0x40f6e0 ORR	X1, XZR, X25

0x40f6e4 LDR	X0, [X8, X26]    [2]

0x40f6e8 LDR	X9, [X0]    [1]

0x40f6ec LDR	X10, [X9, #32]    [5]

0x40f6f0 BLR	X10

0x40f6f4 FMUL	D15, D15, D0

0x40f6f8 ORR	X0, XZR, X21

0x40f6fc ADD	X19, X19, #1

0x40f700 BL	4c4660

0x40f704 LDP	X11, X12, [X20]    [3]

0x40f708 SUB	X13, X12, X11

0x40f70c CMP	X19, X13,ASR #3

0x40f710 B.CC	40f6c0

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 198 - 201

--------------------------------------------------------------------------------

198:   for (size_t i = 0; i < Jastrows.size(); i++)

199:   {

200:     ScopedTimer local_timer(jastrow_timers[i]);

201:     ratio *= Jastrows[i]->ratioGrad(P, iat, grad);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 993

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P2, P3, P4, P5,
Function	qmcplusplus::WaveFunction::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	NewTimer.h:242-242,NewTimer.h:249-249,refwrap.h:347-347,WaveFunction.cpp:198-201,stl_vector.h:993-993
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.41
Front-end cycles	2.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.25
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.33
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P2, P3, P4, P5,
Function	qmcplusplus::WaveFunction::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	NewTimer.h:242-242,NewTimer.h:249-249,refwrap.h:347-347,WaveFunction.cpp:198-201,stl_vector.h:993-993
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.41
Front-end cycles	2.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.25
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.33
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::WaveFunction::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	WaveFunction.cpp:198-201
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:198-201
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.00	3.00	3.00	3.00	0.25	0.25	0.25	0.25	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	3.00	3.00	3.00	3.00	0.25	0.25	0.25	0.25	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	2.63
Data deps.	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40f6c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X3, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X26, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [X3, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X3, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BLR X10	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D15, D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X13, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X19, X13,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
B.CC 40f6c0 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::WaveFunction::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	WaveFunction.cpp:198-201
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:198-201
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.00	3.00	3.00	3.00	0.25	0.25	0.25	0.25	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	3.00	3.00	3.00	3.00	0.25	0.25	0.25	0.25	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	2.63
Data deps.	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40f6c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X3, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X26, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [X3, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X3, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BLR X10	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D15, D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X13, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X19, X13,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
B.CC 40f6c0 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code