OV - exec - Loop 186

0x40f580 UBFM	X22, X19, #61, #60

0x40f584 LDR	X7, [X23]    [6]

0x40f588 LDR	X21, [X7, X22]    [2]

0x40f58c ORR	X0, XZR, X21

0x40f590 BL	4c43c0

0x40f594 LDR	X8, [X20]    [4]

0x40f598 ORR	W2, WZR, W24

0x40f59c ORR	X1, XZR, X25

0x40f5a0 LDR	X0, [X8, X22]    [1]

0x40f5a4 LDR	X9, [X0]    [7]

0x40f5a8 LDR	X10, [X9, #24]    [5]

0x40f5ac BLR	X10

0x40f5b0 FADD	D15, D15, D0

0x40f5b4 FADD	D14, D14, D1

0x40f5b8 ORR	X0, XZR, X21

0x40f5bc FADD	D13, D13, D2

0x40f5c0 STP	D0, D1, [SP, #160]    [3]

0x40f5c4 ADD	X19, X19, #1

0x40f5c8 STR	D2, [SP, #176]    [3]

0x40f5cc BL	4c4660

0x40f5d0 LDP	X11, X12, [X20]    [4]

0x40f5d4 SUB	X13, X12, X11

0x40f5d8 CMP	X19, X13,ASR #3

0x40f5dc B.CC	40f580

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 185 - 188

--------------------------------------------------------------------------------

185:   for (size_t i = 0; i < Jastrows.size(); i++)

186:   {

187:     ScopedTimer local_timer(jastrow_timers[i]);

188:     grad_iat += Jastrows[i]->evalGrad(P, iat);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 94 - 94

--------------------------------------------------------------------------------

94:     (const_cast<T1&>(a) += b);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 1128

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue, P10, P11, P12,
Function	qmcplusplus::WaveFunction::evalGrad(qmcplusplus::ParticleSet&, int)
Source	NewTimer.h:242-242,NewTimer.h:249-249,refwrap.h:347-347,WaveFunction.cpp:185-188,OperatorTags.h:94-94,stl_vector.h:993-993,stl_vector.h:1128-1128
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.54
Front-end cycles	3.00
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	1.25
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.00
Vectorization ratio load	NA
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.13
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue, P10, P11, P12,
Function	qmcplusplus::WaveFunction::evalGrad(qmcplusplus::ParticleSet&, int)
Source	NewTimer.h:242-242,NewTimer.h:249-249,refwrap.h:347-347,WaveFunction.cpp:185-188,OperatorTags.h:94-94,stl_vector.h:993-993,stl_vector.h:1128-1128
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.54
Front-end cycles	3.00
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	1.25
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.00
Vectorization ratio load	NA
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.13
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::WaveFunction::evalGrad(qmcplusplus::ParticleSet&, int)
Source file and lines	WaveFunction.cpp:185-188
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:185-188
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1128

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.54 cycles (5.54x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU stores are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 64 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.75	2.75	2.75	2.75	1.25	1.25	1.25	1.25	3.00	3.00	3.00	0.00	0.00
cycles	2.00	2.00	2.75	2.75	2.75	2.75	1.25	1.25	1.25	1.25	3.00	3.00	3.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	3.00

Vectorization ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40f580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
UBFM X22, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X7, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X21, [X7, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W2, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X9, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BLR X10	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
FADD D15, D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D14, D14, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D13, D13, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STP D0, D1, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D2, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X13, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X19, X13,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
B.CC 40f580 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::WaveFunction::evalGrad(qmcplusplus::ParticleSet&, int)
Source file and lines	WaveFunction.cpp:185-188
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:185-188
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1128

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.54 cycles (5.54x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU stores are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 64 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.75	2.75	2.75	2.75	1.25	1.25	1.25	1.25	3.00	3.00	3.00	0.00	0.00
cycles	2.00	2.00	2.75	2.75	2.75	2.75	1.25	1.25	1.25	1.25	3.00	3.00	3.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	3.00

Vectorization ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40f580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
UBFM X22, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X7, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X21, [X7, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W2, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X9, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BLR X10	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
FADD D15, D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D14, D14, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D13, D13, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STP D0, D1, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D2, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X13, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X19, X13,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
B.CC 40f580 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code