OV - exec - Loop 1407

0x468538 ADD	X10, X2, X0

0x46853c LDR	D29, [X2]    [6]

0x468540 ORR	X3, XZR, X17

0x468544 ADD	X7, X10, X0

0x468548 ADD	X17, X17, #64

0x46854c ADD	X8, X7, X0

0x468550 LDR	D6, [X2, X0]    [4]

0x468554 ADD	X9, X8, X0

0x468558 ADD	X24, X9, X0

0x46855c LDR	D30, [X10, X0]    [8]

0x468560 ADD	X11, X24, X0

0x468564 LDR	D28, [X24, X0]    [5]

0x468568 ADD	X2, X11, X0,LSL #1

0x46856c STR	D29, [X3], #8    [10]

0x468570 LDR	D15, [X9, X0]    [3]

0x468574 STUR	D6, [X17, #456]    [7]

0x468578 STR	D30, [X3, #8]    [10]

0x46857c LDR	D7, [X11, X0]    [2]

0x468580 LDR	D16, [X8, X0]    [9]

0x468584 STP	D15, D28, [X17, #1000]    [7]

0x468588 LDR	D17, [X7, X0]    [1]

0x46858c STUR	D7, [X17, #504]    [7]

0x468590 STP	D17, D16, [X17, #984]    [7]

0x468594 CMP	X17, X4

0x468598 B.NE	468538

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 211 - 212

--------------------------------------------------------------------------------

211:     for (size_t j = 0; j < m; ++j)

212:       B[i * ldb + j] = A[j * lda + i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.89
Front-end cycles	3.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.89
Front-end cycles	3.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines	inner_product.hpp:211-212
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:211-212.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.89 cycles (3.70x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	3.13
Data deps.	7.00
Overall L1	7.00

Vectorization ratios

all	14%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 468538

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X10, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D29, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X3, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X17, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X2, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X9, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X24, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D30, [X10, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X11, X24, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D28, [X24, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X11, X0,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D29, [X3], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D15, [X9, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D6, [X17, #456]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D30, [X3, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D7, [X11, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X8, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D15, D28, [X17, #1000]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D17, [X7, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D7, [X17, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D17, D16, [X17, #984]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 468538 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines	inner_product.hpp:211-212
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:211-212.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.89 cycles (3.70x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	3.13
Data deps.	7.00
Overall L1	7.00

Vectorization ratios

all	14%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 468538

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X10, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D29, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X3, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X17, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X2, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X9, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X24, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D30, [X10, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X11, X24, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D28, [X24, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X11, X0,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D29, [X3], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D15, [X9, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D6, [X17, #456]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D30, [X3, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D7, [X11, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X8, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D15, D28, [X17, #1000]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D17, [X7, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D7, [X17, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D17, D16, [X17, #984]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 468538 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code