OV - exec - Loop 1187

	Loop Id: 1187	Module: exec	Source: einspline_spo_ref.hpp:223-227 [...]	Coverage: 0.14%

0x454710 LDR	D26, [X8, X0,LSL #3]    [19]

0x454714 ADD	X2, X0, #1

0x454718 ADD	X30, X1, #24

0x45471c ADD	X5, X0, #2

0x454720 ADD	X28, X1, #48

0x454724 ADD	X3, X0, #3

0x454728 ADD	X27, X1, #72

0x45472c ADD	X1, X1, #96

0x454730 STR	D26, [X12, X0,LSL #3]    [25]

0x454734 LDR	D30, [X6, X0,LSL #3]    [8]

0x454738 LDR	D24, [X11, X0,LSL #3]    [22]

0x45473c LDR	D27, [X10, X0,LSL #3]    [5]

0x454740 STP	D30, D24, [X1, #928]    [12]

0x454744 STUR	D27, [X1, #432]    [12]

0x454748 LDR	D2, [X7, X0,LSL #3]    [9]

0x45474c STR	D2, [X9, X0,LSL #3]    [13]

0x454750 ADD	X0, X0, #4

0x454754 LDR	D16, [X8, X2,LSL #3]    [1]

0x454758 STR	D16, [X12, X2,LSL #3]    [29]

0x45475c LDR	D17, [X6, X2,LSL #3]    [2]

0x454760 LDR	D18, [X11, X2,LSL #3]    [32]

0x454764 LDR	D20, [X10, X2,LSL #3]    [7]

0x454768 STUR	D17, [X1, #440]    [12]

0x45476c STP	D18, D20, [X30, #8]    [16]

0x454770 LDR	D1, [X7, X2,LSL #3]    [21]

0x454774 STR	D1, [X9, X2,LSL #3]    [26]

0x454778 LDR	D31, [X8, X5,LSL #3]    [14]

0x45477c STR	D31, [X12, X5,LSL #3]    [10]

0x454780 LDR	D22, [X6, X5,LSL #3]    [15]

0x454784 LDR	D25, [X11, X5,LSL #3]    [11]

0x454788 LDR	D3, [X10, X5,LSL #3]    [20]

0x45478c STUR	D22, [X1, #464]    [12]

0x454790 STP	D25, D3, [X28, #8]    [30]

0x454794 LDR	D4, [X7, X5,LSL #3]    [3]

0x454798 STR	D4, [X9, X5,LSL #3]    [6]

0x45479c LDR	D5, [X8, X3,LSL #3]    [24]

0x4547a0 STR	D5, [X12, X3,LSL #3]    [17]

0x4547a4 LDR	D19, [X11, X3,LSL #3]    [18]

0x4547a8 LDR	D6, [X10, X3,LSL #3]    [4]

0x4547ac LDR	D7, [X6, X3,LSL #3]    [27]

0x4547b0 STUR	D7, [X1, #488]    [12]

0x4547b4 STP	D19, D6, [X27, #8]    [28]

0x4547b8 LDR	D21, [X7, X3,LSL #3]    [23]

0x4547bc STR	D21, [X9, X3,LSL #3]    [31]

0x4547c0 CMP	X13, X0

0x4547c4 B.NE	454710

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 223 - 227

--------------------------------------------------------------------------------

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:223-227,TinyVector.h:145-145
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	3.33
Front-end cycles	5.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	160.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	27.78
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:223-227,TinyVector.h:145-145
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	3.33
Front-end cycles	5.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	160.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	27.78
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 3.33 cycles (3.60x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 160 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.75
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 454710

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
LDR D26, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X28, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X1, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D26, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D30, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D24, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D27, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D30, D24, [X1, #928]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STUR D27, [X1, #432]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D2, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D2, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X8, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D16, [X12, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D17, [X6, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D20, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D17, [X1, #440]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D18, D20, [X30, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X7, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D1, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D31, [X8, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D31, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D22, [X6, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D22, [X1, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D25, D3, [X28, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D4, [X7, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D4, [X9, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D5, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D19, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D7, [X1, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D19, D6, [X27, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D21, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D21, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 454710 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 160 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.75
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 454710

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
LDR D26, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X28, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X1, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D26, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D30, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D24, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D27, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D30, D24, [X1, #928]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STUR D27, [X1, #432]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D2, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D2, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X8, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D16, [X12, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D17, [X6, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D20, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D17, [X1, #440]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D18, D20, [X30, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X7, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D1, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D31, [X8, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D31, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D22, [X6, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D22, [X1, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D25, D3, [X28, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D4, [X7, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D4, [X9, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D5, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D19, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D7, [X1, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D19, D6, [X27, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D21, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D21, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 454710 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code