OV - exec - Loop 1186

	Loop Id: 1186	Module: exec	Source: einspline_spo_ref.hpp:219-227 [...]	Coverage: 0.01%

0x454608 CMP	W14, W24

0x45460c CSEL	W27, W14, W24, #13

0x454610 CMP	W15, W27

0x454614 B.GE	4547c8

0x454618 LDR	X5, [X19, #808]

0x45461c SUB	W13, W27, W15

0x454620 MOVZ	X0, #0

0x454624 ANDS	X30, X13, #4160

0x454628 LDR	X9, [X19, #832]

0x45462c LDR	X28, [X19, #784]

0x454630 ADD	X3, X5, X17

0x454634 LDRSW	X1, [X3, #8]

0x454638 ADD	X6, X9, X17

0x45463c LDR	X7, [X6, #24]

0x454640 LDR	X8, [X28, X16]

0x454644 UBFM	X27, X1, #61, #60

0x454648 UBFM	X2, X1, #60, #59

0x45464c LDR	X6, [X3, #24]

0x454650 LDR	X5, [X21, #24]

0x454654 LDR	X3, [X20, #24]

0x454658 ADD	X11, X6, X27

0x45465c ADD	X10, X6, X2

0x454660 LDR	X28, [X22, #24]

0x454664 ADD	X1, X5, X18

0x454668 ADD	X9, X3, X4

0x45466c ADD	X12, X28, X4

0x454670 B.EQ	454710

0x454674 CMP	X30, #1

0x454678 B.EQ	4546dc

0x45467c CMP	X30, #2

0x454680 B.EQ	4546b0

0x454684 LDR	D1, [X8]

0x454688 MOVZ	X0, #1

0x45468c ADD	X1, X1, #24

0x454690 STR	D1, [X28, X4]

0x454694 LDR	D25, [X6]

0x454698 LDR	D31, [X6, X27]

0x45469c LDR	D22, [X6, X2]

0x4546a0 STR	D25, [X5, X18]

0x4546a4 STP	D31, D22, [X1, #1008]

0x4546a8 LDR	D3, [X7]

0x4546ac STR	D3, [X3, X4]

0x4546b0 LDR	D4, [X8, X0,LSL #3]

0x4546b4 ADD	X1, X1, #24

0x4546b8 STR	D4, [X12, X0,LSL #3]

0x4546bc LDR	D5, [X6, X0,LSL #3]

0x4546c0 LDR	D7, [X11, X0,LSL #3]

0x4546c4 LDR	D19, [X10, X0,LSL #3]

0x4546c8 STP	D5, D7, [X1, #1000]

0x4546cc STUR	D19, [X1, #504]

0x4546d0 LDR	D6, [X7, X0,LSL #3]

0x4546d4 STR	D6, [X9, X0,LSL #3]

0x4546d8 ADD	X0, X0, #1

0x4546dc LDR	D21, [X8, X0,LSL #3]

0x4546e0 ADD	X1, X1, #24

0x4546e4 STR	D21, [X12, X0,LSL #3]

0x4546e8 LDR	D23, [X6, X0,LSL #3]

0x4546ec LDR	D28, [X11, X0,LSL #3]

0x4546f0 LDR	D29, [X10, X0,LSL #3]

0x4546f4 STP	D23, D28, [X1, #1000]

0x4546f8 STUR	D29, [X1, #504]

0x4546fc LDR	D0, [X7, X0,LSL #3]

0x454700 STR	D0, [X9, X0,LSL #3]

0x454704 ADD	X0, X0, #1

0x454708 CMP	X13, X0

0x45470c B.EQ	4547c8

  (1187) 0x454710 LDR	D26, [X8, X0,LSL #3]

  (1187) 0x454714 ADD	X2, X0, #1

  (1187) 0x454718 ADD	X30, X1, #24

  (1187) 0x45471c ADD	X5, X0, #2

  (1187) 0x454720 ADD	X28, X1, #48

  (1187) 0x454724 ADD	X3, X0, #3

  (1187) 0x454728 ADD	X27, X1, #72

  (1187) 0x45472c ADD	X1, X1, #96

  (1187) 0x454730 STR	D26, [X12, X0,LSL #3]

  (1187) 0x454734 LDR	D30, [X6, X0,LSL #3]

  (1187) 0x454738 LDR	D24, [X11, X0,LSL #3]

  (1187) 0x45473c LDR	D27, [X10, X0,LSL #3]

  (1187) 0x454740 STP	D30, D24, [X1, #928]

  (1187) 0x454744 STUR	D27, [X1, #432]

  (1187) 0x454748 LDR	D2, [X7, X0,LSL #3]

  (1187) 0x45474c STR	D2, [X9, X0,LSL #3]

  (1187) 0x454750 ADD	X0, X0, #4

  (1187) 0x454754 LDR	D16, [X8, X2,LSL #3]

  (1187) 0x454758 STR	D16, [X12, X2,LSL #3]

  (1187) 0x45475c LDR	D17, [X6, X2,LSL #3]

  (1187) 0x454760 LDR	D18, [X11, X2,LSL #3]

  (1187) 0x454764 LDR	D20, [X10, X2,LSL #3]

  (1187) 0x454768 STUR	D17, [X1, #440]

  (1187) 0x45476c STP	D18, D20, [X30, #8]

  (1187) 0x454770 LDR	D1, [X7, X2,LSL #3]

  (1187) 0x454774 STR	D1, [X9, X2,LSL #3]

  (1187) 0x454778 LDR	D31, [X8, X5,LSL #3]

  (1187) 0x45477c STR	D31, [X12, X5,LSL #3]

  (1187) 0x454780 LDR	D22, [X6, X5,LSL #3]

  (1187) 0x454784 LDR	D25, [X11, X5,LSL #3]

  (1187) 0x454788 LDR	D3, [X10, X5,LSL #3]

  (1187) 0x45478c STUR	D22, [X1, #464]

  (1187) 0x454790 STP	D25, D3, [X28, #8]

  (1187) 0x454794 LDR	D4, [X7, X5,LSL #3]

  (1187) 0x454798 STR	D4, [X9, X5,LSL #3]

  (1187) 0x45479c LDR	D5, [X8, X3,LSL #3]

  (1187) 0x4547a0 STR	D5, [X12, X3,LSL #3]

  (1187) 0x4547a4 LDR	D19, [X11, X3,LSL #3]

  (1187) 0x4547a8 LDR	D6, [X10, X3,LSL #3]

  (1187) 0x4547ac LDR	D7, [X6, X3,LSL #3]

  (1187) 0x4547b0 STUR	D7, [X1, #488]

  (1187) 0x4547b4 STP	D19, D6, [X27, #8]

  (1187) 0x4547b8 LDR	D21, [X7, X3,LSL #3]

  (1187) 0x4547bc STR	D21, [X9, X3,LSL #3]

  (1187) 0x4547c0 CMP	X13, X0

  (1187) 0x4547c4 B.NE	454710

0x4547c8 LDR	X13, [SP, #168]

0x4547cc ADD	X16, X16, #24

0x4547d0 ADD	W14, W14, W26

0x4547d4 ADD	W15, W15, W25

0x4547d8 ADD	X17, X17, #40

0x4547dc ADD	X18, X18, X23

0x4547e0 ADD	X4, X4, X13

0x4547e4 CMP	X23, X16

0x4547e8 B.NE	454608

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 219 - 227

--------------------------------------------------------------------------------

219:     for (int i = 0; i < nBlocks; ++i)

220:     {

221:       // in real simulation, phase needs to be applied. Here just fake computation

222:       const int first = i * nBlocks;

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1131 - 1131

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.41
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:219-219,einspline_spo_ref.hpp:223-227,VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,OhmmsVector.h:223-223,stl_algobase.h:238-238,TinyVector.h:145-145,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.67
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	12.67
CQA cycles if fully vectorized	2.96
Front-end cycles	9.38
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	7.75
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.67
P10 cycles	12.67
P11 cycles	12.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.58
Bytes prefetched	0.00
Bytes loaded	204.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.34
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	15.63
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.41
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:219-219,einspline_spo_ref.hpp:223-227,VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,OhmmsVector.h:223-223,stl_algobase.h:238-238,TinyVector.h:145-145,stl_vector.h:1131-1131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.67
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	12.67
CQA cycles if fully vectorized	2.96
Front-end cycles	9.38
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	7.75
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.67
P10 cycles	12.67
P11 cycles	12.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.58
Bytes prefetched	0.00
Bytes loaded	204.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.34
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	15.63
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:219-227
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:219-227
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1131

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.67 to 9.00 cycles (1.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.67 to 2.96 cycles (4.28x speedup).

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 204 bytes. The binary loop is storing 120 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	6.00	6.00	0.00	0.00	12.67	12.67	12.67	0.00	0.00
cycles	3.00	3.00	7.75	7.75	7.75	7.75	6.00	6.00	0.00	0.00	12.67	12.67	12.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Overall L1	12.67

Vectorization ratios

all	8%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.67 cycles. At this rate:

16% of peak load performance is reached (16.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 454608

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W14, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W27, W14, W24, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W15, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4547c8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X19, #808]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W13, W27, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X30, X13, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
LDR X9, [X19, #832]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X28, [X19, #784]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X3, X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDRSW X1, [X3, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X6, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X28, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X27, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X2, X1, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X3, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X21, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X3, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X11, X6, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X22, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X28, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 454710 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4546dc <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xabc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4546b0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xa90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X28, X4]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D25, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D31, [X6, X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X6, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D25, [X5, X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D31, D22, [X1, #1008]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D3, [X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X3, X4]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D4, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D19, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D5, D7, [X1, #1000]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STUR D19, [X1, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D6, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D6, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D21, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D21, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D23, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D28, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D29, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D23, D28, [X1, #1000]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STUR D29, [X1, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D0, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4547c8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X16, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W14, W14, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W15, W15, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X17, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X23, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 454608 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x9e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:219-227
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:219-227
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1131

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.67 to 9.00 cycles (1.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 204 bytes. The binary loop is storing 120 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	6.00	6.00	0.00	0.00	12.67	12.67	12.67	0.00	0.00
cycles	3.00	3.00	7.75	7.75	7.75	7.75	6.00	6.00	0.00	0.00	12.67	12.67	12.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Overall L1	12.67

Vectorization ratios

all	8%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.67 cycles. At this rate:

16% of peak load performance is reached (16.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 454608

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W14, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W27, W14, W24, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W15, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4547c8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X19, #808]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W13, W27, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X30, X13, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
LDR X9, [X19, #832]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X28, [X19, #784]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X3, X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDRSW X1, [X3, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X6, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X28, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X27, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X2, X1, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X3, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X21, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X3, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X11, X6, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X22, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X28, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 454710 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4546dc <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xabc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4546b0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xa90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X28, X4]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D25, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D31, [X6, X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X6, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D25, [X5, X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D31, D22, [X1, #1008]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D3, [X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X3, X4]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D4, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D19, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D5, D7, [X1, #1000]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STUR D19, [X1, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D6, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D6, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D21, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D21, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D23, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D28, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D29, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D23, D28, [X1, #1000]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STUR D29, [X1, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D0, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4547c8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X16, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W14, W14, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W15, W15, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X17, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X23, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 454608 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x9e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code