OV - exec - Loop 1185

0x45428c UBFM	X18, X13, #61, #60

0x454290 UBFM	X9, X8, #61, #60

0x454294 ADD	X5, X15, X18

0x454298 ADD	X0, X30, X18

0x45429c LDR	X1, [SP, #184]

0x4542a0 ADD	X4, X16, X18

0x4542a4 ADD	X3, X9, X17

0x4542a8 MOVZ	X6, #1

0x4542ac LDR	X18, [SP, #176]

0x4542b0 LDUR	D4, [X5, #504]

0x4542b4 LDUR	D5, [X0, #504]

0x4542b8 LDUR	D3, [X4, #504]

0x4542bc ADD	X4, X1, X9

0x4542c0 ADD	X1, X18, X9

  (1184) 0x4542c4 UBFM	X5, X6, #61, #60

  (1184) 0x4542c8 MOVZ	X0, #0

  (1184) 0x4542cc ADD	X9, X10, X5

  (1184) 0x4542d0 ADD	X18, X11, X5

  (1184) 0x4542d4 ADD	X5, X14, X5

  (1184) 0x4542d8 LDUR	D25, [X9, #504]

  (1184) 0x4542dc ADD	X9, X3, X12

  (1184) 0x4542e0 LDUR	D28, [X18, #504]

  (1184) 0x4542e4 LDUR	D22, [X5, #504]

  (1184) 0x4542e8 FMUL	D19, D4, D25

  (1184) 0x4542ec FMUL	D6, D3, D28

  (1184) 0x4542f0 FMUL	D21, D28, D4

  (1184) 0x4542f4 FMUL	D23, D28, D5

  (1184) 0x4542f8 FMUL	D20, D5, D22

  (1184) 0x4542fc FMUL	D22, D5, D25

    (1183) 0x454300 LDR	D2, [X3, X0]

    (1183) 0x454304 LDR	D29, [X1, X0]

    (1183) 0x454308 LDR	D0, [X9, X0]

    (1183) 0x45430c LDR	D26, [X4, X0]

    (1183) 0x454310 FMUL	D30, D2, D7

    (1183) 0x454314 FMUL	D24, D2, D16

    (1183) 0x454318 FMUL	D27, D2, D9

    (1183) 0x45431c FMUL	D2, D29, D17

    (1183) 0x454320 LDR	D25, [X19, X0]

    (1183) 0x454324 FMUL	D28, D29, D10

    (1183) 0x454328 FMUL	D29, D29, D15

    (1183) 0x45432c FMADD	D30, D0, D11, D30

    (1183) 0x454330 FMADD	D24, D0, D14, D24

    (1183) 0x454334 FMADD	D27, D0, D13, D27

    (1183) 0x454338 LDR	D0, [X20, X0]

    (1183) 0x45433c FMADD	D2, D26, D8, D2

    (1183) 0x454340 FMADD	D28, D26, D18, D28

    (1183) 0x454344 FMADD	D29, D26, D12, D29

    (1183) 0x454348 LDR	D26, [X28, X0]

    (1183) 0x45434c FADD	D30, D30, D2

    (1183) 0x454350 FADD	D24, D28, D24

    (1183) 0x454354 FADD	D2, D27, D29

    (1183) 0x454358 FMADD	D25, D6, D30, D25

    (1183) 0x45435c FMADD	D27, D21, D30, D0

    (1183) 0x454360 FMADD	D28, D23, D30, D26

    (1183) 0x454364 STR	D25, [X19, X0]

    (1183) 0x454368 LDR	D29, [X22, X0]

    (1183) 0x45436c STR	D27, [X20, X0]

    (1183) 0x454370 LDR	D0, [X23, X0]

    (1183) 0x454374 STR	D28, [X28, X0]

    (1183) 0x454378 FMADD	D25, D19, D30, D29

    (1183) 0x45437c FMADD	D26, D22, D30, D0

    (1183) 0x454380 STR	D25, [X22, X0]

    (1183) 0x454384 LDR	D27, [X25, X0]

    (1183) 0x454388 STR	D26, [X23, X0]

    (1183) 0x45438c LDR	D28, [X26, X0]

    (1183) 0x454390 FMADD	D29, D21, D24, D27

    (1183) 0x454394 FMADD	D0, D23, D24, D28

    (1183) 0x454398 STR	D29, [X25, X0]

    (1183) 0x45439c LDR	D25, [X21, X0]

    (1183) 0x4543a0 STR	D0, [X26, X0]

    (1183) 0x4543a4 FMADD	D30, D20, D30, D25

    (1183) 0x4543a8 STR	D30, [X21, X0]

    (1183) 0x4543ac LDR	D26, [X24, X0]

    (1183) 0x4543b0 FMADD	D24, D22, D24, D26

    (1183) 0x4543b4 STR	D24, [X24, X0]

    (1183) 0x4543b8 LDR	D27, [X27, X0]

    (1183) 0x4543bc FMADD	D2, D23, D2, D27

    (1183) 0x4543c0 STR	D2, [X27, X0]

    (1183) 0x4543c4 ADD	X0, X0, #8

    (1183) 0x4543c8 CMP	X2, X0

    (1183) 0x4543cc B.NE	454300

  (1184) 0x4543d0 ADD	X6, X6, #1

  (1184) 0x4543d4 ADD	X3, X3, X7

  (1184) 0x4543d8 ADD	X4, X4, X7

  (1184) 0x4543dc ADD	X1, X1, X7

  (1184) 0x4543e0 CMP	X6, #5

  (1184) 0x4543e4 B.NE	4542c4

0x4543e8 LDR	X3, [SP, #168]

0x4543ec ADD	X13, X13, #1

0x4543f0 ADD	X8, X8, X3

0x4543f4 CMP	X13, #5

0x4543f8 B.NE	45428c

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 226 - 262

--------------------------------------------------------------------------------

226:   for (int i = 0; i < 4; i++)

227:     for (int j = 0; j < 4; j++)

228:     {

229:       const T* restrict coefs    = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

230:       const T* restrict coefszs  = coefs + zs;

231:       const T* restrict coefs2zs = coefs + 2 * zs;

232:       const T* restrict coefs3zs = coefs + 3 * zs;

233:

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:226-226,MultiBsplineRef.hpp:234-236
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:226-226,MultiBsplineRef.hpp:234-236
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:226-262
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:226-262.

Analyzed code is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:226,234-236.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45428c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X9, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X15, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR D4, [X5, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D5, [X0, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D3, [X4, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 45428c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:226-262
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:226-262.

Analyzed code is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:226,234-236.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45428c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X9, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X15, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR D4, [X5, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D5, [X0, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D3, [X4, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 45428c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code