OV - exec - Loop 1144

0x451594 LDR	W5, [X23, #64]    [3]

0x451598 MADD	W1, W11, W19, WZR

0x45159c ADD	W19, W19, #1

0x4515a0 LDR	W6, [X23, #8]    [3]

0x4515a4 MADD	W12, W19, W5, WZR

0x4515a8 CMP	W12, W6

0x4515ac CSEL	W10, W12, W6, #13

0x4515b0 SUB	W9, W10, W1

0x4515b4 CMP	W9, #0

0x4515b8 B.LE	4515e4

0x4515bc LDR	X7, [X21, #24]    [5]

0x4515c0 UBFM	X8, X1, #61, #31

0x4515c4 UBFM	X2, X9, #61, #31

0x4515c8 LDR	X3, [X23, #784]    [3]

0x4515cc ADD	X0, X7, X8

0x4515d0 LDR	X1, [X3, X22]    [2]

0x4515d4 CMP	X2, #8

0x4515d8 B.EQ	4516c0

0x4515dc BL	403a40

0x4515e0 LDR	W11, [X23, #48]    [3]

0x4515e4 ADD	X22, X22, #24

0x4515e8 CMP	W19, W11

0x4515ec B.LT	451594

0x4516c0 LDR	D6, [X1]    [4]

0x4516c4 STR	D6, [X7, X8]    [1]

0x4516c8 B	4515e4

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 183 - 187

--------------------------------------------------------------------------------

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 238 - 452

--------------------------------------------------------------------------------

238:       if (__b < __a)

[...]

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1263 - 1263

--------------------------------------------------------------------------------

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:183-187,stl_algobase.h:238-238,stl_algobase.h:413-413,stl_algobase.h:451-452,stl_vector.h:1263-1263,stl_algo.h:683-683,stl_algo.h:709-709
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.43
Front-end cycles	2.50
DIV/SQRT cycles	1.67
P0 cycles	1.67
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.17
P6 cycles	0.17
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.72
P10 cycles	1.61
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.33
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.54
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	2.67
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.47
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.28

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:183-187,stl_algobase.h:238-238,stl_algobase.h:413-413,stl_algobase.h:451-452,stl_vector.h:1263-1263,stl_algo.h:683-683,stl_algo.h:709-709
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.31
Front-end cycles	1.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.56
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:183-187,stl_algobase.h:238-238,stl_algobase.h:413-413,stl_algobase.h:451-452,stl_vector.h:1263-1263,stl_algo.h:683-683,stl_algo.h:709-709
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.50
Front-end cycles	2.88
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.29
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.07
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	3.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:183-187,stl_algobase.h:238-238,stl_algobase.h:413-413,stl_algobase.h:451-452,stl_vector.h:1263-1263,stl_algo.h:683-683,stl_algo.h:709-709
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.47
Front-end cycles	3.00
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.50
P10 cycles	2.17
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.77
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238,413,451-452
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1263
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 16% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.43 cycles (7.02x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes. The binary loop is storing 2 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.67	1.67	3.00	3.00	3.00	3.00	0.17	0.17	0.00	0.00	1.72	1.61	1.67	0.00	0.00
cycles	1.67	1.67	3.00	3.00	3.00	3.00	0.17	0.17	0.00	0.00	1.72	1.61	1.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.50
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

9% of peak load performance is reached (8.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238,413,451-452
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1263
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.31 cycles (7.20x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	13
loop length	52
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451594

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR W5, [X23, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W1, W11, W19, WZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W6, [X23, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W12, W19, W5, WZR	1	0	0	0	0	1	0	0	0	0	2	1
CMP W12, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W10, W12, W6, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W9, W10, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 4515e4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X22, X22, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 451594 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238,413,451-452
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1263
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 16% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.50 cycles (7.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.50 to 1.00 cycles (3.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	2.00	2.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.88
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

10% of peak load performance is reached (10.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451594

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR W5, [X23, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W1, W11, W19, WZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W6, [X23, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W12, W19, W5, WZR	1	0	0	0	0	1	0	0	0	0	2	1
CMP W12, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W10, W12, W6, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W9, W10, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 4515e4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X7, [X21, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X8, X1, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X2, X9, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X23, #784]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X1, [X3, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 4516c0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
BL 403a40 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR W11, [X23, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X22, X22, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 451594 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238,413,451-452
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1263
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.25 to 0.47 cycles (6.93x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	0.50	0.50	0.00	0.00	2.50	2.17	2.33	0.00	0.00
cycles	2.00	2.00	3.25	3.25	3.25	3.25	0.50	0.50	0.00	0.00	2.50	2.17	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Data deps.	1.00
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

12% of peak load performance is reached (12.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451594

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
LDR W5, [X23, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W1, W11, W19, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W6, [X23, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W12, W19, W5, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W12, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W10, W12, W6, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W9, W10, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4515e4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X21, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X8, X1, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X2, X9, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X23, #784]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X3, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4516c0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X22, X22, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 451594 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D6, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D6, [X7, X8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
B 4515e4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code