OV - exec - Loop 1143

0x451470 ADD	X23, X2, X0,LSL #3

0x451474 ORR	X28, XZR, X22

0x451478 LDR	D6, [X4]

0x45147c DUP	Z4.D, Z6.D[0]

  (1142) 0x451480 LDR	D3, [X28]

  (1142) 0x451484 SUB	X6, X23, X13

  (1142) 0x451488 MOVZ	X21, #0

  (1142) 0x45148c SUB	X5, X6, X13

  (1142) 0x451490 ADD	X12, X23, X13

  (1142) 0x451494 LD1RD	{Z27.D}, P7/Z, [X28, #1]

  (1142) 0x451498 ADD	X10, X23, X17

  (1142) 0x45149c ADD	X9, X23, X16

  (1142) 0x4514a0 FMUL	Z30.D, Z27.D, Z4.D

  (1142) 0x4514a4 ADD	X8, X23, X14

  (1142) 0x4514a8 ADD	X7, X23, X15

  (1142) 0x4514ac ORR	P3.B, P8/Z, P8.B, P8.B

  (1142) 0x4514b0 FMUL	D28, D6, D3

  (1142) 0x4514b4 DUP	Z2.D, Z28.D[0]

  (1142) 0x4514b8 HINT	#0

  (1142) 0x4514bc HINT	#0

    (1141) 0x4514c0 LD1D	{Z5.D}, P3/Z, [X23, X21,LSL #3]

    (1141) 0x4514c4 LD1D	{Z26.D}, P3/Z, [X12, X21,LSL #3]

    (1141) 0x4514c8 LD1D	{Z7.D}, P3/Z, [X5, X21,LSL #3]

    (1141) 0x4514cc LD1D	{Z22.D}, P3/Z, [X6, X21,LSL #3]

    (1141) 0x4514d0 LD1D	{Z16.D}, P3/Z, [X3, X21,LSL #3]

    (1141) 0x4514d4 FMUL	Z23.D, Z1.D, Z5.D

    (1141) 0x4514d8 FMUL	Z25.D, Z12.D, Z7.D

    (1141) 0x4514dc FMAD	Z26.D, P7/M, Z15.D, Z23.D

    (1141) 0x4514e0 FMAD	Z22.D, P7/M, Z19.D, Z25.D

    (1141) 0x4514e4 FADD	Z0.D, Z22.D, Z26.D

    (1141) 0x4514e8 FMAD	Z0.D, P7/M, Z2.D, Z16.D

    (1141) 0x4514ec ST1D	{Z0.D}, P3, [X3, X21,LSL #3]

    (1141) 0x4514f0 LD1D	{Z24.D}, P3/Z, [X9, X21,LSL #3]

    (1141) 0x4514f4 LD1D	{Z17.D}, P3/Z, [X10, X21,LSL #3]

    (1141) 0x4514f8 LD1D	{Z20.D}, P3/Z, [X7, X21,LSL #3]

    (1141) 0x4514fc LD1D	{Z31.D}, P3/Z, [X8, X21,LSL #3]

    (1141) 0x451500 FMUL	Z18.D, Z24.D, Z1.D

    (1141) 0x451504 FMUL	Z21.D, Z20.D, Z12.D

    (1141) 0x451508 FMAD	Z17.D, P7/M, Z15.D, Z18.D

    (1141) 0x45150c FMAD	Z31.D, P7/M, Z19.D, Z21.D

    (1141) 0x451510 FADD	Z29.D, Z31.D, Z17.D

    (1141) 0x451514 FMLA	Z0.D, P7/M, Z29.D, Z30.D

    (1141) 0x451518 ST1D	{Z0.D}, P3, [X3, X21,LSL #3]

    (1141) 0x45151c ADD	X21, X21, X11

    (1141) 0x451520 WHILELO	P3.D, X21, X19

    (1141) 0x451524 B.NE	4514c0

  (1142) 0x451528 ADD	X28, X28, #16

  (1142) 0x45152c ADD	X20, SP, #320

  (1142) 0x451530 ADD	X23, X23, X18

  (1142) 0x451534 CMP	X28, X20

  (1142) 0x451538 B.NE	451480

0x45153c ADD	X4, X4, #8

0x451540 ADD	X0, X0, X27

0x451544 CMP	X4, X22

0x451548 B.NE	451470

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 63 - 71

--------------------------------------------------------------------------------

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:63-66
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.69
Front-end cycles	1.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	40.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	62.50

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:63-66
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.69
Front-end cycles	1.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	40.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	62.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:63-71
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:63-71.

Analyzed code is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:63-66.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.25 to 1.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 40% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.25 to 0.69 cycles (1.82x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	8
loop length	32
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	0.50	0.50	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	0.50	0.50	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Data deps.	1.00
Overall L1	1.25

Vectorization ratios

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X23, X2, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X28, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
DUP Z4.D, Z6.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 451470 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:63-71
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:63-71.

Analyzed code is defined in /home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:63-66.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.25 to 1.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 40% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.25 to 0.69 cycles (1.82x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	8
loop length	32
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	0.50	0.50	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	0.50	0.50	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Data deps.	1.00
Overall L1	1.25

Vectorization ratios

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X23, X2, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X28, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
DUP Z4.D, Z6.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 451470 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code