OV - exec - Loop 1140

    (1138) 0x45125c LDR	X21, [X24]

    (1138) 0x451260 LDR	D28, [SP, #184]

    (1138) 0x451264 LDR	X3, [X25]

    (1138) 0x451268 LDR	D14, [X21, #40]

    (1138) 0x45126c LDP	D12, D13, [X21, #72]

    (1138) 0x451270 LDR	D15, [X21, #120]

    (1138) 0x451274 FSUB	D6, D9, S14

    (1138) 0x451278 FSUB	D1, D28, S13

    (1138) 0x45127c FSUB	D0, D8, S15

    (1138) 0x451280 FMUL	D4, D6, D12

    (1138) 0x451284 FCMPE	D4, #0

    (1138) 0x451288 B.MI	451648

    (1138) 0x45128c LDR	W17, [X21, #56]

    (1138) 0x451290 FCVTZS	W16, D4

    (1138) 0x451294 SUB	W18, W17, #1

    (1138) 0x451298 CMP	W18, W16

    (1138) 0x45129c B.LT	451660

    (1138) 0x4512a0 ORR	X23, XZR, #3840

    (1138) 0x4512a4 FRINTZ	D27, D4

    (1138) 0x4512a8 FSUB	D3, D4, S27

    (1138) 0x4512ac MOVK	X23, #49093

    (1138) 0x4512b0 FMOV	D26, #0.5000000

    (1138) 0x4512b4 FMOV	D2, #-0.5000000

    (1138) 0x4512b8 FMOV	D23, #-1.0000000

    (1138) 0x4512bc SBFM	X20, X16, #0, #31

    (1138) 0x4512c0 FMOV	D5, X23

    (1138) 0x4512c4 FMSUB	D7, D3, D26, D26

    (1138) 0x4512c8 FMUL	D25, D3, D3

    (1138) 0x4512cc FMADD	D22, D3, D26, D23

    (1138) 0x4512d0 FMADD	D24, D3, D7, D26

    (1138) 0x4512d4 FMUL	D16, D3, D5

    (1138) 0x4512d8 FMADD	D27, D22, D25, D11

    (1138) 0x4512dc FMADD	D6, D3, D24, D10

    (1138) 0x4512e0 FADD	D17, D16, D26

    (1138) 0x4512e4 FNMUL	D4, D16, D25

    (1138) 0x4512e8 FMADD	D18, D3, D17, D2

    (1138) 0x4512ec FMADD	D30, D3, D18, D10

    (1138) 0x4512f0 LDR	D19, [X21, #112]

    (1138) 0x4512f4 FMUL	D20, D1, D19

    (1138) 0x4512f8 FCMPE	D20, #0

    (1138) 0x4512fc B.MI	45160c

    (1138) 0x451300 LDR	W0, [X21, #96]

    (1138) 0x451304 FCVTZS	W30, D20

    (1138) 0x451308 SUB	W1, W0, #1

    (1138) 0x45130c CMP	W1, W30

    (1138) 0x451310 B.LT	451680

    (1138) 0x451314 ORR	X2, XZR, #3840

    (1138) 0x451318 FRINTZ	D21, D20

    (1138) 0x45131c FSUB	D31, D20, S21

    (1138) 0x451320 MOVK	X2, #49093

    (1138) 0x451324 FMOV	D29, #0.5000000

    (1138) 0x451328 FMOV	D12, #-0.5000000

    (1138) 0x45132c FMOV	D14, #-1.0000000

    (1138) 0x451330 SBFM	X5, X30, #0, #31

    (1138) 0x451334 FMOV	D13, X2

    (1138) 0x451338 FMSUB	D15, D31, D29, D29

    (1138) 0x45133c FMUL	D1, D31, D31

    (1138) 0x451340 FMADD	D3, D31, D29, D14

    (1138) 0x451344 FMADD	D26, D31, D15, D29

    (1138) 0x451348 FMUL	D28, D31, D13

    (1138) 0x45134c FMADD	D25, D3, D1, D11

    (1138) 0x451350 FMADD	D23, D31, D26, D10

    (1138) 0x451354 FADD	D2, D28, D29

    (1138) 0x451358 FNMUL	D7, D28, D1

    (1138) 0x45135c FMADD	D5, D31, D2, D12

    (1138) 0x451360 FMADD	D22, D31, D5, D10

    (1138) 0x451364 LDR	D16, [X21, #152]

    (1138) 0x451368 FMUL	D0, D0, D16

    (1138) 0x45136c FCMPE	D0, #0

    (1138) 0x451370 B.MI	451630

    (1139) 0x451374 LDR	W7, [X21, #136]

    (1139) 0x451378 FCVTZS	W8, D0

    (1139) 0x45137c SUB	W9, W7, #1

    (1139) 0x451380 CMP	W9, W8

    (1139) 0x451384 B.LT	4516a0

  (1137) 0x451388 ORR	X10, XZR, #3840

  (1137) 0x45138c FRINTZ	D24, D0

  (1137) 0x451390 FSUB	D17, D0, S24

  (1137) 0x451394 MOVK	X10, #49093

  (1137) 0x451398 FMOV	D18, #0.5000000

  (1137) 0x45139c FMOV	D20, #-0.5000000

  (1137) 0x4513a0 FMOV	D31, #-1.0000000

  (1137) 0x4513a4 SBFM	X13, X8, #0, #31

  (1137) 0x4513a8 FMOV	D21, X10

  (1137) 0x4513ac FMSUB	D29, D17, D18, D18

  (1137) 0x4513b0 FMUL	D19, D17, D17

  (1137) 0x4513b4 FMADD	D13, D17, D18, D31

  (1137) 0x4513b8 FMADD	D12, D17, D29, D18

  (1137) 0x4513bc FMUL	D14, D17, D21

  (1137) 0x4513c0 FMADD	D13, D13, D19, D11

  (1137) 0x4513c4 FMADD	D12, D17, D12, D10

  (1137) 0x4513c8 FADD	D15, D14, D18

  (1137) 0x4513cc FNMUL	D14, D14, D19

  (1137) 0x4513d0 FMADD	D1, D17, D15, D20

  (1137) 0x4513d4 FMADD	D15, D17, D1, D10

    (1138) 0x4513d8 LDR	X28, [X21, #32]

    (1138) 0x4513dc STP	D30, D27, [SP, #256]

    (1138) 0x4513e0 STP	D6, D4, [SP, #272]

    (1138) 0x4513e4 STP	D22, D25, [SP, #288]

    (1138) 0x4513e8 STP	D23, D7, [SP, #304]

    (1138) 0x4513ec LDP	X27, X23, [X21, #16]

    (1138) 0x4513f0 CBZ	X26, 451410

    (1138) 0x4513f4 ORR	X0, XZR, X3

    (1138) 0x4513f8 ORR	X2, XZR, X26

    (1138) 0x4513fc MOVZ	W1, #0

    (1138) 0x451400 STP	X5, X13, [SP, #168]

    (1138) 0x451404 BL	403bd0

    (1138) 0x451408 LDP	X5, X13, [SP, #168]

    (1138) 0x45140c ORR	X3, XZR, X0

    (1138) 0x451410 MADD	X14, X28, X13, XZR

    (1138) 0x451414 LDR	X15, [X21, #8]

    (1138) 0x451418 CBZ	X19, 45154c

    (1138) 0x45141c MADD	X21, X5, X23, XZR

    (1138) 0x451420 UBFM	X16, X23, #61, #60

    (1138) 0x451424 UBFM	X18, X23, #60, #59

    (1138) 0x451428 MADD	X0, X20, X27, X14

    (1138) 0x45142c ADD	X4, SP, #256

    (1138) 0x451430 CNTD	X11, ALL

    (1138) 0x451434 SUB	X13, XZR, X28,LSL #3

    (1138) 0x451438 DUP	Z19.D, Z12.D[0]

    (1138) 0x45143c DUP	Z15.D, Z15.D[0]

    (1138) 0x451440 ADD	X17, X21, X23

    (1138) 0x451444 SUB	X20, XZR, X21,LSL #3

    (1138) 0x451448 ADD	X30, X21, X28

    (1138) 0x45144c ADD	X1, X17, X28

    (1138) 0x451450 ADD	X2, X15, X30,LSL #3

    (1138) 0x451454 ADD	X17, X13, X16

    (1138) 0x451458 ADD	X14, X20, X1,LSL #3

    (1138) 0x45145c DUP	Z1.D, Z13.D[0]

    (1138) 0x451460 DUP	Z12.D, Z14.D[0]

    (1138) 0x451464 ADD	X15, X16, X28,LSL #4

    (1138) 0x451468 WHILELO	P8.D, XZR, X19

    (1138) 0x45146c PTRUE	P7.B, ALL

      (1143) 0x451470 ADD	X23, X2, X0,LSL #3

      (1143) 0x451474 ORR	X28, XZR, X22

      (1143) 0x451478 LDR	D6, [X4]

      (1143) 0x45147c DUP	Z4.D, Z6.D[0]

        (1142) 0x451480 LDR	D3, [X28]

        (1142) 0x451484 SUB	X6, X23, X13

        (1142) 0x451488 MOVZ	X21, #0

        (1142) 0x45148c SUB	X5, X6, X13

        (1142) 0x451490 ADD	X12, X23, X13

        (1142) 0x451494 LD1RD	{Z27.D}, P7/Z, [X28, #1]

        (1142) 0x451498 ADD	X10, X23, X17

        (1142) 0x45149c ADD	X9, X23, X16

        (1142) 0x4514a0 FMUL	Z30.D, Z27.D, Z4.D

        (1142) 0x4514a4 ADD	X8, X23, X14

        (1142) 0x4514a8 ADD	X7, X23, X15

        (1142) 0x4514ac ORR	P3.B, P8/Z, P8.B, P8.B

        (1142) 0x4514b0 FMUL	D28, D6, D3

        (1142) 0x4514b4 DUP	Z2.D, Z28.D[0]

        (1142) 0x4514b8 HINT	#0

        (1142) 0x4514bc HINT	#0

          (1141) 0x4514c0 LD1D	{Z5.D}, P3/Z, [X23, X21,LSL #3]

          (1141) 0x4514c4 LD1D	{Z26.D}, P3/Z, [X12, X21,LSL #3]

          (1141) 0x4514c8 LD1D	{Z7.D}, P3/Z, [X5, X21,LSL #3]

          (1141) 0x4514cc LD1D	{Z22.D}, P3/Z, [X6, X21,LSL #3]

          (1141) 0x4514d0 LD1D	{Z16.D}, P3/Z, [X3, X21,LSL #3]

          (1141) 0x4514d4 FMUL	Z23.D, Z1.D, Z5.D

          (1141) 0x4514d8 FMUL	Z25.D, Z12.D, Z7.D

          (1141) 0x4514dc FMAD	Z26.D, P7/M, Z15.D, Z23.D

          (1141) 0x4514e0 FMAD	Z22.D, P7/M, Z19.D, Z25.D

          (1141) 0x4514e4 FADD	Z0.D, Z22.D, Z26.D

          (1141) 0x4514e8 FMAD	Z0.D, P7/M, Z2.D, Z16.D

          (1141) 0x4514ec ST1D	{Z0.D}, P3, [X3, X21,LSL #3]

          (1141) 0x4514f0 LD1D	{Z24.D}, P3/Z, [X9, X21,LSL #3]

          (1141) 0x4514f4 LD1D	{Z17.D}, P3/Z, [X10, X21,LSL #3]

          (1141) 0x4514f8 LD1D	{Z20.D}, P3/Z, [X7, X21,LSL #3]

          (1141) 0x4514fc LD1D	{Z31.D}, P3/Z, [X8, X21,LSL #3]

          (1141) 0x451500 FMUL	Z18.D, Z24.D, Z1.D

          (1141) 0x451504 FMUL	Z21.D, Z20.D, Z12.D

          (1141) 0x451508 FMAD	Z17.D, P7/M, Z15.D, Z18.D

          (1141) 0x45150c FMAD	Z31.D, P7/M, Z19.D, Z21.D

          (1141) 0x451510 FADD	Z29.D, Z31.D, Z17.D

          (1141) 0x451514 FMLA	Z0.D, P7/M, Z29.D, Z30.D

          (1141) 0x451518 ST1D	{Z0.D}, P3, [X3, X21,LSL #3]

          (1141) 0x45151c ADD	X21, X21, X11

          (1141) 0x451520 WHILELO	P3.D, X21, X19

          (1141) 0x451524 B.NE	4514c0

        (1142) 0x451528 ADD	X28, X28, #16

        (1142) 0x45152c ADD	X20, SP, #320

        (1142) 0x451530 ADD	X23, X23, X18

        (1142) 0x451534 CMP	X28, X20

        (1142) 0x451538 B.NE	451480

      (1143) 0x45153c ADD	X4, X4, #8

      (1143) 0x451540 ADD	X0, X0, X27

      (1143) 0x451544 CMP	X4, X22

      (1143) 0x451548 B.NE	451470

    (1138) 0x45154c LDR	X30, [SP, #192]

    (1138) 0x451550 ADD	X24, X24, #8

    (1138) 0x451554 ADD	X25, X25, #24

    (1138) 0x451558 CMP	X30, X24

    (1138) 0x45155c B.NE	45125c

0x451560 LDP	D10, D11, [SP, #112]

0x451564 LDP	X25, X26, [SP, #64]

0x451568 LDP	X28, X23, [SP, #200]

0x45156c LDP	D12, D13, [SP, #128]

0x451570 LDP	D14, D15, [SP, #144]

0x451574 LDR	X21, [SP, #216]

0x451578 ORR	X0, XZR, X28

0x45157c MOVZ	X22, #0

0x451580 BL	4c4660

0x451584 LDR	W11, [X23, #48]

0x451588 MOVZ	W19, #0

0x45158c CMP	W11, #0

0x451590 B.LE	4515f0

  (1144) 0x451594 LDR	W5, [X23, #64]

  (1144) 0x451598 MADD	W1, W11, W19, WZR

  (1144) 0x45159c ADD	W19, W19, #1

  (1144) 0x4515a0 LDR	W6, [X23, #8]

  (1144) 0x4515a4 MADD	W12, W19, W5, WZR

  (1144) 0x4515a8 CMP	W12, W6

  (1144) 0x4515ac CSEL	W10, W12, W6, #13

  (1144) 0x4515b0 SUB	W9, W10, W1

  (1144) 0x4515b4 CMP	W9, #0

  (1144) 0x4515b8 B.LE	4515e4

  (1144) 0x4515bc LDR	X7, [X21, #24]

  (1144) 0x4515c0 UBFM	X8, X1, #61, #31

  (1144) 0x4515c4 UBFM	X2, X9, #61, #31

  (1144) 0x4515c8 LDR	X3, [X23, #784]

  (1144) 0x4515cc ADD	X0, X7, X8

  (1144) 0x4515d0 LDR	X1, [X3, X22]

  (1144) 0x4515d4 CMP	X2, #8

  (1144) 0x4515d8 B.EQ	4516c0

  (1144) 0x4515dc BL	403a40

  (1144) 0x4515e0 LDR	W11, [X23, #48]

  (1144) 0x4515e4 ADD	X22, X22, #24

  (1144) 0x4515e8 CMP	W19, W11

  (1144) 0x4515ec B.LT	451594

0x4515f0 LDP	D8, D9, [SP, #96]

0x4515f4 LDP	X19, X20, [SP, #16]

0x4515f8 LDP	X21, X22, [SP, #32]

0x4515fc LDP	X23, X24, [SP, #48]

0x451600 LDP	X27, X28, [SP, #80]

0x451604 LDP	X29, X30, [SP], #320

0x451608 RET

  (1137) 0x45160c LDR	D16, [X21, #152]

  (1137) 0x451610 FMOV	D23, D10

  (1137) 0x451614 MOVI	D7, #0

  (1137) 0x451618 FMOV	D25, D11

  (1137) 0x45161c FMOV	D22, D10

  (1137) 0x451620 MOVZ	X5, #0

  (1137) 0x451624 FMUL	D0, D0, D16

  (1137) 0x451628 FCMPE	D0, #0

  (1137) 0x45162c B.GE	451374

    (1138) 0x451630 FMOV	D12, D10

    (1138) 0x451634 MOVI	D14, #0

    (1138) 0x451638 MOVZ	X13, #0

    (1138) 0x45163c FMOV	D13, D11

    (1138) 0x451640 FMOV	D15, D10

    (1138) 0x451644 B	4513d8

    (1138) 0x451648 FMOV	D6, D10

    (1138) 0x45164c MOVI	D4, #0

    (1138) 0x451650 MOVZ	X20, #0

    (1138) 0x451654 FMOV	D27, D11

    (1138) 0x451658 FMOV	D30, D10

    (1138) 0x45165c B	4512f0

    (1138) 0x451660 ADRP	X27,

    (1138) 0x451664 ADRP	X28,

    (1138) 0x451668 MOVI	D30, #0

    (1138) 0x45166c FMOV	D6, D11

    (1138) 0x451670 SBFM	X20, X18, #0, #31

    (1138) 0x451674 LDR	D4, [X27, #4040]

    (1138) 0x451678 LDR	D27, [X28, #4048]

    (1138) 0x45167c B	4512f0

    (1138) 0x451680 ADRP	X4,

    (1138) 0x451684 ADRP	X6,

    (1138) 0x451688 MOVI	D22, #0

    (1138) 0x45168c FMOV	D23, D11

    (1138) 0x451690 SBFM	X5, X1, #0, #31

    (1138) 0x451694 LDR	D7, [X4, #4040]

    (1138) 0x451698 LDR	D25, [X6, #4048]

    (1138) 0x45169c B	451364

  (1137) 0x4516a0 ADRP	X11,

  (1137) 0x4516a4 ADRP	X12,

  (1137) 0x4516a8 MOVI	D15, #0

  (1137) 0x4516ac FMOV	D12, D11

  (1137) 0x4516b0 SBFM	X13, X9, #0, #31

  (1137) 0x4516b4 LDR	D14, [X11, #4040]

  (1137) 0x4516b8 LDR	D13, [X12, #4048]

  (1137) 0x4516bc B	4513d8

  (1144) 0x4516c0 LDR	D6, [X1]

  (1144) 0x4516c4 STR	D6, [X7, X8]

  (1144) 0x4516c8 B	4515e4

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 249 - 249

--------------------------------------------------------------------------------

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 53 - 63

--------------------------------------------------------------------------------

53:   if (x < 0)

[...]

60:     ind = static_cast<int>(x);

61:     dx = x - ind;

62:     // upper bound

63:     if (ind > nmax)

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 42 - 71

--------------------------------------------------------------------------------

42:   x -= spline_m->x_grid.start;

43:   y -= spline_m->y_grid.start;

44:   z -= spline_m->z_grid.start;

45:   T tx, ty, tz;

46:   int ix, iy, iz;

47:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

48:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

49:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

57:   const intptr_t ys = spline_m->y_stride;

58:   const intptr_t zs = spline_m->z_stride;

59:

60:   constexpr T zero(0);

61:   std::fill(vals, vals + num_splines, zero);

62:

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 175 - 189

--------------------------------------------------------------------------------

175:     for (int i = 0; i < nBlocks; ++i)

176:       MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock);

[...]

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

188:     }

189:   }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57

--------------------------------------------------------------------------------

54:     a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03;

55:     a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13;

56:     a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23;

57:     a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33;

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 238 - 952

--------------------------------------------------------------------------------

238:       if (__b < __a)

[...]

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

[...]

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1263 - 1263

--------------------------------------------------------------------------------

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.73
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	NewTimer.h:249-249,einspline_spo_ref.hpp:175-175,einspline_spo_ref.hpp:183-183,einspline_spo_ref.hpp:189-189
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	4.33
CQA cycles if fully vectorized	1.04
Front-end cycles	2.50
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.33
P10 cycles	4.33
P11 cycles	4.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	43.38
Bytes prefetched	0.00
Bytes loaded	188.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	57.14
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	37.50
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	2.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.73
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	NewTimer.h:249-249,einspline_spo_ref.hpp:175-175,einspline_spo_ref.hpp:183-183,einspline_spo_ref.hpp:189-189
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	4.33
CQA cycles if fully vectorized	1.04
Front-end cycles	2.50
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.33
P10 cycles	4.33
P11 cycles	4.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	43.38
Bytes prefetched	0.00
Bytes loaded	188.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	57.14
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	37.50
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:175-189
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,57-71
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:175-176,183-189
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238,413,451-452,951-952
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1263
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.33 to 1.67 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 37% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.33 to 1.04 cycles (4.16x speedup).

Details

57% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.33 to 0.50 cycles (8.67x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 188 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	0.00	0.00
cycles	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Overall L1	4.33

Vectorization ratios

all	57%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

45% of peak load performance is reached (43.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451578

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X28, X23, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X21, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR W11, [X23, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVZ W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 4515f0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:175-189
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,57-71
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:175-176,183-189
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:238,413,451-452,951-952
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1263
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.33 to 1.67 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 37% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.33 to 1.04 cycles (4.16x speedup).

Details

57% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.33 to 0.50 cycles (8.67x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 188 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	0.00	0.00
cycles	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Overall L1	4.33

Vectorization ratios

all	57%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

45% of peak load performance is reached (43.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451578

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X28, X23, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X21, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR W11, [X23, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVZ W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 4515f0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code