OV - exec - Function qmcplusplus::SoaDistanceTableAAOMPTarget<double, 3u, 40>::update(int)

	Function: qmcplusplus::SoaDistanceTableAAOMPTarget<double, 3u, 40>::update(int)	Module: exec	Source: SoaDistanceTableAAOMPTarget.h:429-445 [...]	Coverage: 8.83%

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h: 429 - 445

--------------------------------------------------------------------------------

429:   inline void update(IndexType iat) override

430:   {

431:     ScopedTimer local_timer(update_timer_);

[...]

437:     for (int idim = 0; idim < D; ++idim)

438:       std::copy_n(temp_dr_.data(idim), nupdate, displacements_[iat].data(idim));

439:     //copy column

440:     for (size_t i = iat + 1; i < num_targets_; ++i)

441:     {

442:       distances_[i][iat]     = temp_r_[i];

443:       displacements_[i](iat) = -temp_dr_[i];

444:     }

445:   }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

243:       for (size_t i = 0; i < D; ++i)

244:         *(_base + M * i) = rhs[i];

[...]

263:   inline Accessor operator()(size_t i) { return Accessor(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 248

--------------------------------------------------------------------------------

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 413 - 452

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 182 - 182

--------------------------------------------------------------------------------

182:       inverse[d] = -X[d];

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1131 - 1131

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

0x4eed80 STP	X29, X30, [SP, #944]!

0x4eed84 ADD	X29, SP, #0

0x4eed88 STP	X19, X20, [SP, #16]

0x4eed8c ORR	W19, WZR, W1

0x4eed90 SBFM	X20, X1, #61, #31

0x4eed94 STP	X21, X22, [SP, #32]

0x4eed98 ORR	X22, XZR, X0

0x4eed9c STP	X23, X24, [SP, #48]

0x4eeda0 MOVZ	W24, #40

0x4eeda4 SMADDL	X24, W1, W24, XZR

0x4eeda8 LDR	X21, [X0, #648]

0x4eedac ORR	X0, XZR, X21

0x4eedb0 BL	4c43c0

0x4eedb4 CMP	W19, #0

0x4eedb8 B.LE	4eee2c

0x4eedbc LDR	X0, [X22, #72]

0x4eedc0 LDR	X1, [X22, #144]

0x4eedc4 ADD	X2, X0, X24

0x4eedc8 LDR	X0, [X2, #24]

0x4eedcc CMP	X20, #8

0x4eedd0 B.EQ	4eef7c

0x4eedd4 ORR	X2, XZR, X20

0x4eedd8 MOVZ	X23, #0

0x4eeddc STP	X25, X26, [SP, #64]

0x4eede0 ADD	X25, X22, #160

0x4eede4 ADD	X26, X22, #96

0x4eede8 BL	403a40

(3290) 0x4eedec LDR	X15, [X26]

(3290) 0x4eedf0 ORR	X2, XZR, X20

(3290) 0x4eedf4 LDR	X12, [X25, #8]

(3290) 0x4eedf8 LDR	X13, [X25, #24]

(3290) 0x4eedfc ADD	X16, X15, X24

(3290) 0x4eee00 LDR	X17, [X16, #8]

(3290) 0x4eee04 MADD	X14, X23, X12, XZR

(3290) 0x4eee08 LDR	X18, [X16, #24]

(3290) 0x4eee0c ADD	X1, X13, X14,LSL #3

(3290) 0x4eee10 MADD	X30, X23, X17, XZR

(3290) 0x4eee14 ADD	X23, X23, #1

(3290) 0x4eee18 ADD	X0, X18, X30,LSL #3

(3290) 0x4eee1c BL	403a40

(3290) 0x4eee20 CMP	X23, #3

(3290) 0x4eee24 B.NE	4eedec

0x4eee28 LDP	X25, X26, [SP, #64]

(3288) 0x4eee2c ADD	W19, W19, #1

(3288) 0x4eee30 SBFM	X1, X19, #0, #31

(3288) 0x4eee34 LDR	X16, [X22, #24]

(3288) 0x4eee38 CMP	X1, X16

(3288) 0x4eee3c B.CS	4eef60

(3288) 0x4eee40 LDR	X15, [X22, #72]

(3288) 0x4eee44 SUB	X0, X16, X1

(3288) 0x4eee48 ADD	X11, X24, #64

(3288) 0x4eee4c LDR	X13, [X22, #96]

(3288) 0x4eee50 LDR	X9, [X22, #144]

(3288) 0x4eee54 LDRSW	X2, [X22, #168]

(3288) 0x4eee58 SUB	X12, X13, #16

(3288) 0x4eee5c LDR	X22, [X22, #184]

(3288) 0x4eee60 ADD	X8, X22, X2,LSL #3

(3288) 0x4eee64 ADD	X6, X22, X2,LSL #4

(3288) 0x4eee68 TBZ	W0, #0, 4eeec0

(3288) 0x4eee6c LDR	D3, [X9, X1,LSL #3]

(3288) 0x4eee70 LDR	X5, [X15, X11]

(3288) 0x4eee74 LDR	X3, [X12, X11]

(3288) 0x4eee78 LDR	X4, [X13, X11]

(3288) 0x4eee7c ADD	X11, X24, #104

(3288) 0x4eee80 STR	D3, [X5, X20]

(3288) 0x4eee84 LDR	D29, [X22, X1,LSL #3]

(3288) 0x4eee88 UBFM	X24, X3, #61, #60

(3288) 0x4eee8c LDR	D4, [X8, X1,LSL #3]

(3288) 0x4eee90 ADD	X7, X24, X20

(3288) 0x4eee94 ADD	X10, X4, X24

(3288) 0x4eee98 LDR	D30, [X6, X1,LSL #3]

(3288) 0x4eee9c ADD	X1, X1, #1

(3288) 0x4eeea0 FNEG	D5, D29

(3288) 0x4eeea4 FNEG	D6, D4

(3288) 0x4eeea8 FNEG	D7, D30

(3288) 0x4eeeac STR	D5, [X4, X20]

(3288) 0x4eeeb0 STR	D6, [X4, X7]

(3288) 0x4eeeb4 STR	D7, [X10, X7]

(3288) 0x4eeeb8 CMP	X1, X16

(3288) 0x4eeebc B.EQ	4eef60

  (3289) 0x4eeec0 LDR	D16, [X9, X1,LSL #3]

  (3289) 0x4eeec4 ADD	X17, X11, #40

  (3289) 0x4eeec8 ADD	X14, X1, #1

  (3289) 0x4eeecc LDR	X18, [X15, X11]

  (3289) 0x4eeed0 LDR	X30, [X12, X11]

  (3289) 0x4eeed4 LDR	X23, [X13, X11]

  (3289) 0x4eeed8 ADD	X11, X11, #80

  (3289) 0x4eeedc STR	D16, [X18, X20]

  (3289) 0x4eeee0 LDR	D23, [X22, X1,LSL #3]

  (3289) 0x4eeee4 UBFM	X19, X30, #61, #60

  (3289) 0x4eeee8 LDR	D25, [X8, X1,LSL #3]

  (3289) 0x4eeeec ADD	X5, X19, X20

  (3289) 0x4eeef0 ADD	X2, X23, X19

  (3289) 0x4eeef4 LDR	D24, [X6, X1,LSL #3]

  (3289) 0x4eeef8 ADD	X1, X1, #2

  (3289) 0x4eeefc FNEG	D17, D23

  (3289) 0x4eef00 LDR	X0, [X12, X17]

  (3289) 0x4eef04 FNEG	D18, D25

  (3289) 0x4eef08 LDR	X3, [X15, X17]

  (3289) 0x4eef0c FNEG	D19, D24

  (3289) 0x4eef10 STR	D17, [X23, X20]

  (3289) 0x4eef14 LDR	X4, [X13, X17]

  (3289) 0x4eef18 UBFM	X24, X0, #61, #60

  (3289) 0x4eef1c STR	D18, [X23, X5]

  (3289) 0x4eef20 ADD	X7, X24, X20

  (3289) 0x4eef24 STR	D19, [X2, X5]

  (3289) 0x4eef28 LDR	D20, [X9, X14,LSL #3]

  (3289) 0x4eef2c ADD	X10, X4, X24

  (3289) 0x4eef30 STR	D20, [X3, X20]

  (3289) 0x4eef34 LDR	D26, [X22, X14,LSL #3]

  (3289) 0x4eef38 LDR	D28, [X8, X14,LSL #3]

  (3289) 0x4eef3c LDR	D27, [X6, X14,LSL #3]

  (3289) 0x4eef40 FNEG	D21, D26

  (3289) 0x4eef44 FNEG	D22, D28

  (3289) 0x4eef48 FNEG	D31, D27

  (3289) 0x4eef4c STR	D21, [X4, X20]

  (3289) 0x4eef50 STR	D22, [X4, X7]

  (3289) 0x4eef54 STR	D31, [X10, X7]

  (3289) 0x4eef58 CMP	X1, X16

  (3289) 0x4eef5c B.NE	4eeec0

(3288) 0x4eef60 ORR	X0, XZR, X21

(3288) 0x4eef64 BL	4c4660

(3288) 0x4eef68 LDP	X19, X20, [SP, #16]

(3288) 0x4eef6c LDP	X21, X22, [SP, #32]

(3288) 0x4eef70 LDP	X23, X24, [SP, #48]

(3288) 0x4eef74 LDP	X29, X30, [SP], #80

(3288) 0x4eef78 RET

(3288) 0x4eef7c LDR	D31, [X1]

(3288) 0x4eef80 LDR	X5, [X22, #96]

(3288) 0x4eef84 LDR	X3, [X22, #184]

(3288) 0x4eef88 LDR	X1, [X22, #168]

(3288) 0x4eef8c ADD	X7, X5, X24

(3288) 0x4eef90 STR	D31, [X0]

(3288) 0x4eef94 LDR	X8, [X7, #24]

(3288) 0x4eef98 LDR	D0, [X3]

(3288) 0x4eef9c UBFM	X6, X1, #61, #60

(3288) 0x4eefa0 LDR	X9, [X7, #8]

(3288) 0x4eefa4 ADD	X4, X3, X6

(3288) 0x4eefa8 STR	D0, [X8]

(3288) 0x4eefac LDR	D1, [X3, X6]

(3288) 0x4eefb0 UBFM	X10, X9, #61, #60

(3288) 0x4eefb4 ADD	X11, X8, X10

(3288) 0x4eefb8 STR	D1, [X8, X10]

(3288) 0x4eefbc LDR	D2, [X4, X6]

(3288) 0x4eefc0 STR	D2, [X11, X10]

(3288) 0x4eefc4 B	4eee2c

0x4eefc8 HINT	#0

0x4eefcc HINT	#0

0x4eefd0 HINT	#0

0x4eefd4 HINT	#0

0x4eefd8 HINT	#0

0x4eefdc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	SoaDistanceTableAAOMPTarget.h:429-445
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:429-431,437-445
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,243-244,263,271
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:413,451-452
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:182
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1131
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.25 to 0.62 cycles (6.80x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.25 to 1.00 cycles (4.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50
cycles	2.00	2.00	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	4.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.25 cycles. At this rate:

11% of peak load performance is reached (11.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (18.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4eed80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W19, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X20, X1, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W24, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMADDL X24, W1, W24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X21, [X0, #648]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4eee2c <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X22, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X22, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4eef7c <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X25, X22, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X22, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a40 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	SoaDistanceTableAAOMPTarget.h:429-445
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:429-431,437-445
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,243-244,263,271
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:413,451-452
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:182
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1131
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.25 to 1.00 cycles (4.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50
cycles	2.00	2.00	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	4.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.25 cycles. At this rate:

11% of peak load performance is reached (11.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (18.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4eed80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W19, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X20, X1, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W24, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMADDL X24, W1, W24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X21, [X0, #648]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4eee2c <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X22, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X22, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4eef7c <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X25, X22, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X22, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a40 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::SoaDistanceTableAAOMPTarget::update(int)–	8.83	14.6
▼Loop 3288 - SoaDistanceTableAAOMPTarget.h:437-445 - exec–	0	0.01
○Loop 3289 - SoaDistanceTableAAOMPTarget.h:440-442 - exec	8.83	12.35
○Loop 3290 - SoaDistanceTableAAOMPTarget.h:437-437 - exec	0	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code