OV - exec - Function qmcplusplus::WaveFunction::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector<double, 3u>&)

	Function: qmcplusplus::WaveFunction::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVect ...	Module: exec	Source: WaveFunction.cpp:194-204 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 194 - 204

--------------------------------------------------------------------------------

194: {

195:   grad       = valT(0);

196:   valT ratio = (iat < nelup ? Det_up->ratioGrad(P, iat, grad) : Det_dn->ratioGrad(P, iat, grad));

197:

198:   for (size_t i = 0; i < Jastrows.size(); i++)

199:   {

200:     ScopedTimer local_timer(jastrow_timers[i]);

201:     ratio *= Jastrows[i]->ratioGrad(P, iat, grad);

202:   }

203:   return ratio;

204: }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 164 - 164

--------------------------------------------------------------------------------

164:       X[d] = rhs;

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 993

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

0x40f648 STP	X29, X30, [SP, #928]!

0x40f64c ADD	X29, SP, #0

0x40f650 STP	X19, X20, [SP, #16]

0x40f654 STP	X21, X22, [SP, #32]

0x40f658 ORR	X22, XZR, X0

0x40f65c STP	X23, X24, [SP, #48]

0x40f660 ORR	X23, XZR, X3

0x40f664 ORR	W24, WZR, W2

0x40f668 STP	X25, X26, [SP, #64]

0x40f66c ORR	X25, XZR, X1

0x40f670 LDR	W0, [X0, #52]

0x40f674 STR	D15, [SP, #80]

0x40f678 STP	XZR, XZR, [X3]

0x40f67c STR	XZR, [X3, #16]

0x40f680 CMP	W0, W2

0x40f684 B.LE	40f734

0x40f688 LDR	X0, [X22]

0x40f68c LDR	X6, [X0]

0x40f690 LDR	X7, [X6, #32]

0x40f694 BLR	X7

0x40f698 FMOV	D15, D0

(187) 0x40f69c LDR	X2, [X22, #16]

(187) 0x40f6a0 ADD	X20, X22, #16

(187) 0x40f6a4 MOVZ	X19, #0

(187) 0x40f6a8 ADD	X22, X22, #88

(187) 0x40f6ac LDR	X1, [X20, #8]

(187) 0x40f6b0 CMP	X1, X2

(187) 0x40f6b4 B.EQ	40f714

(187) 0x40f6b8 HINT	#0

(187) 0x40f6bc HINT	#0

  (188) 0x40f6c0 LDR	X3, [X22]

  (188) 0x40f6c4 UBFM	X26, X19, #61, #60

  (188) 0x40f6c8 LDR	X21, [X3, X26]

  (188) 0x40f6cc ORR	X0, XZR, X21

  (188) 0x40f6d0 BL	4c43c0

  (188) 0x40f6d4 LDR	X8, [X20]

  (188) 0x40f6d8 ORR	X3, XZR, X23

  (188) 0x40f6dc ORR	W2, WZR, W24

  (188) 0x40f6e0 ORR	X1, XZR, X25

  (188) 0x40f6e4 LDR	X0, [X8, X26]

  (188) 0x40f6e8 LDR	X9, [X0]

  (188) 0x40f6ec LDR	X10, [X9, #32]

  (188) 0x40f6f0 BLR	X10

  (188) 0x40f6f4 FMUL	D15, D15, D0

  (188) 0x40f6f8 ORR	X0, XZR, X21

  (188) 0x40f6fc ADD	X19, X19, #1

  (188) 0x40f700 BL	4c4660

  (188) 0x40f704 LDP	X11, X12, [X20]

  (188) 0x40f708 SUB	X13, X12, X11

  (188) 0x40f70c CMP	X19, X13,ASR #3

  (188) 0x40f710 B.CC	40f6c0

(187) 0x40f714 FMOV	D0, D15

(187) 0x40f718 LDR	D15, [SP, #80]

(187) 0x40f71c LDP	X19, X20, [SP, #16]

(187) 0x40f720 LDP	X21, X22, [SP, #32]

(187) 0x40f724 LDP	X23, X24, [SP, #48]

(187) 0x40f728 LDP	X25, X26, [SP, #64]

(187) 0x40f72c LDP	X29, X30, [SP], #96

(187) 0x40f730 RET

(187) 0x40f734 LDR	X0, [X22, #8]

(187) 0x40f738 LDR	X4, [X0]

(187) 0x40f73c LDR	X5, [X4, #32]

(187) 0x40f740 BLR	X5

(187) 0x40f744 FMOV	D15, D0

(187) 0x40f748 B	40f69c

0x40f74c ORR	X23, XZR, X0

0x40f750 ORR	X0, XZR, X21

0x40f754 BL	4c4660

0x40f758 ORR	X0, XZR, X23

0x40f75c BL	403e10

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	WaveFunction.cpp:194-204
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:194-204
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:164
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 0.83 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.00 to 0.56 cycles (7.11x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.50 cycles (2.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	0.50	0.50	0.50	0.50	4.00	4.00	4.00	3.50	3.50
cycles	2.00	2.00	3.25	3.25	3.25	3.25	0.50	0.50	0.50	0.50	4.00	4.00	4.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

7% of peak load performance is reached (7.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
58% of peak store performance is reached (28.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40f648

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D15, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP XZR, XZR, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 40f734 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X6, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	WaveFunction.cpp:194-204
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/refwrap.h:347
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:194-204
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:164
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 0.83 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.50 cycles (2.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	0.50	0.50	0.50	0.50	4.00	4.00	4.00	3.50	3.50
cycles	2.00	2.00	3.25	3.25	3.25	3.25	0.50	0.50	0.50	0.50	4.00	4.00	4.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

7% of peak load performance is reached (7.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
58% of peak store performance is reached (28.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40f648

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D15, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP XZR, XZR, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 40f734 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X6, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼qmcplusplus::WaveFunction::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)–	0.01	0.02
▼Loop 187 - WaveFunction.cpp:196-204 - exec–	0	0.01
○Loop 188 - WaveFunction.cpp:198-201 - exec	0.01	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code