OV - exec - Function qmcplusplus::TimerType<std::chrono::_V2::system

	Function: qmcplusplus::TimerType<std::chrono::_V2::system_clock>::stop()	Module: exec	Source: NewTimer.cpp:84-120 [...]	Coverage: 0.03%

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_tree.h: 269 - 2459

--------------------------------------------------------------------------------

269:       _Rb_tree_iterator(_Base_ptr __x) _GLIBCXX_NOEXCEPT

[...]

283: 	_M_node = _Rb_tree_increment(_M_node);

[...]

298: 	_M_node = _Rb_tree_decrement(_M_node);

299: 	return *this;

[...]

631:       }

[...]

733:       { return static_cast<_Link_type>(this->_M_impl._M_header._M_parent); }

[...]

748:       { return &this->_M_impl._M_header; }

[...]

778:       { return static_cast<_Link_type>(__x->_M_left); }

[...]

786:       { return static_cast<_Link_type>(__x->_M_right); }

[...]

1636: 	~_Auto_node()

[...]

1947:       while (__x != 0)

1948: 	if (!_M_impl._M_key_compare(_S_key(__x), __k))

1949: 	  __y = __x, __x = _S_left(__x);

[...]

2109:       _Base_ptr __y = _M_end();

2110:       bool __comp = true;

2111:       while (__x != 0)

2112: 	{

2113: 	  __y = __x;

2114: 	  __comp = _M_impl._M_key_compare(__k, _S_key(__x));

2115: 	  __x = __comp ? _S_left(__x) : _S_right(__x);

2116: 	}

2117:       iterator __j = iterator(__y);

2118:       if (__comp)

2119: 	{

2120: 	  if (__j == begin())

2121: 	    return _Res(__x, __y);

2122: 	  else

2123: 	    --__j;

2124: 	}

2125:       if (_M_impl._M_key_compare(_S_key(__j._M_node), __k))

[...]

2217: 	      && _M_impl._M_key_compare(_S_key(_M_rightmost()), __k))

2218: 	    return _Res(0, _M_rightmost());

2219: 	  else

2220: 	    return _M_get_insert_unique_pos(__k);

2221: 	}

2222:       else if (_M_impl._M_key_compare(__k, _S_key(__pos._M_node)))

2223: 	{

2224: 	  // First, try before...

2225: 	  iterator __before = __pos;

2226: 	  if (__pos._M_node == _M_leftmost()) // begin()

2227: 	    return _Res(_M_leftmost(), _M_leftmost());

2228: 	  else if (_M_impl._M_key_compare(_S_key((--__before)._M_node), __k))

2229: 	    {

2230: 	      if (_S_right(__before._M_node) == 0)

[...]

2242: 	  if (__pos._M_node == _M_rightmost())

2243: 	    return _Res(0, _M_rightmost());

2244: 	  else if (_M_impl._M_key_compare(__k, _S_key((++__after)._M_node)))

2245: 	    {

2246: 	      if (_S_right(__pos._M_node) == 0)

[...]

2373:     _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::

2374:     _M_insert_node(_Base_ptr __x, _Base_ptr __p, _Link_type __z)

2375:     -> iterator

2376:     {

2377:       bool __insert_left = (__x != 0 || __p == _M_end()

2378: 			    || _M_impl._M_key_compare(_S_key(__z),

2379: 						      _S_key(__p)));

2380:

2381:       _Rb_tree_insert_and_rebalance(__insert_left, __z, __p,

2382: 				    this->_M_impl._M_header);

2383:       ++_M_impl._M_node_count;

[...]

2459: 	auto __res = _M_get_insert_hint_unique_pos(__pos, __z._M_key());

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 124

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

120:       {

121:         return this->long_buckets[j] < rhs.long_buckets[j];

122:       }

123:     }

124:     return this->long_buckets[N - 1] < rhs.long_buckets[N - 1];

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_map.h: 511 - 511

--------------------------------------------------------------------------------

511: 	if (__i == end() || key_comp()(__k, (*__i).first))

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/chrono.h: 214 - 716

--------------------------------------------------------------------------------

214: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

716: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 84 - 120

--------------------------------------------------------------------------------

84: void TimerType<CLOCK>::stop()

85: {

86:   if (active)

[...]

98:     bool is_true_master(true);

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       std::chrono::duration<double> elapsed = CLOCK::now() - start_time;

105:       total_time += elapsed.count();

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed.count();

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/tuple: 2887 - 2888

--------------------------------------------------------------------------------

2887:       : first(std::forward<_Args1>(std::get<_Indexes1>(__tuple1))...),

2888: 	second(std::forward<_Args2>(std::get<_Indexes2>(__tuple2))...)

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h: 151 - 172

--------------------------------------------------------------------------------

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

0x4c4660 STP	X29, X30, [SP, #928]!

0x4c4664 ADD	X29, SP, #0

0x4c4668 STP	X21, X22, [SP, #32]

0x4c466c LDRB	W21, [X0, #56]

0x4c4670 TBNZ	W21, #0, 4c4680

(2613) 0x4c4674 LDP	X21, X22, [SP, #32]

(2613) 0x4c4678 LDP	X29, X30, [SP], #96

(2613) 0x4c467c RET

(2613) 0x4c4680 STP	X19, X20, [SP, #16]

(2613) 0x4c4684 ORR	W20, WZR, W21

(2613) 0x4c4688 STP	X23, X24, [SP, #48]

(2613) 0x4c468c ORR	X23, XZR, X0

(2613) 0x4c4690 BL	404080

(2613) 0x4c4694 ORR	W19, WZR, W0

(2613) 0x4c4698 CMP	W0, #0

(2613) 0x4c469c B.LE	4c484c

(2613) 0x4c46a0 ANDS	W1, W0, #128

(2613) 0x4c46a4 SUB	W22, W0, #1

(2613) 0x4c46a8 B.EQ	4c4770

(2613) 0x4c46ac CMP	W1, #1

(2613) 0x4c46b0 B.EQ	4c4754

(2613) 0x4c46b4 CMP	W1, #2

(2613) 0x4c46b8 B.EQ	4c473c

(2613) 0x4c46bc CMP	W1, #3

(2613) 0x4c46c0 B.EQ	4c4724

(2613) 0x4c46c4 CMP	W1, #4

(2613) 0x4c46c8 B.EQ	4c470c

(2613) 0x4c46cc CMP	W1, #5

(2613) 0x4c46d0 B.EQ	4c46f4

(2613) 0x4c46d4 CMP	W1, #6

(2613) 0x4c46d8 B.NE	4c49ec

(2613) 0x4c46dc ORR	W0, WZR, W19

(2613) 0x4c46e0 SUB	W19, W19, #1

(2613) 0x4c46e4 BL	403de0

(2613) 0x4c46e8 CMP	W0, #0

(2613) 0x4c46ec CCMP	W20, #0, #4, #0

(2613) 0x4c46f0 CSINC	W20, WZR, WZR, #0

(2613) 0x4c46f4 ORR	W0, WZR, W19

(2613) 0x4c46f8 SUB	W19, W19, #1

(2613) 0x4c46fc BL	403de0

(2613) 0x4c4700 CMP	W0, #0

(2613) 0x4c4704 CCMP	W20, #0, #4, #0

(2613) 0x4c4708 CSINC	W20, WZR, WZR, #0

(2613) 0x4c470c ORR	W0, WZR, W19

(2613) 0x4c4710 SUB	W19, W19, #1

(2613) 0x4c4714 BL	403de0

(2613) 0x4c4718 CMP	W0, #0

(2613) 0x4c471c CCMP	W20, #0, #4, #0

(2613) 0x4c4720 CSINC	W20, WZR, WZR, #0

(2613) 0x4c4724 ORR	W0, WZR, W19

(2613) 0x4c4728 SUB	W19, W19, #1

(2613) 0x4c472c BL	403de0

(2613) 0x4c4730 CMP	W0, #0

(2613) 0x4c4734 CCMP	W20, #0, #4, #0

(2613) 0x4c4738 CSINC	W20, WZR, WZR, #0

(2613) 0x4c473c ORR	W0, WZR, W19

(2613) 0x4c4740 SUB	W19, W19, #1

(2613) 0x4c4744 BL	403de0

(2613) 0x4c4748 CMP	W0, #0

(2613) 0x4c474c CCMP	W20, #0, #4, #0

(2613) 0x4c4750 CSINC	W20, WZR, WZR, #0

(2613) 0x4c4754 ORR	W0, WZR, W19

(2613) 0x4c4758 BL	403de0

(2613) 0x4c475c CMP	W0, #0

(2613) 0x4c4760 CCMP	W20, #0, #4, #0

(2613) 0x4c4764 CSINC	W20, WZR, WZR, #0

(2613) 0x4c4768 SUBS	W19, W19, #1

(2613) 0x4c476c B.EQ	4c4834

  (2622) 0x4c4770 ORR	W0, WZR, W19

  (2622) 0x4c4774 SUB	W24, W19, #1

  (2622) 0x4c4778 BL	403de0

  (2622) 0x4c477c CMP	W0, #0

  (2622) 0x4c4780 ORR	W0, WZR, W24

  (2622) 0x4c4784 CCMP	W20, #0, #4, #0

  (2622) 0x4c4788 CSINC	W22, WZR, WZR, #0

  (2622) 0x4c478c BL	403de0

  (2622) 0x4c4790 ORR	W2, WZR, W0

  (2622) 0x4c4794 SUB	W0, W24, #1

  (2622) 0x4c4798 CMP	W2, #0

  (2622) 0x4c479c CCMP	W22, #0, #4, #0

  (2622) 0x4c47a0 CSINC	W20, WZR, WZR, #0

  (2622) 0x4c47a4 BL	403de0

  (2622) 0x4c47a8 ORR	W3, WZR, W0

  (2622) 0x4c47ac SUB	W0, W19, #3

  (2622) 0x4c47b0 CMP	W3, #0

  (2622) 0x4c47b4 CCMP	W20, #0, #4, #0

  (2622) 0x4c47b8 CSINC	W24, WZR, WZR, #0

  (2622) 0x4c47bc BL	403de0

  (2622) 0x4c47c0 ORR	W4, WZR, W0

  (2622) 0x4c47c4 SUB	W0, W19, #4

  (2622) 0x4c47c8 CMP	W4, #0

  (2622) 0x4c47cc CCMP	W24, #0, #4, #0

  (2622) 0x4c47d0 CSINC	W22, WZR, WZR, #0

  (2622) 0x4c47d4 BL	403de0

  (2622) 0x4c47d8 ORR	W5, WZR, W0

  (2622) 0x4c47dc SUB	W0, W19, #5

  (2622) 0x4c47e0 CMP	W5, #0

  (2622) 0x4c47e4 CCMP	W22, #0, #4, #0

  (2622) 0x4c47e8 CSINC	W20, WZR, WZR, #0

  (2622) 0x4c47ec BL	403de0

  (2622) 0x4c47f0 ORR	W6, WZR, W0

  (2622) 0x4c47f4 SUB	W0, W19, #6

  (2622) 0x4c47f8 CMP	W6, #0

  (2622) 0x4c47fc CCMP	W20, #0, #4, #0

  (2622) 0x4c4800 CSINC	W24, WZR, WZR, #0

  (2622) 0x4c4804 BL	403de0

  (2622) 0x4c4808 ORR	W7, WZR, W0

  (2622) 0x4c480c SUB	W0, W19, #7

  (2622) 0x4c4810 CMP	W7, #0

  (2622) 0x4c4814 CCMP	W24, #0, #4, #0

  (2622) 0x4c4818 CSINC	W22, WZR, WZR, #0

  (2622) 0x4c481c BL	403de0

  (2622) 0x4c4820 CMP	W0, #0

  (2622) 0x4c4824 CCMP	W22, #0, #4, #0

  (2622) 0x4c4828 CSINC	W20, WZR, WZR, #0

  (2622) 0x4c482c SUBS	W19, W19, #8

  (2622) 0x4c4830 B.NE	4c4770

(2613) 0x4c4834 TBNZ	W20, #0, 4c484c

(2613) 0x4c4838 LDP	X19, X20, [SP, #16]

(2613) 0x4c483c LDP	X23, X24, [SP, #48]

(2613) 0x4c4840 LDP	X21, X22, [SP, #32]

(2613) 0x4c4844 LDP	X29, X30, [SP], #96

(2613) 0x4c4848 RET

(2613) 0x4c484c STP	X25, X26, [SP, #64]

(2613) 0x4c4850 ADD	X24, X23, #104

(2613) 0x4c4854 ADD	X20, X23, #112

(2613) 0x4c4858 STR	X27, [SP, #80]

(2613) 0x4c485c STR	D15, [SP, #88]

(2613) 0x4c4860 BL	403e30

(2613) 0x4c4864 LDR	X9, [X23]

(2613) 0x4c4868 ADRP	X8,

(2613) 0x4c486c LDR	D15, [X8, #2504]

(2613) 0x4c4870 LDR	D0, [X23, #8]

(2613) 0x4c4874 SUB	X0, X0, X9

(2613) 0x4c4878 LDR	X10, [X23, #16]

(2613) 0x4c487c SCVTF	D1, X0

(2613) 0x4c4880 LDR	X15, [X24, #16]

(2613) 0x4c4884 ADD	X11, X10, #1

(2613) 0x4c4888 FMUL	D15, D1, D15

(2613) 0x4c488c STR	X11, [X23, #16]

(2613) 0x4c4890 FADD	D2, D0, D15

(2613) 0x4c4894 STR	D2, [X23, #8]

(2613) 0x4c4898 CBZ	X15, 4c4a04

(2613) 0x4c489c LDR	X16, [X23, #80]

(2613) 0x4c48a0 ORR	X19, XZR, X20

  (2619) 0x4c48a4 ADD	X12, X15, #32

  (2619) 0x4c48a8 LDR	X13, [X15, #32]

  (2619) 0x4c48ac CMP	X13, X16

  (2619) 0x4c48b0 B.NE	4c49c0

  (2619) 0x4c48b4 LDR	X13, [X12, #8]

  (2619) 0x4c48b8 LDR	X14, [X23, #88]

  (2619) 0x4c48bc CMP	X14, X13

  (2619) 0x4c48c0 B.NE	4c49c4

  (2619) 0x4c48c4 ORR	X19, XZR, X15

  (2619) 0x4c48c8 LDR	X15, [X15, #16]

  (2619) 0x4c48cc CBNZ	X15, 4c48a4

(2613) 0x4c48d0 CMP	X20, X19

(2613) 0x4c48d4 B.EQ	4c4a04

(2613) 0x4c48d8 LDR	X17, [X19, #32]

(2613) 0x4c48dc ADD	X25, X19, #32

(2613) 0x4c48e0 CMP	X17, X16

(2613) 0x4c48e4 B.NE	4c4bcc

(2613) 0x4c48e8 LDR	X17, [X25, #8]

(2613) 0x4c48ec LDR	X16, [X23, #88]

(2613) 0x4c48f0 CMP	X16, X17

(2613) 0x4c48f4 B.NE	4c4bcc

(2613) 0x4c48f8 LDR	D31, [X19, #56]

(2613) 0x4c48fc ADD	X24, X23, #152

(2613) 0x4c4900 ADD	X20, X23, #160

(2613) 0x4c4904 LDR	X26, [X24, #16]

(2613) 0x4c4908 FADD	D3, D31, D15

(2613) 0x4c490c STR	D3, [X19, #56]

(2613) 0x4c4910 CBZ	X26, 4c4a9c

(2613) 0x4c4914 LDR	X5, [X23, #80]

(2613) 0x4c4918 ORR	X19, XZR, X20

(2613) 0x4c491c HINT	#0

  (2615) 0x4c4920 ADD	X30, X26, #32

  (2615) 0x4c4924 LDR	X3, [X26, #32]

  (2615) 0x4c4928 CMP	X3, X5

  (2615) 0x4c492c B.NE	4c49ac

  (2615) 0x4c4930 LDR	X3, [X30, #8]

  (2615) 0x4c4934 LDR	X6, [X23, #88]

  (2615) 0x4c4938 CMP	X6, X3

  (2615) 0x4c493c B.NE	4c49b0

  (2615) 0x4c4940 ORR	X19, XZR, X26

  (2615) 0x4c4944 LDR	X26, [X26, #16]

  (2615) 0x4c4948 CBNZ	X26, 4c4920

(2613) 0x4c494c CMP	X20, X19

(2613) 0x4c4950 B.EQ	4c4a9c

(2613) 0x4c4954 LDR	X7, [X19, #32]

(2613) 0x4c4958 ADD	X25, X19, #32

(2613) 0x4c495c CMP	X7, X5

(2613) 0x4c4960 B.NE	4c4d34

(2613) 0x4c4964 LDR	X7, [X25, #8]

(2613) 0x4c4968 LDR	X5, [X23, #88]

(2613) 0x4c496c CMP	X5, X7

(2613) 0x4c4970 B.NE	4c4d34

(2613) 0x4c4974 LDR	X24, [X19, #56]

(2613) 0x4c4978 LDR	X0, [X23, #72]

(2613) 0x4c497c ADD	X12, X24, #1

(2613) 0x4c4980 STR	X12, [X19, #56]

(2613) 0x4c4984 CBZ	X0, 4c49d4

0x4c4988 LDR	X27, [SP, #80]

0x4c498c ORR	X1, XZR, X23

0x4c4990 LDP	X19, X20, [SP, #16]

0x4c4994 LDP	X23, X24, [SP, #48]

0x4c4998 LDP	X25, X26, [SP, #64]

0x4c499c LDP	X21, X22, [SP, #32]

0x4c49a0 LDR	D15, [SP, #88]

0x4c49a4 LDP	X29, X30, [SP], #96

0x4c49a8 B	4ca340

  (2615) 0x4c49ac ORR	X6, XZR, X5

  (2615) 0x4c49b0 CMP	X6, X3

  (2615) 0x4c49b4 B.LE	4c4940

  (2615) 0x4c49b8 LDR	X26, [X26, #24]

  (2615) 0x4c49bc B	4c4948

  (2619) 0x4c49c0 ORR	X14, XZR, X16

  (2619) 0x4c49c4 CMP	X14, X13

  (2619) 0x4c49c8 B.LE	4c48c4

  (2619) 0x4c49cc LDR	X15, [X15, #24]

  (2619) 0x4c49d0 B	4c48cc

(2613) 0x4c49d4 LDR	X27, [SP, #80]

(2613) 0x4c49d8 LDP	X19, X20, [SP, #16]

(2613) 0x4c49dc LDP	X23, X24, [SP, #48]

(2613) 0x4c49e0 LDP	X25, X26, [SP, #64]

(2613) 0x4c49e4 LDR	D15, [SP, #88]

(2613) 0x4c49e8 B	4c4674

(2613) 0x4c49ec BL	403de0

(2613) 0x4c49f0 CMP	W0, #0

(2613) 0x4c49f4 ORR	W19, WZR, W22

(2613) 0x4c49f8 CCMP	W21, #0, #4, #0

(2613) 0x4c49fc CSINC	W20, WZR, WZR, #0

(2613) 0x4c4a00 B	4c46dc

(2613) 0x4c4a04 MOVZ	X0, #64

(2613) 0x4c4a08 BL	403e80

(2613) 0x4c4a0c LDP	X6, X7, [X23, #80]

(2613) 0x4c4a10 ADD	X25, X0, #32

(2613) 0x4c4a14 ORR	X26, XZR, X0

(2613) 0x4c4a18 ORR	X27, XZR, X0

(2613) 0x4c4a1c LDR	X5, [X23, #96]

(2613) 0x4c4a20 STP	X6, X7, [X0, #32]

(2613) 0x4c4a24 LDR	X7, [X24, #40]

(2613) 0x4c4a28 STP	X5, XZR, [X25, #16]

(2613) 0x4c4a2c CBZ	X7, 4c4a58

(2613) 0x4c4a30 LDR	X2, [X23, #136]

(2613) 0x4c4a34 LDR	X19, [X26, #32]

(2613) 0x4c4a38 LDR	X9, [X2, #32]

(2613) 0x4c4a3c ADD	X8, X2, #32

(2613) 0x4c4a40 CMP	X9, X19

(2613) 0x4c4a44 B.NE	4c522c

(2613) 0x4c4a48 LDR	X10, [X8, #8]

(2613) 0x4c4a4c LDR	X0, [X25, #8]

(2613) 0x4c4a50 CMP	X10, X0

(2613) 0x4c4a54 B.NE	4c520c

(2613) 0x4c4a58 LDR	X19, [X24, #16]

(2613) 0x4c4a5c CBZ	X19, 4c5134

(2613) 0x4c4a60 LDR	X22, [X26, #32]

(2613) 0x4c4a64 ORR	X4, XZR, X22

  (2618) 0x4c4a68 LDR	X1, [X19, #32]

  (2618) 0x4c4a6c ADD	X12, X19, #32

  (2618) 0x4c4a70 CMP	X1, X22

  (2618) 0x4c4a74 B.NE	4c4bb0

  (2618) 0x4c4a78 LDR	X13, [X12, #8]

  (2618) 0x4c4a7c LDR	X14, [X25, #8]

  (2618) 0x4c4a80 CMP	X13, X14

  (2618) 0x4c4a84 B.NE	4c4bb8

  (2618) 0x4c4a88 LDR	X18, [X19, #24]

  (2618) 0x4c4a8c MOVZ	W15, #0

  (2618) 0x4c4a90 CBZ	X18, 4c4b34

  (2618) 0x4c4a94 ORR	X19, XZR, X18

  (2618) 0x4c4a98 B	4c4a68

(2613) 0x4c4a9c MOVZ	X0, #64

(2613) 0x4c4aa0 BL	403e80

(2613) 0x4c4aa4 LDP	X12, X13, [X23, #80]

(2613) 0x4c4aa8 ADD	X25, X0, #32

(2613) 0x4c4aac ORR	X26, XZR, X0

(2613) 0x4c4ab0 ORR	X27, XZR, X0

(2613) 0x4c4ab4 LDR	X14, [X24, #40]

(2613) 0x4c4ab8 STP	X12, X13, [X0, #32]

(2613) 0x4c4abc LDR	X13, [X23, #96]

(2613) 0x4c4ac0 STP	X13, XZR, [X25, #16]

(2613) 0x4c4ac4 CBZ	X14, 4c4af0

(2613) 0x4c4ac8 LDR	X2, [X23, #184]

(2613) 0x4c4acc LDR	X18, [X26, #32]

(2613) 0x4c4ad0 LDR	X15, [X2, #32]

(2613) 0x4c4ad4 ADD	X4, X2, #32

(2613) 0x4c4ad8 CMP	X15, X18

(2613) 0x4c4adc B.NE	4c51e4

(2613) 0x4c4ae0 LDR	X19, [X4, #8]

(2613) 0x4c4ae4 LDR	X16, [X25, #8]

(2613) 0x4c4ae8 CMP	X19, X16

(2613) 0x4c4aec B.NE	4c51c4

(2613) 0x4c4af0 LDR	X19, [X24, #16]

(2613) 0x4c4af4 CBZ	X19, 4c514c

(2613) 0x4c4af8 LDR	X22, [X26, #32]

(2613) 0x4c4afc ORR	X9, XZR, X22

  (2614) 0x4c4b00 LDR	X8, [X19, #32]

  (2614) 0x4c4b04 ADD	X2, X19, #32

  (2614) 0x4c4b08 CMP	X22, X8

  (2614) 0x4c4b0c B.NE	4c4b94

  (2614) 0x4c4b10 LDR	X1, [X2, #8]

  (2614) 0x4c4b14 LDR	X6, [X25, #8]

  (2614) 0x4c4b18 CMP	X1, X6

  (2614) 0x4c4b1c B.NE	4c4b9c

  (2614) 0x4c4b20 LDR	X7, [X19, #24]

  (2614) 0x4c4b24 MOVZ	W5, #0

  (2614) 0x4c4b28 CBZ	X7, 4c4b64

  (2614) 0x4c4b2c ORR	X19, XZR, X7

  (2614) 0x4c4b30 B	4c4b00

(2613) 0x4c4b34 ORR	X2, XZR, X19

(2613) 0x4c4b38 TBNZ	W15, #0, 4c4fe0

(2613) 0x4c4b3c CMP	X22, X1

(2613) 0x4c4b40 B.NE	4c5100

(2613) 0x4c4b44 LDR	X4, [X25, #8]

(2613) 0x4c4b48 LDR	X1, [X19, #40]

(2613) 0x4c4b4c CMP	X1, X4

(2613) 0x4c4b50 B.NE	4c5100

(2613) 0x4c4b54 ORR	X0, XZR, X27

(2613) 0x4c4b58 MOVZ	X1, #64

(2613) 0x4c4b5c BL	403d70

(2613) 0x4c4b60 B	4c48f8

(2613) 0x4c4b64 ORR	X2, XZR, X19

(2613) 0x4c4b68 TBNZ	W5, #0, 4c4fb8

(2613) 0x4c4b6c CMP	X22, X8

(2613) 0x4c4b70 B.NE	4c50f0

(2613) 0x4c4b74 LDR	X9, [X25, #8]

(2613) 0x4c4b78 LDR	X8, [X19, #40]

(2613) 0x4c4b7c CMP	X8, X9

(2613) 0x4c4b80 B.NE	4c50f0

(2613) 0x4c4b84 ORR	X0, XZR, X27

(2613) 0x4c4b88 MOVZ	X1, #64

(2613) 0x4c4b8c BL	403d70

(2613) 0x4c4b90 B	4c4974

  (2614) 0x4c4b94 ORR	X1, XZR, X8

  (2614) 0x4c4b98 ORR	X6, XZR, X22

  (2614) 0x4c4b9c CMP	X1, X6

  (2614) 0x4c4ba0 B.LE	4c4b20

  (2614) 0x4c4ba4 LDR	X7, [X19, #16]

  (2614) 0x4c4ba8 ORR	W5, WZR, W21

  (2614) 0x4c4bac B	4c4b28

  (2618) 0x4c4bb0 ORR	X13, XZR, X1

  (2618) 0x4c4bb4 ORR	X14, XZR, X22

  (2618) 0x4c4bb8 CMP	X13, X14

  (2618) 0x4c4bbc B.LE	4c4a88

  (2618) 0x4c4bc0 LDR	X18, [X19, #16]

  (2618) 0x4c4bc4 ORR	W15, WZR, W21

  (2618) 0x4c4bc8 B	4c4a90

(2613) 0x4c4bcc CMP	X16, X17

(2613) 0x4c4bd0 B.GE	4c48f8

(2613) 0x4c4bd4 MOVZ	X0, #64

(2613) 0x4c4bd8 BL	403e80

(2613) 0x4c4bdc LDP	X22, X18, [X23, #80]

(2613) 0x4c4be0 ADD	X26, X0, #32

(2613) 0x4c4be4 ORR	X27, XZR, X0

(2613) 0x4c4be8 LDR	X1, [X23, #96]

(2613) 0x4c4bec STP	X22, X18, [X0, #32]

(2613) 0x4c4bf0 STP	X1, XZR, [X26, #16]

(2613) 0x4c4bf4 LDR	X2, [X19, #32]

(2613) 0x4c4bf8 CMP	X22, X2

(2613) 0x4c4bfc B.NE	4c4c84

(2613) 0x4c4c00 LDR	X30, [X25, #8]

(2613) 0x4c4c04 LDR	X3, [X26, #8]

(2613) 0x4c4c08 CMP	X3, X30

(2613) 0x4c4c0c B.LT	4c4c88

(2613) 0x4c4c10 B.EQ	4c4b54

(2613) 0x4c4c14 LDR	X4, [X23, #136]

(2613) 0x4c4c18 CMP	X19, X4

(2613) 0x4c4c1c B.EQ	4c5014

(2613) 0x4c4c20 ORR	X0, XZR, X19

(2613) 0x4c4c24 BL	403d40

(2613) 0x4c4c28 LDR	X6, [X0, #32]

(2613) 0x4c4c2c ADD	X5, X0, #32

(2613) 0x4c4c30 CMP	X6, X22

(2613) 0x4c4c34 B.NE	4c52bc

(2613) 0x4c4c38 LDR	X7, [X5, #8]

(2613) 0x4c4c3c LDR	X8, [X26, #8]

(2613) 0x4c4c40 CMP	X8, X7

(2613) 0x4c4c44 B.NE	4c52a4

(2613) 0x4c4c48 LDR	X19, [X24, #16]

(2613) 0x4c4c4c CBZ	X19, 4c52d4

  (2620) 0x4c4c50 LDR	X15, [X19, #32]

  (2620) 0x4c4c54 ADD	X10, X19, #32

  (2620) 0x4c4c58 CMP	X15, X22

  (2620) 0x4c4c5c B.NE	4c5094

  (2620) 0x4c4c60 LDR	X0, [X10, #8]

  (2620) 0x4c4c64 LDR	X11, [X26, #8]

  (2620) 0x4c4c68 CMP	X0, X11

  (2620) 0x4c4c6c B.NE	4c509c

  (2620) 0x4c4c70 LDR	X13, [X19, #24]

  (2620) 0x4c4c74 MOVZ	W12, #0

  (2620) 0x4c4c78 CBZ	X13, 4c5020

  (2620) 0x4c4c7c ORR	X19, XZR, X13

  (2620) 0x4c4c80 B	4c4c50

(2613) 0x4c4c84 B.GE	4c4c14

(2613) 0x4c4c88 LDR	X25, [X23, #128]

(2613) 0x4c4c8c CMP	X19, X25

(2613) 0x4c4c90 B.EQ	4c4d0c

(2613) 0x4c4c94 ORR	X0, XZR, X19

(2613) 0x4c4c98 BL	403f30

(2613) 0x4c4c9c LDR	X18, [X0, #32]

(2613) 0x4c4ca0 ORR	X2, XZR, X0

(2613) 0x4c4ca4 CMP	X18, X22

(2613) 0x4c4ca8 B.NE	4c4cf8

(2613) 0x4c4cac LDR	X16, [X26, #8]

(2613) 0x4c4cb0 LDR	X18, [X0, #40]

(2613) 0x4c4cb4 CMP	X18, X16

(2613) 0x4c4cb8 B.NE	4c4cfc

(2613) 0x4c4cbc LDR	X19, [X24, #16]

(2613) 0x4c4cc0 CBZ	X19, 4c5198

  (2621) 0x4c4cc4 LDR	X3, [X19, #32]

  (2621) 0x4c4cc8 ADD	X17, X19, #32

  (2621) 0x4c4ccc CMP	X3, X22

  (2621) 0x4c4cd0 B.NE	4c4f34

  (2621) 0x4c4cd4 LDR	X1, [X17, #8]

  (2621) 0x4c4cd8 LDR	X2, [X26, #8]

  (2621) 0x4c4cdc CMP	X1, X2

  (2621) 0x4c4ce0 B.NE	4c4f3c

  (2621) 0x4c4ce4 LDR	X4, [X19, #24]

  (2621) 0x4c4ce8 MOVZ	W30, #0

  (2621) 0x4c4cec CBZ	X4, 4c4f50

  (2621) 0x4c4cf0 ORR	X19, XZR, X4

  (2621) 0x4c4cf4 B	4c4cc4

(2613) 0x4c4cf8 ORR	X16, XZR, X22

(2613) 0x4c4cfc CMP	X18, X16

(2613) 0x4c4d00 B.GE	4c4cbc

(2613) 0x4c4d04 LDR	X22, [X2, #24]

(2613) 0x4c4d08 CBZ	X22, 4c4f78

(2613) 0x4c4d0c ORR	X2, XZR, X19

(2613) 0x4c4d10 ORR	W0, WZR, W21

(2613) 0x4c4d14 ORR	X19, XZR, X27

(2613) 0x4c4d18 ORR	X3, XZR, X20

(2613) 0x4c4d1c ORR	X1, XZR, X19

(2613) 0x4c4d20 BL	403be0

(2613) 0x4c4d24 LDR	X20, [X24, #40]

(2613) 0x4c4d28 ADD	X2, X20, #1

(2613) 0x4c4d2c STR	X2, [X24, #40]

(2613) 0x4c4d30 B	4c48f8

(2613) 0x4c4d34 CMP	X5, X7

(2613) 0x4c4d38 B.GE	4c4974

(2613) 0x4c4d3c MOVZ	X0, #64

(2613) 0x4c4d40 BL	403e80

(2613) 0x4c4d44 LDP	X22, X8, [X23, #80]

(2613) 0x4c4d48 ADD	X26, X0, #32

(2613) 0x4c4d4c ORR	X27, XZR, X0

(2613) 0x4c4d50 LDR	X9, [X23, #96]

(2613) 0x4c4d54 STP	X22, X8, [X0, #32]

(2613) 0x4c4d58 STP	X9, XZR, [X26, #16]

(2613) 0x4c4d5c LDR	X10, [X19, #32]

(2613) 0x4c4d60 CMP	X22, X10

(2613) 0x4c4d64 B.NE	4c4df4

(2613) 0x4c4d68 LDR	X0, [X25, #8]

(2613) 0x4c4d6c LDR	X11, [X26, #8]

(2613) 0x4c4d70 CMP	X11, X0

(2613) 0x4c4d74 B.LT	4c4df8

(2613) 0x4c4d78 B.EQ	4c4b84

(2613) 0x4c4d7c LDR	X12, [X23, #184]

(2613) 0x4c4d80 CMP	X12, X19

(2613) 0x4c4d84 B.EQ	4c5008

(2613) 0x4c4d88 ORR	X0, XZR, X19

(2613) 0x4c4d8c BL	403d40

(2613) 0x4c4d90 LDR	X13, [X0, #32]

(2613) 0x4c4d94 ORR	X2, XZR, X0

(2613) 0x4c4d98 ADD	X4, X0, #32

(2613) 0x4c4d9c CMP	X13, X22

(2613) 0x4c4da0 B.NE	4c5280

(2613) 0x4c4da4 LDR	X14, [X4, #8]

(2613) 0x4c4da8 LDR	X15, [X26, #8]

(2613) 0x4c4dac CMP	X15, X14

(2613) 0x4c4db0 B.NE	4c5268

(2613) 0x4c4db4 LDR	X19, [X24, #16]

(2613) 0x4c4db8 CBZ	X19, 4c5254

(2613) 0x4c4dbc HINT	#0

  (2616) 0x4c4dc0 LDR	X3, [X19, #32]

  (2616) 0x4c4dc4 ADD	X16, X19, #32

  (2616) 0x4c4dc8 CMP	X3, X22

  (2616) 0x4c4dcc B.NE	4c5078

  (2616) 0x4c4dd0 LDR	X4, [X16, #8]

  (2616) 0x4c4dd4 LDR	X17, [X26, #8]

  (2616) 0x4c4dd8 CMP	X4, X17

  (2616) 0x4c4ddc B.NE	4c5080

  (2616) 0x4c4de0 LDR	X2, [X19, #24]

  (2616) 0x4c4de4 MOVZ	W30, #0

  (2616) 0x4c4de8 CBZ	X2, 4c504c

  (2616) 0x4c4dec ORR	X19, XZR, X2

  (2616) 0x4c4df0 B	4c4dc0

(2613) 0x4c4df4 B.GE	4c4d7c

(2613) 0x4c4df8 LDR	X25, [X23, #176]

(2613) 0x4c4dfc CMP	X25, X19

(2613) 0x4c4e00 B.EQ	4c4e88

(2613) 0x4c4e04 ORR	X0, XZR, X19

(2613) 0x4c4e08 BL	403f30

(2613) 0x4c4e0c LDR	X6, [X0, #32]

(2613) 0x4c4e10 ORR	X2, XZR, X0

(2613) 0x4c4e14 CMP	X6, X22

(2613) 0x4c4e18 B.NE	4c4e74

(2613) 0x4c4e1c LDR	X5, [X26, #8]

(2613) 0x4c4e20 LDR	X6, [X0, #40]

(2613) 0x4c4e24 CMP	X6, X5

(2613) 0x4c4e28 B.NE	4c4e78

(2613) 0x4c4e2c LDR	X19, [X24, #16]

(2613) 0x4c4e30 CBZ	X19, 4c5188

(2613) 0x4c4e34 HINT	#0

(2613) 0x4c4e38 HINT	#0

(2613) 0x4c4e3c HINT	#0

  (2617) 0x4c4e40 LDR	X11, [X19, #32]

  (2617) 0x4c4e44 ADD	X7, X19, #32

  (2617) 0x4c4e48 CMP	X11, X22

  (2617) 0x4c4e4c B.NE	4c4eb0

  (2617) 0x4c4e50 LDR	X8, [X7, #8]

  (2617) 0x4c4e54 LDR	X9, [X26, #8]

  (2617) 0x4c4e58 CMP	X8, X9

  (2617) 0x4c4e5c B.NE	4c4eb8

  (2617) 0x4c4e60 LDR	X0, [X19, #24]

  (2617) 0x4c4e64 MOVZ	W10, #0

  (2617) 0x4c4e68 CBZ	X0, 4c4ecc

  (2617) 0x4c4e6c ORR	X19, XZR, X0

  (2617) 0x4c4e70 B	4c4e40

(2613) 0x4c4e74 ORR	X5, XZR, X22

(2613) 0x4c4e78 CMP	X6, X5

(2613) 0x4c4e7c B.GE	4c4e2c

(2613) 0x4c4e80 LDR	X22, [X2, #24]

(2613) 0x4c4e84 CBZ	X22, 4c4ef4

(2613) 0x4c4e88 ORR	X2, XZR, X19

(2613) 0x4c4e8c ORR	X19, XZR, X27

(2613) 0x4c4e90 ORR	X3, XZR, X20

(2613) 0x4c4e94 ORR	W0, WZR, W21

(2613) 0x4c4e98 ORR	X1, XZR, X19

(2613) 0x4c4e9c BL	403be0

(2613) 0x4c4ea0 LDR	X20, [X24, #40]

(2613) 0x4c4ea4 ADD	X11, X20, #1

(2613) 0x4c4ea8 STR	X11, [X24, #40]

(2613) 0x4c4eac B	4c4974

  (2617) 0x4c4eb0 ORR	X8, XZR, X11

  (2617) 0x4c4eb4 ORR	X9, XZR, X22

  (2617) 0x4c4eb8 CMP	X8, X9

  (2617) 0x4c4ebc B.LE	4c4e60

  (2617) 0x4c4ec0 LDR	X0, [X19, #16]

  (2617) 0x4c4ec4 ORR	W10, WZR, W21

  (2617) 0x4c4ec8 B	4c4e68

(2613) 0x4c4ecc ORR	X2, XZR, X19

(2613) 0x4c4ed0 TBNZ	W10, #0, 4c50d0

(2613) 0x4c4ed4 CMP	X22, X11

(2613) 0x4c4ed8 B.NE	4c4eec

(2613) 0x4c4edc LDR	X22, [X26, #8]

(2613) 0x4c4ee0 LDR	X11, [X19, #40]

(2613) 0x4c4ee4 CMP	X11, X22

(2613) 0x4c4ee8 B.EQ	4c4b84

(2613) 0x4c4eec CMP	X11, X22

(2613) 0x4c4ef0 B.GE	4c4b84

(2613) 0x4c4ef4 ORR	X19, XZR, X27

(2613) 0x4c4ef8 CMP	X20, X2

(2613) 0x4c4efc B.EQ	4c4e90

(2613) 0x4c4f00 LDR	X10, [X2, #32]

(2613) 0x4c4f04 LDR	X0, [X19, #32]

(2613) 0x4c4f08 CMP	X10, X0

(2613) 0x4c4f0c B.NE	4c4f28

(2613) 0x4c4f10 ADD	X4, X2, #32

(2613) 0x4c4f14 LDR	X10, [X4, #8]

(2613) 0x4c4f18 MOVZ	W21, #0

(2613) 0x4c4f1c LDR	X0, [X19, #40]

(2613) 0x4c4f20 CMP	X10, X0

(2613) 0x4c4f24 B.EQ	4c4e90

(2613) 0x4c4f28 CMP	X0, X10

(2613) 0x4c4f2c CSINC	W21, WZR, WZR, #10

(2613) 0x4c4f30 B	4c4e90

  (2621) 0x4c4f34 ORR	X1, XZR, X3

  (2621) 0x4c4f38 ORR	X2, XZR, X22

  (2621) 0x4c4f3c CMP	X1, X2

  (2621) 0x4c4f40 B.LE	4c4ce4

  (2621) 0x4c4f44 LDR	X4, [X19, #16]

  (2621) 0x4c4f48 ORR	W30, WZR, W21

  (2621) 0x4c4f4c B	4c4cec

(2613) 0x4c4f50 ORR	X2, XZR, X19

(2613) 0x4c4f54 TBNZ	W30, #0, 4c50b0

(2613) 0x4c4f58 CMP	X22, X3

(2613) 0x4c4f5c B.NE	4c4f70

(2613) 0x4c4f60 LDR	X22, [X26, #8]

(2613) 0x4c4f64 LDR	X3, [X19, #40]

(2613) 0x4c4f68 CMP	X3, X22

(2613) 0x4c4f6c B.EQ	4c4b54

(2613) 0x4c4f70 CMP	X3, X22

(2613) 0x4c4f74 B.GE	4c4b54

(2613) 0x4c4f78 ORR	X19, XZR, X27

(2613) 0x4c4f7c ORR	W0, WZR, W21

(2613) 0x4c4f80 CMP	X20, X2

(2613) 0x4c4f84 B.EQ	4c4d18

(2613) 0x4c4f88 LDR	X27, [X2, #32]

(2613) 0x4c4f8c LDR	X17, [X19, #32]

(2613) 0x4c4f90 CMP	X17, X27

(2613) 0x4c4f94 B.NE	4c4fac

(2613) 0x4c4f98 LDR	X27, [X2, #40]

(2613) 0x4c4f9c MOVZ	W0, #0

(2613) 0x4c4fa0 LDR	X17, [X19, #40]

(2613) 0x4c4fa4 CMP	X17, X27

(2613) 0x4c4fa8 B.EQ	4c4d18

(2613) 0x4c4fac CMP	X17, X27

(2613) 0x4c4fb0 CSINC	W0, WZR, WZR, #10

(2613) 0x4c4fb4 B	4c4d18

(2613) 0x4c4fb8 LDR	X3, [X24, #24]

(2613) 0x4c4fbc CMP	X3, X19

(2613) 0x4c4fc0 B.EQ	4c50f8

(2613) 0x4c4fc4 ORR	X0, XZR, X19

(2613) 0x4c4fc8 BL	403f30

(2613) 0x4c4fcc LDR	X8, [X0, #32]

(2613) 0x4c4fd0 ORR	X2, XZR, X19

(2613) 0x4c4fd4 ORR	X9, XZR, X22

(2613) 0x4c4fd8 ORR	X19, XZR, X0

(2613) 0x4c4fdc B	4c4b6c

(2613) 0x4c4fe0 LDR	X16, [X24, #24]

(2613) 0x4c4fe4 CMP	X16, X19

(2613) 0x4c4fe8 B.EQ	4c5108

(2613) 0x4c4fec ORR	X0, XZR, X19

(2613) 0x4c4ff0 BL	403f30

(2613) 0x4c4ff4 LDR	X1, [X0, #32]

(2613) 0x4c4ff8 ORR	X2, XZR, X19

(2613) 0x4c4ffc ORR	X4, XZR, X22

(2613) 0x4c5000 ORR	X19, XZR, X0

(2613) 0x4c5004 B	4c4b3c

(2613) 0x4c5008 ORR	X2, XZR, X19

(2613) 0x4c500c ORR	X19, XZR, X27

(2613) 0x4c5010 B	4c4f00

(2613) 0x4c5014 ORR	X2, XZR, X19

(2613) 0x4c5018 ORR	X19, XZR, X27

(2613) 0x4c501c B	4c4f88

(2613) 0x4c5020 ORR	X2, XZR, X19

(2613) 0x4c5024 TBNZ	W12, #0, 4c5110

(2613) 0x4c5028 CMP	X22, X15

(2613) 0x4c502c B.NE	4c5040

(2613) 0x4c5030 LDR	X22, [X26, #8]

(2613) 0x4c5034 LDR	X15, [X19, #40]

(2613) 0x4c5038 CMP	X15, X22

(2613) 0x4c503c B.EQ	4c4b54

(2613) 0x4c5040 CMP	X15, X22

(2613) 0x4c5044 B.LT	4c4f78

(2613) 0x4c5048 B	4c4b54

(2613) 0x4c504c ORR	X2, XZR, X19

(2613) 0x4c5050 TBNZ	W30, #0, 4c5164

(2613) 0x4c5054 CMP	X22, X3

(2613) 0x4c5058 B.NE	4c506c

(2613) 0x4c505c LDR	X22, [X26, #8]

(2613) 0x4c5060 LDR	X3, [X19, #40]

(2613) 0x4c5064 CMP	X3, X22

(2613) 0x4c5068 B.EQ	4c4b84

(2613) 0x4c506c CMP	X3, X22

(2613) 0x4c5070 B.LT	4c4ef4

(2613) 0x4c5074 B	4c4b84

  (2616) 0x4c5078 ORR	X4, XZR, X3

  (2616) 0x4c507c ORR	X17, XZR, X22

  (2616) 0x4c5080 CMP	X4, X17

  (2616) 0x4c5084 B.LE	4c4de0

  (2616) 0x4c5088 LDR	X2, [X19, #16]

  (2616) 0x4c508c ORR	W30, WZR, W21

  (2616) 0x4c5090 B	4c4de8

  (2620) 0x4c5094 ORR	X0, XZR, X15

  (2620) 0x4c5098 ORR	X11, XZR, X22

  (2620) 0x4c509c CMP	X0, X11

  (2620) 0x4c50a0 B.LE	4c4c70

  (2620) 0x4c50a4 LDR	X13, [X19, #16]

  (2620) 0x4c50a8 ORR	W12, WZR, W21

  (2620) 0x4c50ac B	4c4c78

(2613) 0x4c50b0 CMP	X25, X19

(2613) 0x4c50b4 B.EQ	4c4f78

(2613) 0x4c50b8 ORR	X0, XZR, X19

(2613) 0x4c50bc BL	403f30

(2613) 0x4c50c0 LDR	X3, [X0, #32]

(2613) 0x4c50c4 ORR	X2, XZR, X19

(2613) 0x4c50c8 ORR	X19, XZR, X0

(2613) 0x4c50cc B	4c4f58

(2613) 0x4c50d0 CMP	X25, X19

(2613) 0x4c50d4 B.EQ	4c4ef4

(2613) 0x4c50d8 ORR	X0, XZR, X19

(2613) 0x4c50dc BL	403f30

(2613) 0x4c50e0 LDR	X11, [X0, #32]

(2613) 0x4c50e4 ORR	X2, XZR, X19

(2613) 0x4c50e8 ORR	X19, XZR, X0

(2613) 0x4c50ec B	4c4ed4

(2613) 0x4c50f0 CMP	X8, X9

(2613) 0x4c50f4 B.GE	4c4b84

(2613) 0x4c50f8 ORR	X19, XZR, X26

(2613) 0x4c50fc B	4c4ef8

(2613) 0x4c5100 CMP	X1, X4

(2613) 0x4c5104 B.GE	4c4b54

(2613) 0x4c5108 ORR	X19, XZR, X26

(2613) 0x4c510c B	4c4f7c

(2613) 0x4c5110 LDR	X14, [X24, #24]

(2613) 0x4c5114 CMP	X19, X14

(2613) 0x4c5118 B.EQ	4c4f78

(2613) 0x4c511c ORR	X0, XZR, X19

(2613) 0x4c5120 BL	403f30

(2613) 0x4c5124 LDR	X15, [X0, #32]

(2613) 0x4c5128 ORR	X2, XZR, X19

(2613) 0x4c512c ORR	X19, XZR, X0

(2613) 0x4c5130 B	4c5028

(2613) 0x4c5134 LDR	X11, [X24, #24]

(2613) 0x4c5138 CMP	X20, X11

(2613) 0x4c513c B.EQ	4c51a8

(2613) 0x4c5140 LDR	X22, [X26, #32]

(2613) 0x4c5144 ORR	X19, XZR, X20

(2613) 0x4c5148 B	4c4fec

(2613) 0x4c514c LDR	X30, [X24, #24]

(2613) 0x4c5150 CMP	X20, X30

(2613) 0x4c5154 B.EQ	4c51b8

(2613) 0x4c5158 LDR	X22, [X26, #32]

(2613) 0x4c515c ORR	X19, XZR, X20

(2613) 0x4c5160 B	4c4fc4

(2613) 0x4c5164 LDR	X1, [X24, #24]

(2613) 0x4c5168 CMP	X1, X19

(2613) 0x4c516c B.EQ	4c4ef4

(2613) 0x4c5170 ORR	X0, XZR, X19

(2613) 0x4c5174 BL	403f30

(2613) 0x4c5178 LDR	X3, [X0, #32]

(2613) 0x4c517c ORR	X2, XZR, X19

(2613) 0x4c5180 ORR	X19, XZR, X0

(2613) 0x4c5184 B	4c5054

(2613) 0x4c5188 CMP	X20, X25

(2613) 0x4c518c B.EQ	4c5298

(2613) 0x4c5190 ORR	X19, XZR, X20

(2613) 0x4c5194 B	4c50d8

(2613) 0x4c5198 CMP	X20, X25

(2613) 0x4c519c B.EQ	4c52e8

(2613) 0x4c51a0 ORR	X19, XZR, X20

(2613) 0x4c51a4 B	4c50b8

(2613) 0x4c51a8 ORR	X19, XZR, X26

(2613) 0x4c51ac ORR	X2, XZR, X20

(2613) 0x4c51b0 ORR	W0, WZR, W21

(2613) 0x4c51b4 B	4c4d18

(2613) 0x4c51b8 ORR	X19, XZR, X26

(2613) 0x4c51bc ORR	X2, XZR, X20

(2613) 0x4c51c0 B	4c4e90

(2613) 0x4c51c4 B.GE	4c4af0

(2613) 0x4c51c8 MOVZ	X17, #0

(2613) 0x4c51cc ORR	X19, XZR, X26

(2613) 0x4c51d0 CMP	X17, #0

(2613) 0x4c51d4 CCMP	X20, X2, #4, #0

(2613) 0x4c51d8 CSINC	W21, WZR, WZR, #1

(2613) 0x4c51dc CBNZ	W21, 4c4e90

(2613) 0x4c51e0 B	4c4f14

(2613) 0x4c51e4 B.GE	4c4af0

(2613) 0x4c51e8 MOVZ	X21, #0

(2613) 0x4c51ec ORR	X19, XZR, X26

(2613) 0x4c51f0 CMP	X21, #0

(2613) 0x4c51f4 CCMP	X20, X2, #4, #0

(2613) 0x4c51f8 CSINC	W21, WZR, WZR, #1

(2613) 0x4c51fc CBNZ	W21, 4c4e90

(2613) 0x4c5200 LDR	X10, [X2, #32]

(2613) 0x4c5204 LDR	X0, [X19, #32]

(2613) 0x4c5208 B	4c4f28

(2613) 0x4c520c B.GE	4c4a58

(2613) 0x4c5210 MOVZ	X0, #0

(2613) 0x4c5214 ORR	X19, XZR, X26

(2613) 0x4c5218 CMP	X0, #0

(2613) 0x4c521c CCMP	X20, X2, #4, #0

(2613) 0x4c5220 CSINC	W0, WZR, WZR, #1

(2613) 0x4c5224 CBNZ	W0, 4c4d18

(2613) 0x4c5228 B	4c4f98

(2613) 0x4c522c B.GE	4c4a58

(2613) 0x4c5230 MOVZ	X0, #0

(2613) 0x4c5234 ORR	X19, XZR, X26

(2613) 0x4c5238 CMP	X0, #0

(2613) 0x4c523c CCMP	X20, X2, #4, #0

(2613) 0x4c5240 CSINC	W0, WZR, WZR, #1

(2613) 0x4c5244 CBNZ	W0, 4c4d18

(2613) 0x4c5248 LDR	X27, [X2, #32]

(2613) 0x4c524c LDR	X17, [X19, #32]

(2613) 0x4c5250 B	4c4fac

(2613) 0x4c5254 LDR	X19, [X24, #24]

(2613) 0x4c5258 CMP	X20, X19

(2613) 0x4c525c B.EQ	4c5298

(2613) 0x4c5260 ORR	X19, XZR, X20

(2613) 0x4c5264 B	4c5170

(2613) 0x4c5268 B.GE	4c4db4

(2613) 0x4c526c LDR	X18, [X19, #24]

(2613) 0x4c5270 CBZ	X18, 4c5008

(2613) 0x4c5274 ORR	X19, XZR, X27

(2613) 0x4c5278 ORR	X17, XZR, X0

(2613) 0x4c527c B	4c51d0

(2613) 0x4c5280 B.LE	4c4db4

(2613) 0x4c5284 LDR	X21, [X19, #24]

(2613) 0x4c5288 CBZ	X21, 4c5008

(2613) 0x4c528c ORR	X19, XZR, X27

(2613) 0x4c5290 ORR	X21, XZR, X0

(2613) 0x4c5294 B	4c51f0

(2613) 0x4c5298 ORR	X19, XZR, X27

(2613) 0x4c529c ORR	X2, XZR, X20

(2613) 0x4c52a0 B	4c4e90

(2613) 0x4c52a4 B.GE	4c4c48

(2613) 0x4c52a8 LDR	X9, [X19, #24]

(2613) 0x4c52ac CBZ	X9, 4c5014

(2613) 0x4c52b0 ORR	X19, XZR, X27

(2613) 0x4c52b4 ORR	X2, XZR, X0

(2613) 0x4c52b8 B	4c5218

(2613) 0x4c52bc B.LE	4c4c48

(2613) 0x4c52c0 LDR	X25, [X19, #24]

(2613) 0x4c52c4 CBZ	X25, 4c5014

(2613) 0x4c52c8 ORR	X19, XZR, X27

(2613) 0x4c52cc ORR	X2, XZR, X0

(2613) 0x4c52d0 B	4c5238

(2613) 0x4c52d4 LDR	X19, [X24, #24]

(2613) 0x4c52d8 CMP	X20, X19

(2613) 0x4c52dc B.EQ	4c52e8

(2613) 0x4c52e0 ORR	X19, XZR, X20

(2613) 0x4c52e4 B	4c511c

(2613) 0x4c52e8 ORR	X19, XZR, X27

(2613) 0x4c52ec ORR	X2, XZR, X20

(2613) 0x4c52f0 ORR	W0, WZR, W21

(2613) 0x4c52f4 B	4c4d18

0x4c52f8 HINT	#0

0x4c52fc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_tree.h:269,283,298-299,631,733,748,778,786,1636,1947-1949,2109-2125,2217-2230,2242-2246,2373-2383,2459
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-124
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_map.h:511
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/chrono.h:214,716
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/tuple:2887-2888
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h:151,172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 0.67 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 3.33 to 0.83 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 97 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00
cycles	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.75
Overall L1	3.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

30% of peak load performance is reached (29.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c4660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ W21, #0, 4c4680 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4ca340 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_tree.h:269,283,298-299,631,733,748,778,786,1636,1947-1949,2109-2125,2217-2230,2242-2246,2373-2383,2459
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-124
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_map.h:511
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/chrono.h:214,716
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/tuple:2887-2888
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h:151,172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 0.67 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 97 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00
cycles	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.75
Overall L1	3.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

30% of peak load performance is reached (29.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c4660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ W21, #0, 4c4680 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4ca340 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::stop()–	0.03	0.04
▼Loop 2613 - stl_tree.h:269-2459 - exec–	0	0.01
○Loop 2620 - stl_tree.h:778-2115 - exec	0	0
○Loop 2617 - stl_tree.h:778-2115 - exec	0	0
○Loop 2618 - stl_tree.h:778-2115 - exec	0	0
○Loop 2622 - NewTimer.cpp:99-100 - exec	0	0
○Loop 2616 - stl_tree.h:778-2115 - exec	0	0
○Loop 2621 - stl_tree.h:778-2115 - exec	0	0
○Loop 2615 - stl_tree.h:786-1949 - exec	0	0.12
○Loop 2614 - stl_tree.h:778-2115 - exec	0	0
○Loop 2619 - stl_tree.h:786-1949 - exec	0	0.15

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code