OV - exec - Function qmcplusplus::TimerType<std::chrono::_V2::system

	Function: qmcplusplus::TimerType<std::chrono::_V2::system_clock>::start()	Module: exec	Source: NewTimer.cpp:37-81 [...]	Coverage: 0.03%

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 90 - 99

--------------------------------------------------------------------------------

90:     short_buckets[level] = c1;

91:     if (level >= max_level - 1)

92:     {

93:       timer_max_level_exceeded = true;

94:     }

95:     else

96:     {

97:       level++;

98:     }

99:   }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 37 - 81

--------------------------------------------------------------------------------

37: void TimerType<CLOCK>::start()

38: {

39:   if (active)

[...]

53:     for (int level = omp_get_level(); level > 0; level--)

54:       if (omp_get_ancestor_thread_num(level) != 0)

55:         is_true_master = false;

56:     if (is_true_master)

57:     {

58:       if (manager)

59:       {

60:         // compute current_stack_key

61:         TimerType* parent = manager->current_timer();

62:         if (parent)

63:         {

64:           current_stack_key = parent->get_stack_key();

65:           current_stack_key.add_id(timer_id);

66:         }

67:         else

68:         {

69:           current_stack_key = StackKey();

70:           current_stack_key.add_id(timer_id);

71:         }

72:

73:         manager->push_timer(this);

74:       }

75:       start_time = CLOCK::now();

[...]

81: }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h: 92 - 93

--------------------------------------------------------------------------------

92:     if (CurrentTimerStack.size() > 0)

93:       current = CurrentTimerStack.back();

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 993

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

0x4c43c0 STP	X29, X30, [SP, #976]!

0x4c43c4 ADD	X29, SP, #0

0x4c43c8 STP	X19, X20, [SP, #16]

0x4c43cc LDRB	W20, [X0, #56]

0x4c43d0 TBNZ	W20, #0, 4c43e0

0x4c43d4 LDP	X19, X20, [SP, #16]

0x4c43d8 LDP	X29, X30, [SP], #48

0x4c43dc RET

0x4c43e0 STP	X21, X22, [SP, #32]

0x4c43e4 ORR	X22, XZR, X0

0x4c43e8 BL	404080

0x4c43ec ORR	W19, WZR, W0

0x4c43f0 CMP	W0, #0

0x4c43f4 B.LE	4c45a0

0x4c43f8 ANDS	W1, W0, #128

0x4c43fc SUB	W21, W0, #1

0x4c4400 B.EQ	4c44c8

0x4c4404 CMP	W1, #1

0x4c4408 B.EQ	4c44ac

0x4c440c CMP	W1, #2

0x4c4410 B.EQ	4c4494

0x4c4414 CMP	W1, #3

0x4c4418 B.EQ	4c447c

0x4c441c CMP	W1, #4

0x4c4420 B.EQ	4c4464

0x4c4424 CMP	W1, #5

0x4c4428 B.EQ	4c444c

0x4c442c CMP	W1, #6

0x4c4430 B.NE	4c4608

(2611) 0x4c4434 ORR	W0, WZR, W19

(2611) 0x4c4438 SUB	W19, W19, #1

(2611) 0x4c443c BL	403de0

(2611) 0x4c4440 CMP	W0, #0

(2611) 0x4c4444 CCMP	W20, #0, #4, #0

(2611) 0x4c4448 CSINC	W20, WZR, WZR, #0

(2611) 0x4c444c ORR	W0, WZR, W19

(2611) 0x4c4450 SUB	W19, W19, #1

(2611) 0x4c4454 BL	403de0

(2611) 0x4c4458 CMP	W0, #0

(2611) 0x4c445c CCMP	W20, #0, #4, #0

(2611) 0x4c4460 CSINC	W20, WZR, WZR, #0

(2611) 0x4c4464 ORR	W0, WZR, W19

(2611) 0x4c4468 SUB	W19, W19, #1

(2611) 0x4c446c BL	403de0

(2611) 0x4c4470 CMP	W0, #0

(2611) 0x4c4474 CCMP	W20, #0, #4, #0

(2611) 0x4c4478 CSINC	W20, WZR, WZR, #0

(2611) 0x4c447c ORR	W0, WZR, W19

(2611) 0x4c4480 SUB	W19, W19, #1

(2611) 0x4c4484 BL	403de0

(2611) 0x4c4488 CMP	W0, #0

(2611) 0x4c448c CCMP	W20, #0, #4, #0

(2611) 0x4c4490 CSINC	W20, WZR, WZR, #0

(2611) 0x4c4494 ORR	W0, WZR, W19

(2611) 0x4c4498 SUB	W19, W19, #1

(2611) 0x4c449c BL	403de0

(2611) 0x4c44a0 CMP	W0, #0

(2611) 0x4c44a4 CCMP	W20, #0, #4, #0

(2611) 0x4c44a8 CSINC	W20, WZR, WZR, #0

(2611) 0x4c44ac ORR	W0, WZR, W19

(2611) 0x4c44b0 BL	403de0

(2611) 0x4c44b4 CMP	W0, #0

(2611) 0x4c44b8 CCMP	W20, #0, #4, #0

(2611) 0x4c44bc CSINC	W20, WZR, WZR, #0

(2611) 0x4c44c0 SUBS	W19, W19, #1

(2611) 0x4c44c4 B.EQ	4c458c

  (2612) 0x4c44c8 ORR	W0, WZR, W19

  (2612) 0x4c44cc SUB	W21, W19, #1

  (2612) 0x4c44d0 BL	403de0

  (2612) 0x4c44d4 CMP	W0, #0

  (2612) 0x4c44d8 ORR	W0, WZR, W21

  (2612) 0x4c44dc CCMP	W20, #0, #4, #0

  (2612) 0x4c44e0 CSINC	W20, WZR, WZR, #0

  (2612) 0x4c44e4 BL	403de0

  (2612) 0x4c44e8 ORR	W2, WZR, W0

  (2612) 0x4c44ec SUB	W0, W21, #1

  (2612) 0x4c44f0 CMP	W2, #0

  (2612) 0x4c44f4 CCMP	W20, #0, #4, #0

  (2612) 0x4c44f8 CSINC	W21, WZR, WZR, #0

  (2612) 0x4c44fc BL	403de0

  (2612) 0x4c4500 ORR	W3, WZR, W0

  (2612) 0x4c4504 SUB	W0, W19, #3

  (2612) 0x4c4508 CMP	W3, #0

  (2612) 0x4c450c CCMP	W21, #0, #4, #0

  (2612) 0x4c4510 CSINC	W20, WZR, WZR, #0

  (2612) 0x4c4514 BL	403de0

  (2612) 0x4c4518 ORR	W4, WZR, W0

  (2612) 0x4c451c SUB	W0, W19, #4

  (2612) 0x4c4520 CMP	W4, #0

  (2612) 0x4c4524 CCMP	W20, #0, #4, #0

  (2612) 0x4c4528 CSINC	W21, WZR, WZR, #0

  (2612) 0x4c452c BL	403de0

  (2612) 0x4c4530 ORR	W5, WZR, W0

  (2612) 0x4c4534 SUB	W0, W19, #5

  (2612) 0x4c4538 CMP	W5, #0

  (2612) 0x4c453c CCMP	W21, #0, #4, #0

  (2612) 0x4c4540 CSINC	W20, WZR, WZR, #0

  (2612) 0x4c4544 BL	403de0

  (2612) 0x4c4548 ORR	W6, WZR, W0

  (2612) 0x4c454c SUB	W0, W19, #6

  (2612) 0x4c4550 CMP	W6, #0

  (2612) 0x4c4554 CCMP	W20, #0, #4, #0

  (2612) 0x4c4558 CSINC	W21, WZR, WZR, #0

  (2612) 0x4c455c BL	403de0

  (2612) 0x4c4560 ORR	W7, WZR, W0

  (2612) 0x4c4564 SUB	W0, W19, #7

  (2612) 0x4c4568 CMP	W7, #0

  (2612) 0x4c456c CCMP	W21, #0, #4, #0

  (2612) 0x4c4570 CSINC	W20, WZR, WZR, #0

  (2612) 0x4c4574 BL	403de0

  (2612) 0x4c4578 CMP	W0, #0

  (2612) 0x4c457c CCMP	W20, #0, #4, #0

  (2612) 0x4c4580 CSINC	W20, WZR, WZR, #0

  (2612) 0x4c4584 SUBS	W19, W19, #8

  (2612) 0x4c4588 B.NE	4c44c8

(2611) 0x4c458c TBNZ	W20, #0, 4c45a0

(2611) 0x4c4590 LDP	X21, X22, [SP, #32]

(2611) 0x4c4594 LDP	X19, X20, [SP, #16]

(2611) 0x4c4598 LDP	X29, X30, [SP], #48

(2611) 0x4c459c RET

(2611) 0x4c45a0 LDR	X0, [X22, #72]

(2611) 0x4c45a4 CBZ	X0, 4c45f0

(2611) 0x4c45a8 LDP	X8, X9, [X0, #72]

(2611) 0x4c45ac LDRB	W10, [X22, #64]

(2611) 0x4c45b0 CMP	X8, X9

(2611) 0x4c45b4 B.EQ	4c4630

(2611) 0x4c45b8 LDUR	X11, [X9, #504]

(2611) 0x4c45bc CBZ	X11, 4c4630

(2611) 0x4c45c0 LDP	X14, X15, [X11, #80]

(2611) 0x4c45c4 ADD	X13, X22, #80

(2611) 0x4c45c8 LDR	W16, [X11, #96]

(2611) 0x4c45cc STP	X14, X15, [X22, #80]

(2611) 0x4c45d0 STR	W16, [X13, #16]

(2611) 0x4c45d4 STRB	W10, [X13, X16,SXTW]

(2611) 0x4c45d8 CMP	W16, #14

(2611) 0x4c45dc B.GT	4c4620

(2611) 0x4c45e0 ADD	W15, W16, #1

(2611) 0x4c45e4 STR	W15, [X13, #16]

(2611) 0x4c45e8 ORR	X1, XZR, X22

(2611) 0x4c45ec BL	4ca120

(2611) 0x4c45f0 BL	403e30

(2611) 0x4c45f4 STR	X0, [X22]

(2611) 0x4c45f8 LDP	X21, X22, [SP, #32]

(2611) 0x4c45fc LDP	X19, X20, [SP, #16]

(2611) 0x4c4600 LDP	X29, X30, [SP], #48

(2611) 0x4c4604 RET

(2611) 0x4c4608 BL	403de0

(2611) 0x4c460c CMP	W0, #0

(2611) 0x4c4610 ORR	W19, WZR, W21

(2611) 0x4c4614 CCMP	W20, #0, #4, #0

(2611) 0x4c4618 CSINC	W20, WZR, WZR, #0

(2611) 0x4c461c B	4c4434

(2611) 0x4c4620 ADRP	X17,

(2611) 0x4c4624 MOVZ	W18, #1

(2611) 0x4c4628 STRB	W18, [X17, #1896]

(2611) 0x4c462c B	4c45e8

(2611) 0x4c4630 MOVZ	W12, #1

(2611) 0x4c4634 STP	XZR, XZR, [X22, #80]

(2611) 0x4c4638 STRB	W10, [X22, #80]

(2611) 0x4c463c STR	W12, [X22, #96]

(2611) 0x4c4640 B	4c45e8

0x4c4644 HINT	#0

0x4c4648 HINT	#0

0x4c464c HINT	#0

0x4c4650 HINT	#0

0x4c4654 HINT	#0

0x4c4658 HINT	#0

0x4c465c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:37-81
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:90-99
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:37-39,53-75,81
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.50 to 0.69 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 33 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	5.50	5.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.63
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

6% of peak load performance is reached (6.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c43c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W20, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ W20, #0, 4c43e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404080 <@plt_start@+0x690>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4c45a0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W1, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W21, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 4c44c8 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c44ac <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c4494 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c447c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c4464 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c444c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4c4608 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	NewTimer.cpp:37-81
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:90-99
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:37-39,53-75,81
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 33 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	5.50	5.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.63
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

6% of peak load performance is reached (6.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c43c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W20, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ W20, #0, 4c43e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404080 <@plt_start@+0x690>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4c45a0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W1, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W21, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 4c44c8 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c44ac <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c4494 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c447c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c4464 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4c444c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4c4608 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::start()–	0.03	0.05
▼Loop 2611 - NewTimer.cpp:53-81 - exec–	0	0.01
○Loop 2612 - NewTimer.cpp:53-54 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code