OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::ParticleAttrib<double, std::allocator<double> >&, bool)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalua ...	Module: exec	Source: DiracDeterminantRef.cpp:152-181 [...]	Coverage: 0.54%

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 110 - 131

--------------------------------------------------------------------------------

110:     for (unsigned d = 0; d < D; ++d)

[...]

129:     Type_t res = lhs[0] * rhs[0];

130:     for (unsigned d = 1; d < D; ++d)

131:       res += lhs[d] * rhs[d];

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 106 - 111

--------------------------------------------------------------------------------

106:     for (int iat = first, i = 0; iat < last; ++iat, ++i)

107:     {

108:       ValueVector_t v(logdet[i], OrbitalSetSize);

109:       GradVector_t g(dlogdet[i], OrbitalSetSize);

110:       ValueVector_t l(d2logdet[i], OrbitalSetSize);

111:       evaluate(P, iat, v, g, l);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 156

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

156:     res += a[i] * b[i];

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 152 - 181

--------------------------------------------------------------------------------

152: void DiracDeterminantRef<DU_TYPE>::evaluateGL(ParticleSet& P,

153:                                               ParticleSet::ParticleGradient& G,

154:                                               ParticleSet::ParticleLaplacian& L,

155:                                               bool fromscratch)

156: {

157:   if (UpdateMode == ORB_PBYP_RATIO)

158:   { //need to compute dpsiM and d2psiM. Do not touch psiM!

159:     SPOVGLTimer->start();

160:     Phi->evaluate_notranspose(P, FirstIndex, LastIndex, psiM_temp, dpsiM, d2psiM);

161:     SPOVGLTimer->stop();

162:   }

163:

164:   if (NumPtcls == 1)

165:   {

166:     ValueType y = psiM(0, 0);

167:     GradType rv = y * dpsiM(0, 0);

168:     G[FirstIndex] += rv;

169:     L[FirstIndex] += y * d2psiM(0, 0) - dot(rv, rv);

170:   }

171:   else

172:   {

173:     for (size_t i = 0, iat = FirstIndex; i < NumPtcls; ++i, ++iat)

174:     {

175:       mValueType dot_temp = simd::dot(psiM[i], d2psiM[i], NumOrbitals);

176:       mGradType rv        = simd::dot(psiM[i], dpsiM[i], NumOrbitals);

177:       G[iat] += rv;

178:       L[iat] += dot_temp - dot(rv, rv);

179:     }

180:   }

181: }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 56 - 248

--------------------------------------------------------------------------------

56:   explicit inline Vector(T* ref, size_t n) : nLocal(n), X(ref) {}

[...]

144:   virtual ~Vector() { free(); }

[...]

210:     if (nAllocated)

[...]

221:   inline Type_t& operator[](size_t i)

222:   {

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 61 - 94

--------------------------------------------------------------------------------

61:   inline typename BinaryReturn<T1, T2, OpMultiply>::Type_t operator()(const T1& a, const T2& b) const

62:   {

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h: 104 - 172

--------------------------------------------------------------------------------

104:       ~__new_allocator() _GLIBCXX_USE_NOEXCEPT { }

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

0x467880 STP	X29, X30, [SP, #752]!

0x467884 ADD	X29, SP, #0

0x467888 ORR	X9, XZR, X0

0x46788c LDR	W0, [X0, #12]

0x467890 STR	X1, [SP, #96]

0x467894 STP	X2, X3, [SP, #120]

0x467898 CBZ	W0, 467cd4

(1378) 0x46789c LDR	W14, [X9, #1156]

(1378) 0x4678a0 LDR	W18, [X9, #1144]

(1378) 0x4678a4 CMP	W14, #1

(1378) 0x4678a8 B.EQ	467c4c

0x4678ac STP	X23, X24, [SP, #48]

0x4678b0 SBFM	X23, X14, #0, #31

0x4678b4 CBZ	W14, 467ebc

0x4678b8 CNTW	X6, ALL

0x4678bc MOVZ	W30, #24

0x4678c0 PTRUE	P7.B, ALL

0x4678c4 LDP	X0, X1, [SP, #120]

0x4678c8 MOVZ	X17, #0

0x4678cc MOVZ	X16, #0

0x4678d0 MOVZ	X10, #0

0x4678d4 CNTD	X7, ALL

0x4678d8 CNTB	X4, ALL, MUL #2

0x4678dc STP	X19, X20, [SP, #16]

0x4678e0 STP	X21, X22, [SP, #32]

0x4678e4 STP	X25, X26, [SP, #64]

0x4678e8 ADD	W26, W6, #3

0x4678ec STP	X27, X28, [SP, #80]

0x4678f0 MOVZ	W27, #96

0x4678f4 LDR	X20, [X9, #216]

0x4678f8 LDR	X25, [X9, #256]

0x4678fc LDR	X19, [X9, #344]

0x467900 UBFM	X22, X20, #61, #60

0x467904 LDR	X24, [X9, #384]

0x467908 LDR	W14, [X9, #1152]

0x46790c UBFM	X21, X19, #61, #60

0x467910 LDR	X2, [X0, #24]

0x467914 ORR	X0, XZR, X25

0x467918 ORR	X15, XZR, X24

0x46791c LDR	X3, [X1, #24]

0x467920 UBFM	W11, W14, #2, #31

0x467924 AND	W12, W14, #64

0x467928 AND	W13, W14, #1886

0x46792c SUB	W28, W14, #1

0x467930 SUB	W5, W14, W6

0x467934 SMADDL	X8, W18, W30, X2

0x467938 ADD	X18, X3, W18,SXTW #3

0x46793c STR	W11, [SP, #96]

0x467940 STR	W12, [SP, #104]

0x467944 STR	W13, [SP, #112]

    (1381) 0x467948 CMP	W14, #0

    (1381) 0x46794c B.LE	467c18

    (1381) 0x467950 MOVZ	W30, #0

    (1381) 0x467954 CMP	W28, W26

    (1381) 0x467958 B.CC	467c34

    (1381) 0x46795c ORR	X2, XZR, X15

    (1381) 0x467960 ORR	X1, XZR, X0

    (1381) 0x467964 DUP	Z3.D, #0

    (1381) 0x467968 ORR	Z1.D, Z3.D, Z3.D

      (1383) 0x46796c ADD	W30, W30, W6

      (1383) 0x467970 LD1D	{Z2.D}, P7/Z, [X1, #1, MUL VL]

      (1383) 0x467974 LD1D	{Z22.D}, P7/Z, [X2, #1, MUL VL]

      (1383) 0x467978 LD1D	{Z21.D}, P7/Z, [X1, MUL VL]

      (1383) 0x46797c LD1D	{Z20.D}, P7/Z, [X2, MUL VL]

      (1383) 0x467980 ADD	X1, X1, X4

      (1383) 0x467984 ADD	X2, X2, X4

      (1383) 0x467988 FMLA	Z3.D, P7/M, Z2.D, Z22.D

      (1383) 0x46798c FMLA	Z1.D, P7/M, Z21.D, Z20.D

      (1383) 0x467990 CMP	W5, W30

      (1383) 0x467994 B.CS	46796c

    (1381) 0x467998 FADD	Z0.D, Z1.D, Z3.D

    (1381) 0x46799c CMP	W14, W30

    (1381) 0x4679a0 B.EQ	4679dc

    (1381) 0x4679a4 ORR	W3, WZR, W30

    (1381) 0x4679a8 SUB	W12, W14, W30

    (1381) 0x4679ac WHILELO	P6.D, WZR, W12

    (1381) 0x4679b0 ADD	X11, X16, X3

    (1381) 0x4679b4 ADD	X13, X17, X3

    (1381) 0x4679b8 ADD	X30, X25, X11,LSL #3

    (1381) 0x4679bc MOVZ	X1, #0

    (1381) 0x4679c0 ADD	X2, X24, X13,LSL #3

      (1380) 0x4679c4 LD1D	{Z19.D}, P6/Z, [X30, X1,LSL #3]

      (1380) 0x4679c8 LD1D	{Z18.D}, P6/Z, [X2, X1,LSL #3]

      (1380) 0x4679cc ADD	X1, X1, X7

      (1380) 0x4679d0 FMLA	Z0.D, P6/M, Z19.D, Z18.D

      (1380) 0x4679d4 WHILELO	P6.D, W1, W12

      (1380) 0x4679d8 B.NE	4679c4

    (1381) 0x4679dc LDR	X3, [X9, #280]

    (1381) 0x4679e0 FADDV	D27, P7, Z0.D

    (1381) 0x4679e4 LDR	X13, [X9, #320]

    (1381) 0x4679e8 MADD	X11, X10, X3, XZR

    (1381) 0x4679ec CMP	W28, #2

    (1381) 0x4679f0 B.LS	467c3c

    (1381) 0x4679f4 LDR	W30, [SP, #96]

    (1381) 0x4679f8 ADD	X12, X11, X11,LSL #1

    (1381) 0x4679fc MOVI	V17.2D, #0

    (1381) 0x467a00 ORR	X3, XZR, X0

    (1381) 0x467a04 UBFM	X2, X12, #61, #60

    (1381) 0x467a08 ADD	X1, X13, X2

    (1381) 0x467a0c ORR	V16.16B, V17.16B, V17.16B

    (1381) 0x467a10 ORR	V7.16B, V17.16B, V17.16B

    (1381) 0x467a14 UMADDL	X12, W30, W27, X1

    (1381) 0x467a18 ORR	V6.16B, V17.16B, V17.16B

    (1381) 0x467a1c ORR	V5.16B, V17.16B, V17.16B

    (1381) 0x467a20 ORR	V4.16B, V17.16B, V17.16B

    (1381) 0x467a24 SUB	X30, X12, X1

    (1381) 0x467a28 TBZ	W30, #5, 467a68

    (1381) 0x467a2c LDP	Q25, Q23, [X0]

    (1381) 0x467a30 ADD	X3, X0, #32

    (1381) 0x467a34 LDP	Q31, Q30, [X1, #16]

    (1381) 0x467a38 LDP	Q29, Q28, [X1, #48]

    (1381) 0x467a3c ADD	X1, X1, #96

    (1381) 0x467a40 LDUR	Q26, [X1, #496]

    (1381) 0x467a44 LDR	Q24, [X13, X2]

    (1381) 0x467a48 FMLA	V5.2D, V31.2D, V25.2D

    (1381) 0x467a4c FMLA	V4.2D, V24.2D, V25.D[0]

    (1381) 0x467a50 FMLA	V6.2D, V30.2D, V25.D[1]

    (1381) 0x467a54 FMLA	V7.2D, V29.2D, V23.D[0]

    (1381) 0x467a58 FMLA	V16.2D, V28.2D, V23.2D

    (1381) 0x467a5c FMLA	V17.2D, V26.2D, V23.D[1]

    (1381) 0x467a60 CMP	X12, X1

    (1381) 0x467a64 B.EQ	467ad8

      (1382) 0x467a68 ORR	X2, XZR, X1

      (1382) 0x467a6c LDP	Q1, Q20, [X3]

      (1382) 0x467a70 ORR	X30, XZR, X3

      (1382) 0x467a74 ADD	X3, X3, #64

      (1382) 0x467a78 LDR	Q21, [X2], #96

      (1382) 0x467a7c LDP	Q0, Q22, [X1, #16]

      (1382) 0x467a80 LDP	Q3, Q2, [X1, #48]

      (1382) 0x467a84 LDP	Q19, Q18, [X1, #80]

      (1382) 0x467a88 ADD	X1, X1, #192

      (1382) 0x467a8c FMLA	V4.2D, V21.2D, V1.D[0]

      (1382) 0x467a90 LDP	Q23, Q31, [X2, #16]

      (1382) 0x467a94 LDP	Q30, Q24, [X2, #48]

      (1382) 0x467a98 FMLA	V5.2D, V0.2D, V1.2D

      (1382) 0x467a9c LDUR	Q25, [X3, #480]

      (1382) 0x467aa0 LDR	Q28, [X30, #48]

      (1382) 0x467aa4 FMLA	V6.2D, V22.2D, V1.D[1]

      (1382) 0x467aa8 LDR	Q29, [X2, #80]

      (1382) 0x467aac FMLA	V7.2D, V3.2D, V20.D[0]

      (1382) 0x467ab0 FMLA	V16.2D, V2.2D, V20.2D

      (1382) 0x467ab4 FMLA	V17.2D, V19.2D, V20.D[1]

      (1382) 0x467ab8 FMLA	V4.2D, V18.2D, V25.D[0]

      (1382) 0x467abc FMLA	V5.2D, V23.2D, V25.2D

      (1382) 0x467ac0 FMLA	V6.2D, V31.2D, V25.D[1]

      (1382) 0x467ac4 FMLA	V7.2D, V30.2D, V28.D[0]

      (1382) 0x467ac8 FMLA	V16.2D, V24.2D, V28.2D

      (1382) 0x467acc FMLA	V17.2D, V29.2D, V28.D[1]

      (1382) 0x467ad0 CMP	X12, X1

      (1382) 0x467ad4 B.NE	467a68

    (1381) 0x467ad8 EXT	V26.16B, V16.16B, V17.16B, #8

    (1381) 0x467adc LDR	W12, [SP, #104]

    (1381) 0x467ae0 EXT	V20.16B, V5.16B, V6.16B, #8

    (1381) 0x467ae4 MOV	D17, V17.D[1]

    (1381) 0x467ae8 MOV	D6, V6.D[1]

    (1381) 0x467aec FADD	V4.2D, V7.2D, V4.2D

    (1381) 0x467af0 FADD	D5, D5, D16

    (1381) 0x467af4 FADD	V7.2D, V26.2D, V20.2D

    (1381) 0x467af8 FADD	D16, D17, D6

    (1381) 0x467afc FADD	V31.2D, V7.2D, V4.2D

    (1381) 0x467b00 FADD	D26, D5, D16

    (1381) 0x467b04 CBZ	W12, 467b9c

    (1381) 0x467b08 LDR	W30, [SP, #112]

    (1381) 0x467b0c ADD	X3, X11, W30,SXTW

    (1381) 0x467b10 ADD	X1, X3, X3,LSL #1

    (1381) 0x467b14 ORR	W2, WZR, W30

    (1381) 0x467b18 UBFM	X3, X2, #61, #60

    (1381) 0x467b1c ADD	W2, W30, #1

    (1381) 0x467b20 UBFM	X1, X1, #61, #60

    (1381) 0x467b24 ADD	X12, X13, X1

    (1381) 0x467b28 LDR	D1, [X0, X3]

    (1381) 0x467b2c LDR	Q0, [X13, X1]

    (1381) 0x467b30 LDR	D22, [X12, #16]

    (1381) 0x467b34 FMLA	V31.2D, V0.2D, V1.D[0]

    (1381) 0x467b38 FMADD	D26, D22, D1, D26

    (1381) 0x467b3c CMP	W14, W2

    (1381) 0x467b40 B.LE	467b9c

    (1381) 0x467b44 ADD	X1, X11, W2,SXTW

    (1381) 0x467b48 ADD	X12, X1, X1,LSL #1

    (1381) 0x467b4c ADD	X3, X0, X3

    (1381) 0x467b50 ADD	W30, W30, #2

    (1381) 0x467b54 UBFM	X2, X12, #61, #60

    (1381) 0x467b58 LDR	D2, [X3, #8]

    (1381) 0x467b5c ADD	X1, X13, X2

    (1381) 0x467b60 LDR	Q3, [X13, X2]

    (1381) 0x467b64 LDR	D21, [X1, #16]

    (1381) 0x467b68 FMLA	V31.2D, V3.2D, V2.D[0]

    (1381) 0x467b6c FMADD	D26, D2, D21, D26

    (1381) 0x467b70 CMP	W14, W30

    (1381) 0x467b74 B.LE	467b9c

    (1381) 0x467b78 ADD	X11, X11, W30,SXTW

    (1381) 0x467b7c ADD	X12, X11, X11,LSL #1

    (1381) 0x467b80 LDR	D23, [X3, #16]

    (1381) 0x467b84 UBFM	X30, X12, #61, #60

    (1381) 0x467b88 ADD	X2, X13, X30

    (1381) 0x467b8c LDR	Q19, [X13, X30]

    (1381) 0x467b90 LDR	D18, [X2, #16]

    (1381) 0x467b94 FMLA	V31.2D, V19.2D, V23.D[0]

    (1381) 0x467b98 FMADD	D26, D18, D23, D26

    (1381) 0x467b9c MOV	D24, V31.D[1]

    (1381) 0x467ba0 FMUL	D28, D26, D26

    (1381) 0x467ba4 FMUL	D30, D31, D31

    (1381) 0x467ba8 FMUL	D29, D24, D24

    (1381) 0x467bac LDR	D25, [X8, #16]

    (1381) 0x467bb0 FADD	D30, D29, D30

    (1381) 0x467bb4 ADD	X0, X0, X22

    (1381) 0x467bb8 ADD	X15, X15, X21

    (1381) 0x467bbc ADD	X16, X16, X20

    (1381) 0x467bc0 LDR	Q29, [X8]

    (1381) 0x467bc4 ADD	X17, X17, X19

    (1381) 0x467bc8 ADD	X8, X8, #24

    (1381) 0x467bcc FADD	D26, D25, D26

    (1381) 0x467bd0 FADD	V31.2D, V29.2D, V31.2D

    (1381) 0x467bd4 STUR	D26, [X8, #504]

    (1381) 0x467bd8 STUR	Q31, [X8, #488]

    (1381) 0x467bdc LDR	D20, [X18, X10,LSL #3]

    (1381) 0x467be0 FADD	D27, D27, D20

    (1381) 0x467be4 FSUB	D28, D27, S28

    (1381) 0x467be8 FSUB	D17, D28, S30

    (1381) 0x467bec STR	D17, [X18, X10,LSL #3]

    (1381) 0x467bf0 ADD	X10, X10, #1

    (1381) 0x467bf4 CMP	X23, X10

    (1381) 0x467bf8 B.NE	467948

(1384) 0x467bfc LDP	X19, X20, [SP, #16]

(1384) 0x467c00 LDP	X21, X22, [SP, #32]

(1384) 0x467c04 LDP	X23, X24, [SP, #48]

(1384) 0x467c08 LDP	X25, X26, [SP, #64]

(1384) 0x467c0c LDP	X27, X28, [SP, #80]

(1384) 0x467c10 LDP	X29, X30, [SP], #272

(1384) 0x467c14 RET

  (1379) 0x467c18 MOVI	V31.2D, #0

  (1379) 0x467c1c FMOV	D30, D31

  (1379) 0x467c20 FMOV	D29, D31

  (1379) 0x467c24 FMOV	D28, D31

  (1379) 0x467c28 FMOV	D27, D31

  (1379) 0x467c2c FMOV	D26, D31

  (1379) 0x467c30 B	467bac

    (1381) 0x467c34 DUP	Z0.D, #0

    (1381) 0x467c38 B	4679a4

    (1381) 0x467c3c MOVI	V31.2D, #0

    (1381) 0x467c40 MOVZ	W30, #0

    (1381) 0x467c44 FMOV	D26, D31

    (1381) 0x467c48 B	467b0c

(1378) 0x467c4c MOVZ	W6, #24

(1378) 0x467c50 LDR	X5, [X9, #256]

(1378) 0x467c54 SBFM	X7, X18, #61, #31

(1378) 0x467c58 LDP	X4, X13, [SP, #120]

(1378) 0x467c5c SMADDL	X14, W18, W6, XZR

(1378) 0x467c60 LDR	X18, [X9, #320]

(1378) 0x467c64 LDR	D7, [X5]

(1378) 0x467c68 LDR	X11, [X4, #24]

(1378) 0x467c6c LDP	D6, D4, [X18]

(1378) 0x467c70 LDR	D5, [X18, #16]

(1378) 0x467c74 ADD	X3, X11, X14

(1378) 0x467c78 LDR	X1, [X13, #24]

(1378) 0x467c7c FMUL	D16, D7, D6

(1378) 0x467c80 FMUL	D1, D7, D4

(1378) 0x467c84 LDR	X9, [X9, #384]

(1378) 0x467c88 FMUL	D22, D7, D5

(1378) 0x467c8c STP	D16, D1, [SP, #224]

(1378) 0x467c90 FMUL	D0, D1, D1

(1378) 0x467c94 LDR	Q3, [X11, X14]

(1378) 0x467c98 LDR	Q21, [SP, #224]

(1378) 0x467c9c FMADD	D2, D16, D16, D0

(1378) 0x467ca0 FADD	V19.2D, V3.2D, V21.2D

(1378) 0x467ca4 STR	Q19, [X11, X14]

(1378) 0x467ca8 LDR	D18, [X3, #16]

(1378) 0x467cac FADD	D23, D18, D22

(1378) 0x467cb0 STR	D23, [X3, #16]

(1378) 0x467cb4 LDR	D24, [X1, X7]

(1378) 0x467cb8 LDR	D30, [X9]

(1378) 0x467cbc FMADD	D29, D7, D30, D24

(1378) 0x467cc0 FMSUB	D25, D22, D22, D29

(1378) 0x467cc4 FSUB	D31, D25, S2

(1378) 0x467cc8 STR	D31, [X1, X7]

(1378) 0x467ccc LDP	X29, X30, [SP], #272

(1378) 0x467cd0 RET

(1378) 0x467cd4 STP	X21, X22, [SP, #32]

(1378) 0x467cd8 LDR	X0, [X9, #1128]

(1378) 0x467cdc STR	X9, [SP, #104]

(1378) 0x467ce0 BL	4c43c0

(1378) 0x467ce4 LDR	X9, [SP, #104]

(1378) 0x467ce8 ADRP	X1,

(1378) 0x467cec ADD	X4, X1, #1760

(1378) 0x467cf0 LDR	X21, [X9, #1136]

(1378) 0x467cf4 LDR	W2, [X9, #1144]

(1378) 0x467cf8 LDR	W3, [X9, #1148]

(1378) 0x467cfc LDR	X5, [X21]

(1378) 0x467d00 STR	W2, [SP, #104]

(1378) 0x467d04 LDR	X7, [X5, #40]

(1378) 0x467d08 CMP	X7, X4

(1378) 0x467d0c B.NE	467e94

(1378) 0x467d10 CMP	W2, W3

(1378) 0x467d14 B.GE	467e30

(1378) 0x467d18 STP	X19, X20, [SP, #16]

(1378) 0x467d1c ADRP	X19,

(1378) 0x467d20 ADRP	X20,

(1378) 0x467d24 SUB	W3, W3, W2

(1378) 0x467d28 MOVZ	X22, #0

(1378) 0x467d2c ADD	X19, X19, #1288

(1378) 0x467d30 ADD	X20, X20, #3000

(1378) 0x467d34 STP	X23, X24, [SP, #48]

(1378) 0x467d38 ADD	X24, X9, #360

(1378) 0x467d3c ADD	X23, X9, #336

(1378) 0x467d40 STP	X25, X26, [SP, #64]

(1378) 0x467d44 ADD	X26, X9, #296

(1378) 0x467d48 ADD	X25, X9, #272

(1378) 0x467d4c STP	X27, X28, [SP, #80]

(1378) 0x467d50 ADD	X28, X9, #168

(1378) 0x467d54 ADD	X27, X9, #144

(1378) 0x467d58 STR	X3, [SP, #112]

(1378) 0x467d5c STR	X9, [SP, #136]

  (1385) 0x467d60 LDR	X13, [X25, #8]

  (1385) 0x467d64 ADD	X5, SP, #224

  (1385) 0x467d68 ADD	X4, SP, #184

  (1385) 0x467d6c STR	X19, [SP, #144]

  (1385) 0x467d70 ADD	X3, SP, #144

  (1385) 0x467d74 LDR	X8, [X23, #8]

  (1385) 0x467d78 STR	X20, [SP, #184]

  (1385) 0x467d7c LDR	X30, [X27, #8]

  (1385) 0x467d80 MADD	X14, X22, X13, XZR

  (1385) 0x467d84 LDR	X1, [X28, #24]

  (1385) 0x467d88 MADD	X11, X22, X8, XZR

  (1385) 0x467d8c LDR	X10, [X24, #24]

  (1385) 0x467d90 ADD	X15, X14, X14,LSL #1

  (1385) 0x467d94 MADD	X0, X22, X30, XZR

  (1385) 0x467d98 LDR	X16, [X26, #24]

  (1385) 0x467d9c LDRSW	X18, [X21, #8]

  (1385) 0x467da0 ADD	X7, X1, X0,LSL #3

  (1385) 0x467da4 ORR	X0, XZR, X21

  (1385) 0x467da8 STR	X19, [SP, #224]

  (1385) 0x467dac ADD	X12, X10, X11,LSL #3

  (1385) 0x467db0 LDR	X9, [X21]

  (1385) 0x467db4 ADD	X17, X16, X15,LSL #3

  (1385) 0x467db8 STR	XZR, [SP, #160]

  (1385) 0x467dbc LDR	W6, [SP, #104]

  (1385) 0x467dc0 STR	X18, [SP, #152]

  (1385) 0x467dc4 LDR	X1, [SP, #96]

  (1385) 0x467dc8 STR	X7, [SP, #168]

  (1385) 0x467dcc STP	X18, XZR, [SP, #192]

  (1385) 0x467dd0 ADD	W2, W6, W22

  (1385) 0x467dd4 LDR	X6, [X9, #24]

  (1385) 0x467dd8 STR	X17, [SP, #208]

  (1385) 0x467ddc STP	X18, XZR, [SP, #232]

  (1385) 0x467de0 STR	X12, [SP, #248]

  (1385) 0x467de4 BLR	X6

  (1385) 0x467de8 LDR	X3, [SP, #240]

  (1385) 0x467dec STR	X19, [SP, #224]

  (1385) 0x467df0 CBNZ	X3, 467e84

  (1385) 0x467df4 LDR	X8, [SP, #200]

  (1385) 0x467df8 STR	X20, [SP, #184]

  (1385) 0x467dfc CBNZ	X8, 467e48

  (1385) 0x467e00 LDR	X10, [SP, #160]

  (1385) 0x467e04 STR	X19, [SP, #144]

  (1385) 0x467e08 CBNZ	X10, 467e64

  (1385) 0x467e0c LDR	X12, [SP, #112]

  (1385) 0x467e10 ADD	X22, X22, #1

  (1385) 0x467e14 CMP	X22, X12

  (1385) 0x467e18 B.NE	467d60

(1378) 0x467e1c LDR	X9, [SP, #136]

(1378) 0x467e20 LDP	X19, X20, [SP, #16]

(1378) 0x467e24 LDP	X23, X24, [SP, #48]

(1378) 0x467e28 LDP	X25, X26, [SP, #64]

(1378) 0x467e2c LDP	X27, X28, [SP, #80]

(1378) 0x467e30 STR	X9, [SP, #96]

(1378) 0x467e34 LDR	X0, [X9, #1128]

(1378) 0x467e38 BL	4c4660

(1378) 0x467e3c LDR	X9, [SP, #96]

(1378) 0x467e40 LDP	X21, X22, [SP, #32]

(1378) 0x467e44 B	46789c

  (1385) 0x467e48 ADD	X11, X8, X8,LSL #1

  (1385) 0x467e4c LDR	X0, [SP, #208]

  (1385) 0x467e50 UBFM	X1, X11, #61, #60

  (1385) 0x467e54 BL	403d70

  (1385) 0x467e58 LDR	X10, [SP, #160]

  (1385) 0x467e5c STR	X19, [SP, #144]

  (1385) 0x467e60 CBZ	X10, 467e0c

  (1385) 0x467e64 LDR	X0, [SP, #168]

  (1385) 0x467e68 UBFM	X1, X10, #61, #60

  (1385) 0x467e6c ADD	X22, X22, #1

  (1385) 0x467e70 BL	403d70

  (1385) 0x467e74 LDR	X13, [SP, #112]

  (1385) 0x467e78 CMP	X13, X22

  (1385) 0x467e7c B.NE	467d60

(1378) 0x467e80 B	467e1c

  (1385) 0x467e84 LDR	X0, [SP, #248]

  (1385) 0x467e88 UBFM	X1, X3, #61, #60

  (1385) 0x467e8c BL	403d70

  (1385) 0x467e90 B	467df4

(1378) 0x467e94 LDR	X1, [SP, #96]

(1378) 0x467e98 ADD	X6, X9, #336

(1378) 0x467e9c ADD	X5, X9, #272

(1378) 0x467ea0 ADD	X4, X9, #144

(1378) 0x467ea4 ORR	X0, XZR, X21

(1378) 0x467ea8 STR	X9, [SP, #96]

(1378) 0x467eac LDR	W2, [SP, #104]

(1378) 0x467eb0 BLR	X7

(1378) 0x467eb4 LDR	X9, [SP, #96]

(1378) 0x467eb8 B	467e30

0x467ebc LDP	X23, X24, [SP, #48]

0x467ec0 B	467c10

0x467ec4 LDR	X4, [SP, #240]

0x467ec8 ORR	X22, XZR, X0

0x467ecc STR	X19, [SP, #224]

0x467ed0 CBZ	X4, 467ee0

0x467ed4 LDR	X0, [SP, #248]

0x467ed8 UBFM	X1, X4, #61, #60

0x467edc BL	403d70

0x467ee0 LDR	X21, [SP, #200]

0x467ee4 STR	X20, [SP, #184]

0x467ee8 CBZ	X21, 467efc

0x467eec MOVZ	X2, #24

0x467ef0 LDR	X0, [SP, #208]

0x467ef4 MADD	X1, X21, X2, XZR

0x467ef8 BL	403d70

0x467efc LDR	X5, [SP, #160]

0x467f00 STR	X19, [SP, #144]

0x467f04 CBZ	X5, 467f14

0x467f08 LDR	X0, [SP, #168]

0x467f0c UBFM	X1, X5, #61, #60

0x467f10 BL	403d70

0x467f14 ORR	X0, XZR, X22

0x467f18 BL	403e10

0x467f1c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	DiracDeterminantRef.cpp:152-181
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:110,129-131
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:106-111
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:152-181
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:56,144,210,221-223,248
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h:104,172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 2.50 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.00 to 2.00 cycles (5.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	71
loop length	284
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	10.00	10.00	10.00	7.00	7.00
cycles	5.00	5.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	10.00	10.00	10.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.75
Overall L1	10.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.00 cycles. At this rate:

14% of peak load performance is reached (13.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 467880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ W0, 467cd4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X23, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ W14, 467ebc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x63c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTW X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W30, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X0, X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTB X4, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W27, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [X9, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X9, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X9, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X22, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X9, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [X9, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X21, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM W11, W14, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W12, W14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W14, #1886	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W28, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMADDL X8, W18, W30, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X18, X3, W18,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR W11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 467c10 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X4, 467ee0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x660>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d70 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X21, 467efc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x67c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X1, X21, X2, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403d70 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X5, 467f14 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d70 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	DiracDeterminantRef.cpp:152-181
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:110,129-131
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:106-111
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:152-181
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:56,144,210,221-223,248
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/new_allocator.h:104,172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 2.50 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.00 to 2.00 cycles (5.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	71
loop length	284
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	10.00	10.00	10.00	7.00	7.00
cycles	5.00	5.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	10.00	10.00	10.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.75
Overall L1	10.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.00 cycles. At this rate:

14% of peak load performance is reached (13.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 467880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ W0, 467cd4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X23, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ W14, 467ebc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x63c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTW X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W30, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X0, X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTB X4, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W27, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [X9, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X9, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X9, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X22, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X9, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [X9, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X21, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM W11, W14, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W12, W14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W14, #1886	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W28, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMADDL X8, W18, W30, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X18, X3, W18,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR W11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 467c10 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X4, 467ee0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x660>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d70 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X21, 467efc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x67c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X1, X21, X2, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403d70 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X5, 467f14 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d70 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus:...–	0.54	0.9
▼Loop 1378 - DiracDeterminantRef.cpp:159-181 - exec–	0	0
○Loop 1385 - SPOSet.h:106-111 - exec	0	0
▼Loop 1384 - DiracDeterminantRef.cpp:173-181 - exec–	0	0
▼Loop 1379 - OperatorTags.h:61-94 - exec–	0	0
▼Loop 1381 - DiracDeterminantRef.cpp:173-178 - exec–	0	0.01
○Loop 1382 - inner_product.hpp:155-155 - exec	0.35	0.49
○Loop 1383 - inner_product.hpp:82-83 - exec	0.19	0.27
○Loop 1380 - inner_product.hpp:82-83 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code