OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector<double, 3u>&)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratioG ...	Module: exec	Source: DiracDeterminantRef.cpp:94-118 [...]	Coverage: 0.12%

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h: 193 - 193

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193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 98 - 113

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98:     if (delay_count == 0)

99:     {

100:       // Ainv is fresh, directly access Ainv

101:       std::copy_n(Ainv[rowchanged], invRow.size(), invRow.data());

102:       return;

103:     }

104:     const T cone(1);

105:     const T czero(0);

106:     const int norb     = Ainv.rows();

107:     const int lda_Binv = Binv.cols();

108:     // save Ainv[rowchanged] to invRow

109:     std::copy_n(Ainv[rowchanged], norb, invRow.data());

110:     // multiply V (NxK) Binv(KxK) U(KxN) invRow right to the left

111:     BLAS::gemv('T', norb, delay_count, cone, U.data(), norb, invRow.data(), 1, czero, p.data(), 1);

112:     BLAS::gemv('N', delay_count, delay_count, cone, Binv.data(), lda_Binv, p.data(), 1, czero, Binv[delay_count], 1);

113:     BLAS::gemv('N', norb, delay_count, -cone, V.data(), norb, Binv[delay_count], 1, cone, invRow.data(), 1);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 77 - 217

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77:   inline size_type rows() const { return D1; }

78:   inline size_type cols() const { return D2; }

[...]

214:   inline const Type_t* operator[](size_type i) const { return X.data() + i * D2; }

215:

216:   /// returns a pointer of i-th row, g++ iterator problem

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 156

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

156:     res += a[i] * b[i];

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 94 - 118

--------------------------------------------------------------------------------

94: typename DiracDeterminantRef<DU_TYPE>::ValueType DiracDeterminantRef<DU_TYPE>::ratioGrad(ParticleSet& P,

95:                                                                                          int iat,

96:                                                                                          GradType& grad_iat)

97: {

98:   SPOVGLTimer->start();

99:   Phi->evaluate(P, iat, psiV, dpsiV, d2psiV);

100:   SPOVGLTimer->stop();

101:   RatioTimer->start();

102:   const int WorkingIndex = iat - FirstIndex;

103:   UpdateMode             = ORB_PBYP_PARTIAL;

[...]

109:   if (invRow_id != WorkingIndex)

110:   {

111:     invRow_id = WorkingIndex;

112:     updateEng.getInvRow(psiM, WorkingIndex, invRow);

113:   }

114:   curRatio = simd::dot(invRow.data(), psiV.data(), invRow.size());

115:   grad_iat += ((RealType)1.0 / curRatio) * simd::dot(invRow.data(), dpsiV.data(), invRow.size());

116:   RatioTimer->stop();

117:   return curRatio;

118: }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 248

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 61 - 94

--------------------------------------------------------------------------------

61:   inline typename BinaryReturn<T1, T2, OpMultiply>::Type_t operator()(const T1& a, const T2& b) const

62:   {

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 413 - 453

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     dgemv(trans_in, n, m, alpha, amat, lda, x, incx, beta, y, incy);

0x465f60 SUB	SP, SP, #224

0x465f64 STP	X29, X30, [SP, #32]

0x465f68 ADD	X29, SP, #32

0x465f6c STP	X19, X20, [SP, #48]

0x465f70 ORR	X19, XZR, X0

0x465f74 ADD	X20, X0, #440

0x465f78 STP	X21, X22, [SP, #64]

0x465f7c ORR	W22, WZR, W2

0x465f80 ORR	X21, XZR, X3

0x465f84 STP	X23, X24, [SP, #80]

0x465f88 ADD	X24, X0, #400

0x465f8c ORR	X23, XZR, X1

0x465f90 LDR	X0, [X0, #1128]

0x465f94 BL	4c43c0

0x465f98 LDR	X0, [X19, #1136]

0x465f9c ORR	X1, XZR, X23

0x465fa0 ADD	X5, X19, #480

0x465fa4 ORR	W2, WZR, W22

0x465fa8 ORR	X4, XZR, X20

0x465fac ORR	X3, XZR, X24

0x465fb0 LDR	X6, [X0]

0x465fb4 LDR	X7, [X6, #24]

0x465fb8 BLR	X7

0x465fbc LDR	X0, [X19, #1128]

0x465fc0 BL	4c4660

0x465fc4 LDR	X0, [X19, #1096]

0x465fc8 BL	4c43c0

0x465fcc LDR	W0, [X19, #1144]

0x465fd0 MOVZ	W2, #2

0x465fd4 LDR	W1, [X19, #1072]

0x465fd8 STR	W2, [X19, #12]

0x465fdc SUB	W5, W22, W0

0x465fe0 CMP	W1, W5

0x465fe4 B.NE	4662a4

0x465fe8 LDR	X5, [X19, #1040]

0x465fec LDR	X0, [X19, #1056]

(1365) 0x465ff0 ORR	W17, WZR, W5

(1365) 0x465ff4 LDR	X30, [X24, #24]

(1365) 0x465ff8 CMP	W5, #0

(1365) 0x465ffc B.LE	46649c

(1365) 0x466000 CNTW	X24, ALL

(1365) 0x466004 SUB	W7, W5, #1

(1365) 0x466008 ADD	W1, W24, #3

(1365) 0x46600c ORR	W16, WZR, W5

(1365) 0x466010 MOVZ	W2, #0

(1365) 0x466014 CMP	W7, W1

(1365) 0x466018 B.CC	4664b0

(1365) 0x46601c SUB	W3, W5, W24

(1365) 0x466020 ORR	X9, XZR, X0

(1365) 0x466024 DUP	Z28.D, #0

(1365) 0x466028 ORR	X11, XZR, X30

(1365) 0x46602c CNTB	X8, ALL, MUL #2

(1365) 0x466030 PTRUE	P7.B, ALL

(1365) 0x466034 ORR	Z3.D, Z28.D, Z28.D

(1365) 0x466038 HINT	#0

(1365) 0x46603c HINT	#0

  (1368) 0x466040 ADD	W2, W2, W24

  (1368) 0x466044 LD1D	{Z2.D}, P7/Z, [X9, #1, MUL VL]

  (1368) 0x466048 LD1D	{Z4.D}, P7/Z, [X11, #1, MUL VL]

  (1368) 0x46604c LD1D	{Z7.D}, P7/Z, [X9, MUL VL]

  (1368) 0x466050 LD1D	{Z6.D}, P7/Z, [X11, MUL VL]

  (1368) 0x466054 ADD	X9, X9, X8

  (1368) 0x466058 ADD	X11, X11, X8

  (1368) 0x46605c FMLA	Z28.D, P7/M, Z2.D, Z4.D

  (1368) 0x466060 FMLA	Z3.D, P7/M, Z7.D, Z6.D

  (1368) 0x466064 CMP	W3, W2

  (1368) 0x466068 B.CS	466040

(1365) 0x46606c FADD	Z5.D, Z3.D, Z28.D

(1365) 0x466070 CMP	W16, W2

(1365) 0x466074 B.EQ	4660b8

(1365) 0x466078 UBFM	X12, X2, #61, #31

(1365) 0x46607c MOVZ	X6, #0

(1365) 0x466080 CNTD	X13, ALL

(1365) 0x466084 ADD	X14, X30, X12

(1365) 0x466088 ADD	X15, X0, X12

(1365) 0x46608c SUB	W18, W16, W2

(1365) 0x466090 WHILELO	P0.D, WZR, W18

(1365) 0x466094 HINT	#0

(1365) 0x466098 HINT	#0

(1365) 0x46609c HINT	#0

  (1366) 0x4660a0 LD1D	{Z16.D}, P0/Z, [X15, X6,LSL #3]

  (1366) 0x4660a4 LD1D	{Z29.D}, P0/Z, [X14, X6,LSL #3]

  (1366) 0x4660a8 ADD	X6, X6, X13

  (1366) 0x4660ac FMLA	Z5.D, P0/M, Z16.D, Z29.D

  (1366) 0x4660b0 WHILELO	P0.D, W6, W18

  (1366) 0x4660b4 B.NE	4660a0

(1365) 0x4660b8 FMOV	D22, #1.0000000

(1365) 0x4660bc PTRUE	P1.B, ALL

(1365) 0x4660c0 FADDV	D17, P1, Z5.D

(1365) 0x4660c4 LDR	X20, [X20, #24]

(1365) 0x4660c8 STR	D17, [X19, #1080]

(1365) 0x4660cc FDIV	D22, D22, D17

(1365) 0x4660d0 DUP	V21.2D, V22.D[0]

(1365) 0x4660d4 CMP	W7, #2

(1365) 0x4660d8 B.LS	4664b8

(1365) 0x4660dc UBFM	W22, W16, #2, #31

(1365) 0x4660e0 MOVZ	W10, #96

(1365) 0x4660e4 MOVI	V20.2D, #0

(1365) 0x4660e8 ORR	X24, XZR, X20

(1365) 0x4660ec ORR	X4, XZR, X0

(1365) 0x4660f0 UMADDL	X5, W22, W10, X20

(1365) 0x4660f4 ORR	V19.16B, V20.16B, V20.16B

(1365) 0x4660f8 ORR	V18.16B, V20.16B, V20.16B

(1365) 0x4660fc SUB	X30, X5, X20

(1365) 0x466100 ORR	V17.16B, V20.16B, V20.16B

(1365) 0x466104 ORR	V0.16B, V20.16B, V20.16B

(1365) 0x466108 ORR	V16.16B, V20.16B, V20.16B

(1365) 0x46610c TBZ	W30, #5, 466148

(1365) 0x466110 LDP	Q23, Q1, [X0]

(1365) 0x466114 ADD	X4, X0, #32

(1365) 0x466118 LDP	Q27, Q26, [X20, #16]

(1365) 0x46611c LDP	Q25, Q24, [X20, #48]

(1365) 0x466120 LDR	Q5, [X20, #80]

(1365) 0x466124 LDR	Q31, [X24], #96

(1365) 0x466128 FMLA	V0.2D, V27.2D, V23.2D

(1365) 0x46612c FMLA	V17.2D, V26.2D, V23.D[1]

(1365) 0x466130 FMLA	V18.2D, V25.2D, V1.D[0]

(1365) 0x466134 FMLA	V19.2D, V1.2D, V24.2D

(1365) 0x466138 FMLA	V16.2D, V31.2D, V23.D[0]

(1365) 0x46613c FMLA	V20.2D, V5.2D, V1.D[1]

(1365) 0x466140 CMP	X24, X5

(1365) 0x466144 B.EQ	4661b0

  (1367) 0x466148 ORR	X7, XZR, X24

  (1367) 0x46614c LDP	Q28, Q3, [X4]

  (1367) 0x466150 LDR	Q29, [X7], #96

  (1367) 0x466154 LDP	Q2, Q4, [X24, #16]

  (1367) 0x466158 LDP	Q7, Q6, [X24, #48]

  (1367) 0x46615c LDP	Q30, Q23, [X24, #80]

  (1367) 0x466160 ADD	X24, X24, #192

  (1367) 0x466164 FMLA	V16.2D, V29.2D, V28.D[0]

  (1367) 0x466168 LDP	Q31, Q5, [X4, #32]

  (1367) 0x46616c ADD	X4, X4, #64

  (1367) 0x466170 LDP	Q1, Q27, [X7, #16]

  (1367) 0x466174 FMLA	V0.2D, V2.2D, V28.2D

  (1367) 0x466178 LDP	Q26, Q25, [X7, #48]

  (1367) 0x46617c LDR	Q24, [X7, #80]

  (1367) 0x466180 FMLA	V17.2D, V4.2D, V28.D[1]

  (1367) 0x466184 FMLA	V18.2D, V7.2D, V3.D[0]

  (1367) 0x466188 FMLA	V19.2D, V3.2D, V6.2D

  (1367) 0x46618c FMLA	V20.2D, V30.2D, V3.D[1]

  (1367) 0x466190 FMLA	V16.2D, V23.2D, V31.D[0]

  (1367) 0x466194 FMLA	V0.2D, V1.2D, V31.2D

  (1367) 0x466198 FMLA	V17.2D, V27.2D, V31.D[1]

  (1367) 0x46619c FMLA	V18.2D, V26.2D, V5.D[0]

  (1367) 0x4661a0 FMLA	V19.2D, V5.2D, V25.2D

  (1367) 0x4661a4 FMLA	V20.2D, V24.2D, V5.D[1]

  (1367) 0x4661a8 CMP	X24, X5

  (1367) 0x4661ac B.NE	466148

(1365) 0x4661b0 EXT	V28.16B, V0.16B, V17.16B, #8

(1365) 0x4661b4 EXT	V3.16B, V19.16B, V20.16B, #8

(1365) 0x4661b8 MOV	D17, V17.D[1]

(1365) 0x4661bc MOV	D20, V20.D[1]

(1365) 0x4661c0 FADD	V16.2D, V16.2D, V18.2D

(1365) 0x4661c4 FADD	D0, D19, D0

(1365) 0x4661c8 FADD	V18.2D, V28.2D, V3.2D

(1365) 0x4661cc FADD	D19, D17, D20

(1365) 0x4661d0 FADD	V30.2D, V18.2D, V16.2D

(1365) 0x4661d4 FADD	D25, D0, D19

(1365) 0x4661d8 ANDS	XZR, X16, #4160

(1365) 0x4661dc B.EQ	466260

(1365) 0x4661e0 AND	W23, W16, #1886

(1365) 0x4661e4 MOVZ	W1, #24

(1365) 0x4661e8 ORR	W16, WZR, W23

(1365) 0x4661ec UBFM	X8, X16, #61, #60

(1365) 0x4661f0 ADD	W3, W23, #1

(1365) 0x4661f4 UMADDL	X11, W23, W1, XZR

(1365) 0x4661f8 LDR	D2, [X0, X8]

(1365) 0x4661fc ADD	X2, X20, X11

(1365) 0x466200 LDR	Q4, [X20, X11]

(1365) 0x466204 LDR	D7, [X2, #16]

(1365) 0x466208 FMLA	V30.2D, V4.2D, V2.D[0]

(1365) 0x46620c FMADD	D25, D7, D2, D25

(1365) 0x466210 CMP	W17, W3

(1365) 0x466214 B.LE	466260

(1365) 0x466218 ADD	X9, X11, #24

(1365) 0x46621c ADD	X12, X0, X8

(1365) 0x466220 ADD	X13, X20, X9

(1365) 0x466224 ADD	W14, W23, #2

(1365) 0x466228 LDR	Q6, [X20, X9]

(1365) 0x46622c LDR	D29, [X12, #8]

(1365) 0x466230 LDR	D23, [X13, #16]

(1365) 0x466234 FMLA	V30.2D, V6.2D, V29.D[0]

(1365) 0x466238 FMADD	D25, D29, D23, D25

(1365) 0x46623c CMP	W17, W14

(1365) 0x466240 B.LE	466260

(1365) 0x466244 ADD	X17, X11, #48

(1365) 0x466248 LDR	D26, [X12, #16]

(1365) 0x46624c ADD	X15, X20, X17

(1365) 0x466250 LDR	Q27, [X20, X17]

(1365) 0x466254 LDR	D1, [X15, #16]

(1365) 0x466258 FMLA	V30.2D, V27.2D, V26.D[0]

(1365) 0x46625c FMADD	D25, D26, D1, D25

(1365) 0x466260 FMUL	D22, D22, D25

(1365) 0x466264 FMUL	V21.2D, V21.2D, V30.2D

(1365) 0x466268 LDR	Q30, [X21]

(1365) 0x46626c LDR	D24, [X21, #16]

(1365) 0x466270 LDR	X0, [X19, #1096]

(1365) 0x466274 FADD	V31.2D, V30.2D, V21.2D

(1365) 0x466278 FADD	D5, D24, D22

(1365) 0x46627c STR	Q31, [X21]

(1365) 0x466280 STR	D5, [X21, #16]

(1365) 0x466284 BL	4c4660

(1365) 0x466288 LDR	D0, [X19, #1080]

(1365) 0x46628c LDP	X29, X30, [SP, #32]

(1365) 0x466290 LDP	X21, X22, [SP, #64]

(1365) 0x466294 LDP	X23, X24, [SP, #80]

(1365) 0x466298 LDP	X19, X20, [SP, #48]

(1365) 0x46629c ADD	SP, SP, #224

(1365) 0x4662a0 RET

(1365) 0x4662a4 STP	X27, X28, [SP, #112]

(1365) 0x4662a8 SBFM	X3, X5, #0, #31

(1365) 0x4662ac ADD	X28, X19, #520

(1365) 0x4662b0 LDR	X8, [X19, #216]

(1365) 0x4662b4 STR	W5, [X19, #1072]

(1365) 0x4662b8 LDR	X4, [X19, #256]

(1365) 0x4662bc LDR	W12, [X28, #360]

(1365) 0x4662c0 MADD	X9, X3, X8, XZR

(1365) 0x4662c4 UBFM	X10, X9, #61, #60

(1365) 0x4662c8 ADD	X1, X4, X10

(1365) 0x4662cc CBZ	W12, 46646c

(1365) 0x4662d0 STP	X25, X26, [SP, #96]

(1365) 0x4662d4 ADD	X27, X19, #1032

(1365) 0x4662d8 ADD	X25, X19, #648

(1365) 0x4662dc LDR	X11, [X25, #8]

(1365) 0x4662e0 LDR	X23, [X19, #208]

(1365) 0x4662e4 LDR	X6, [X27, #24]

(1365) 0x4662e8 STR	D15, [SP, #128]

(1365) 0x4662ec STR	X11, [SP, #144]

(1365) 0x4662f0 CMP	W23, #0

(1365) 0x4662f4 B.LE	466314

(1365) 0x4662f8 UBFM	X2, X23, #61, #31

(1365) 0x4662fc CMP	X2, #8

(1365) 0x466300 B.EQ	4664c8

(1365) 0x466304 ORR	X0, XZR, X6

(1365) 0x466308 BL	403a40

(1365) 0x46630c LDR	X6, [X27, #24]

(1365) 0x466310 LDR	W12, [X28, #360]

(1365) 0x466314 FMOV	D15, #1.0000000

(1365) 0x466318 MOVZ	W22, #1

(1365) 0x46631c ADD	X26, SP, #204

(1365) 0x466320 LDR	X16, [X19, #840]

(1365) 0x466324 ADD	X14, SP, #216

(1365) 0x466328 MOVZ	W15, #84

(1365) 0x46632c ADD	X13, X19, #816

(1365) 0x466330 ADD	X7, SP, #200

(1365) 0x466334 STR	X26, [SP, #16]

(1365) 0x466338 ADD	X5, SP, #196

(1365) 0x46633c ADD	X3, SP, #208

(1365) 0x466340 STP	W23, W12, [SP, #188]

(1365) 0x466344 ADD	X2, SP, #192

(1365) 0x466348 ADD	X0, SP, #187

(1365) 0x46634c STP	W23, W22, [SP, #196]

(1365) 0x466350 LDR	X4, [X19, #568]

(1365) 0x466354 ADD	X1, SP, #188

(1365) 0x466358 STP	X14, X16, [SP]

(1365) 0x46635c STR	X13, [SP, #168]

(1365) 0x466360 STRB	W15, [SP, #187]

(1365) 0x466364 STR	W22, [SP, #204]

(1365) 0x466368 STR	D15, [SP, #208]

(1365) 0x46636c STR	XZR, [SP, #216]

(1365) 0x466370 BL	403cf0

(1365) 0x466374 LDR	W10, [X28, #360]

(1365) 0x466378 ADD	X4, SP, #216

(1365) 0x46637c MOVZ	W6, #78

(1365) 0x466380 STP	W22, W22, [SP, #200]

(1365) 0x466384 ADD	X18, X19, #672

(1365) 0x466388 ADD	X7, SP, #200

(1365) 0x46638c STR	X4, [SP]

(1365) 0x466390 ADD	X5, SP, #196

(1365) 0x466394 ADD	X3, SP, #208

(1365) 0x466398 LDR	X9, [SP, #168]

(1365) 0x46639c ADD	X2, SP, #192

(1365) 0x4663a0 ADD	X1, SP, #188

(1365) 0x4663a4 ADD	X0, SP, #187

(1365) 0x4663a8 STR	W6, [SP, #156]

(1365) 0x4663ac STP	W10, W10, [SP, #188]

(1365) 0x4663b0 SBFM	X8, X10, #0, #31

(1365) 0x4663b4 LDR	X11, [X25, #8]

(1365) 0x4663b8 STR	X26, [SP, #16]

(1365) 0x4663bc LDR	X4, [X19, #696]

(1365) 0x4663c0 STRB	W6, [SP, #187]

(1365) 0x4663c4 LDR	W13, [SP, #144]

(1365) 0x4663c8 MADD	X12, X8, X11, XZR

(1365) 0x4663cc STR	X18, [SP, #160]

(1365) 0x4663d0 LDR	X6, [X9, #24]

(1365) 0x4663d4 STR	D15, [SP, #208]

(1365) 0x4663d8 ADD	X14, X4, X12,LSL #3

(1365) 0x4663dc STR	XZR, [SP, #216]

(1365) 0x4663e0 STR	W13, [SP, #196]

(1365) 0x4663e4 STR	X14, [SP, #8]

(1365) 0x4663e8 BL	403cf0

(1365) 0x4663ec LDR	W28, [X28, #360]

(1365) 0x4663f0 FMOV	D0, #-1.0000000

(1365) 0x4663f4 ADD	X15, SP, #216

(1365) 0x4663f8 STP	W23, W22, [SP, #196]

(1365) 0x4663fc ADD	X5, SP, #196

(1365) 0x466400 ADD	X0, SP, #187

(1365) 0x466404 LDR	X4, [SP, #160]

(1365) 0x466408 ADD	X7, SP, #200

(1365) 0x46640c ADD	X3, SP, #208

(1365) 0x466410 STR	X15, [SP]

(1365) 0x466414 ADD	X2, SP, #192

(1365) 0x466418 ADD	X1, SP, #188

(1365) 0x46641c STP	D0, D15, [SP, #208]

(1365) 0x466420 STP	W23, W28, [SP, #188]

(1365) 0x466424 SBFM	X18, X28, #0, #31

(1365) 0x466428 LDR	X25, [X25, #8]

(1365) 0x46642c STR	W22, [SP, #204]

(1365) 0x466430 LDR	X23, [X4, #24]

(1365) 0x466434 LDR	X10, [X27, #24]

(1365) 0x466438 MADD	X22, X18, X25, XZR

(1365) 0x46643c LDR	W6, [SP, #156]

(1365) 0x466440 STP	X10, X26, [SP, #8]

(1365) 0x466444 LDR	X4, [X19, #632]

(1365) 0x466448 STRB	W6, [SP, #187]

(1365) 0x46644c ADD	X6, X23, X22,LSL #3

(1365) 0x466450 BL	403cf0

(1365) 0x466454 LDR	X5, [X27, #8]

(1365) 0x466458 LDP	X25, X26, [SP, #96]

(1365) 0x46645c LDR	X0, [X27, #24]

(1365) 0x466460 LDP	X27, X28, [SP, #112]

(1365) 0x466464 LDR	D15, [SP, #128]

(1365) 0x466468 B	465ff0

(1365) 0x46646c LDR	X5, [X19, #1040]

(1365) 0x466470 CBZ	X5, 466498

(1365) 0x466474 UBFM	X2, X5, #61, #60

(1365) 0x466478 LDR	X0, [X19, #1056]

(1365) 0x46647c CMP	X2, #8

(1365) 0x466480 B.LE	4664d4

(1365) 0x466484 BL	403a40

(1365) 0x466488 LDR	X5, [X19, #1040]

(1365) 0x46648c LDP	X27, X28, [SP, #112]

(1365) 0x466490 LDR	X0, [X19, #1056]

(1365) 0x466494 B	465ff0

(1365) 0x466498 LDP	X27, X28, [SP, #112]

(1365) 0x46649c ADRP	X18,

(1365) 0x4664a0 STR	XZR, [X19, #1080]

(1365) 0x4664a4 LDR	Q21, [X18, #416]

(1365) 0x4664a8 FMOV	D22, D21

(1365) 0x4664ac B	466268

(1365) 0x4664b0 DUP	Z5.D, #0

(1365) 0x4664b4 B	466078

(1365) 0x4664b8 MOVI	V30.2D, #0

(1365) 0x4664bc MOVZ	W23, #0

(1365) 0x4664c0 FMOV	D25, D30

(1365) 0x4664c4 B	4661e4

(1365) 0x4664c8 LDR	D31, [X4, X10]

(1365) 0x4664cc STR	D31, [X6]

(1365) 0x4664d0 B	466314

(1365) 0x4664d4 B.EQ	4664e0

(1365) 0x4664d8 LDP	X27, X28, [SP, #112]

(1365) 0x4664dc B	465ff0

(1365) 0x4664e0 LDR	D1, [X4, X10]

(1365) 0x4664e4 STR	D1, [X0]

(1365) 0x4664e8 LDP	X27, X28, [SP, #112]

(1365) 0x4664ec B	465ff0

0x4664f0 HINT	#0

0x4664f4 HINT	#0

0x4664f8 HINT	#0

0x4664fc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	DiracDeterminantRef.cpp:94-118
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:94-103,109-118
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.17 to 0.84 cycles (6.12x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.00 cycles (2.58x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50
cycles	2.50	2.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

14% of peak load performance is reached (13.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 465f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X0, #440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W22, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X24, X0, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X19, #480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W0, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W2, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W5, W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W1, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4662a4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	DiracDeterminantRef.cpp:94-118
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:94-103,109-118
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.00 cycles (2.58x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50
cycles	2.50	2.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

14% of peak load performance is reached (13.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 465f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X0, #440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W22, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X24, X0, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X19, #480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W0, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W2, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W5, W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W1, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4662a4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)–	0.12	0.19
▼Loop 1365 - OhmmsVector.h:178-248 - exec–	0	0.01
○Loop 1368 - inner_product.hpp:82-83 - exec	0.07	0.1
○Loop 1367 - inner_product.hpp:155-155 - exec	0.04	0.05
○Loop 1366 - inner_product.hpp:82-83 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code