OV - exec - Function qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSet&)

	Function: qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSe ...	Module: exec	Source: SoaDistanceTableABOMPTarget.h:61-233 [...]	Coverage: 5.22%

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h: 193 - 193

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193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

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242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp: 46 - 46

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46:   return ((n + ND - 1) / ND) * ND;

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

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280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp: 78 - 79

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78:     free(p);

79:   }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp: 38 - 38

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38:   return a < b ? a : b;

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 154 - 267

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154:     nAllocated = 0;

[...]

167:     if (nAllocated)

[...]

174:     nLocal  = n;

175:     nGhosts = n_padded;

176:     myData  = ptr;

[...]

267:   inline const T* data() const { return myData; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 149 - 248

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149:     if (nAllocated)

[...]

156:     nLocal     = n;

157:     nAllocated = 0;

[...]

221:   inline Type_t& operator[](size_t i)

222:   {

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 1131

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993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 61 - 233

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61:     if (num_sources_ * num_targets_ == 0)

62:       return;

63:     if (distances_.size())

64:       return;

65:

66:     // initialize memory containers and views

67:     const size_t num_padded  = getAlignedSize<T>(num_sources_);

68:     const size_t stride_size = getPerTargetPctlStrideSize();

69:     r_dr_memorypool_.resize(stride_size * num_targets_);

70:

71:     distances_.resize(num_targets_);

72:     displacements_.resize(num_targets_);

73:     for (int i = 0; i < num_targets_; ++i)

74:     {

75:       distances_[i].attachReference(r_dr_memorypool_.data() + i * stride_size, num_sources_);

76:       displacements_[i].attachReference(num_sources_, num_padded,

77:                                         r_dr_memorypool_.data() + i * stride_size + num_padded);

[...]

180:   size_t getPerTargetPctlStrideSize() const override { return getAlignedSize<T>(num_sources_) * (D + 1); }

181:

182:   /** evaluate the full table */

183:   inline void evaluate(ParticleSet& P) override

184:   {

185:     resize();

186:

187:     ScopedTimer local_timer(evaluate_timer_);

188:     // be aware of the sign of Displacement

189:     const int num_targets_local = num_targets_;

190:     const int num_sources_local = num_sources_;

191:     const int num_padded        = getAlignedSize<T>(num_sources_);

192:

193:     target_pos.resize(num_targets_ * D);

194:     for (size_t iat = 0; iat < num_targets_; iat++)

195:       for (size_t idim = 0; idim < D; idim++)

196:         target_pos[iat * D + idim] = P.R[iat][idim];

197:

198:     auto* target_pos_ptr = target_pos.data();

199:     auto* source_pos_ptr = origin_.getCoordinates().getAllParticlePos().data();

[...]

205:     const size_t num_teams     = (num_sources_ + ChunkSizePerTeam - 1) / ChunkSizePerTeam;

206:     const size_t stride_size   = getPerTargetPctlStrideSize();

207:

208:     {

209:       ScopedTimer offload(offload_timer_);

210:       PRAGMA_OFFLOAD("omp target teams distribute collapse(2) num_teams(num_targets_*num_teams) \

211:                         map(to: source_pos_ptr[:num_padded*D]) \

212:                         map(always, to: target_pos_ptr[:num_targets_*D]) \

213:                         map(always, from: r_dr_ptr[:num_targets_*stride_size])")

214:       for (int iat = 0; iat < num_targets_local; ++iat)

215:         for (int team_id = 0; team_id < num_teams; team_id++)

216:         {

217:           const int first = ChunkSizePerTeam * team_id;

218:           const int last  = omptarget::min(first + ChunkSizePerTeam, num_sources_local);

219:

220:           T pos[D];

221:           for (int idim = 0; idim < D; idim++)

222:             pos[idim] = target_pos_ptr[iat * D + idim];

223:

224:           auto* r_iat_ptr  = r_dr_ptr + iat * stride_size;

225:           auto* dr_iat_ptr = r_iat_ptr + num_padded;

226:

227:           PRAGMA_OFFLOAD("omp parallel for")

228:           for (int iel = first; iel < last; iel++)

229:             DTD_BConds<T, D, SC>::computeDistancesOffload(pos, source_pos_ptr, num_padded, r_iat_ptr, dr_iat_ptr,

230:                                                           num_padded, iel);

231:         }

232:     }

233:   }

0x529020 STP	X29, X30, [SP, #880]!

0x529024 ADD	X29, SP, #0

0x529028 STP	X19, X20, [SP, #16]

0x52902c STP	X21, X22, [SP, #32]

0x529030 ORR	X22, XZR, X0

0x529034 STP	X23, X24, [SP, #48]

0x529038 STP	X25, X26, [SP, #64]

0x52903c STP	X27, X28, [SP, #80]

0x529040 STP	D14, D15, [SP, #96]

0x529044 STR	X1, [SP, #112]

0x529048 LDP	X2, X1, [X0, #16]

0x52904c MADD	X3, X2, X1, XZR

0x529050 CBZ	X3, 529068

0x529054 LDR	X4, [X0, #72]

0x529058 ADD	X21, X0, #72

0x52905c LDR	X5, [X21, #8]

0x529060 CMP	X5, X4

0x529064 B.EQ	529500

(4208) 0x529068 LDR	X20, [X22, #440]

(4208) 0x52906c ADD	X21, X22, #384

(4208) 0x529070 ORR	X0, XZR, X20

(4208) 0x529074 BL	4c43c0

(4208) 0x529078 LDP	X23, X26, [X22, #16]

(4208) 0x52907c MOVI	D0, #0

(4208) 0x529080 ORR	X0, XZR, X21

(4208) 0x529084 ADD	X7, X23, #3

(4208) 0x529088 ADD	X1, X26, X26,LSL #1

(4208) 0x52908c AND	X27, X7, #8062

(4208) 0x529090 BL	504b00

(4208) 0x529094 LDR	X24, [X22, #24]

(4208) 0x529098 LDR	X25, [X21, #24]

(4208) 0x52909c CBZ	X24, 5292d4

(4208) 0x5290a0 LDR	X8, [SP, #112]

(4208) 0x5290a4 LDR	X0, [X8, #64]

(4208) 0x5290a8 CMP	X24, #1

(4208) 0x5290ac B.EQ	529690

(4208) 0x5290b0 ADD	X9, X0, #47

(4208) 0x5290b4 SUB	X10, X9, X25

(4208) 0x5290b8 CMP	X10, #94

(4208) 0x5290bc B.LS	529690

(4208) 0x5290c0 UBFM	X1, X24, #1, #63

(4208) 0x5290c4 ORR	X11, XZR, #3841

(4208) 0x5290c8 ADD	X12, X1, X1,LSL #1

(4208) 0x5290cc MOVK	X11, #43691

(4208) 0x5290d0 ORR	X30, XZR, X25

(4208) 0x5290d4 MOVK	X11, #2730

(4208) 0x5290d8 ORR	X28, XZR, X0

(4208) 0x5290dc ADD	X18, X25, X12,LSL #4

(4208) 0x5290e0 SUB	X13, X18, X25

(4208) 0x5290e4 SUB	X14, X13, #48

(4208) 0x5290e8 UBFM	X15, X14, #4, #63

(4208) 0x5290ec MADD	X16, X15, X11, XZR

(4208) 0x5290f0 ADD	X19, X16, #1

(4208) 0x5290f4 ANDS	X17, X19, #4224

(4208) 0x5290f8 B.EQ	5291dc

(4208) 0x5290fc CMP	X17, #1

(4208) 0x529100 B.EQ	5291bc

(4208) 0x529104 CMP	X17, #2

(4208) 0x529108 B.EQ	5291a4

(4208) 0x52910c CMP	X17, #3

(4208) 0x529110 B.EQ	52918c

(4208) 0x529114 CMP	X17, #4

(4208) 0x529118 B.EQ	529174

(4208) 0x52911c CMP	X17, #5

(4208) 0x529120 B.EQ	52915c

(4208) 0x529124 CMP	X17, #6

(4208) 0x529128 B.EQ	529144

(4208) 0x52912c LDP	Q30, Q29, [X0]

(4208) 0x529130 ADD	X30, X25, #48

(4208) 0x529134 ADD	X28, X0, #48

(4208) 0x529138 LDR	Q31, [X0, #32]

(4208) 0x52913c STR	Q31, [X25, #32]

(4208) 0x529140 STP	Q30, Q29, [X25]

(4208) 0x529144 LDP	Q0, Q1, [X28]

(4208) 0x529148 ADD	X30, X30, #48

(4208) 0x52914c ADD	X28, X28, #48

(4208) 0x529150 LDUR	Q2, [X28, #496]

(4208) 0x529154 STUR	Q2, [X30, #496]

(4208) 0x529158 STP	Q0, Q1, [X30, #2000]

(4208) 0x52915c LDP	Q3, Q4, [X28]

(4208) 0x529160 ADD	X30, X30, #48

(4208) 0x529164 ADD	X28, X28, #48

(4208) 0x529168 LDUR	Q5, [X28, #496]

(4208) 0x52916c STUR	Q5, [X30, #496]

(4208) 0x529170 STP	Q3, Q4, [X30, #2000]

(4208) 0x529174 LDP	Q6, Q7, [X28]

(4208) 0x529178 ADD	X30, X30, #48

(4208) 0x52917c ADD	X28, X28, #48

(4208) 0x529180 LDUR	Q14, [X28, #496]

(4208) 0x529184 STUR	Q14, [X30, #496]

(4208) 0x529188 STP	Q6, Q7, [X30, #2000]

(4208) 0x52918c LDP	Q16, Q17, [X28]

(4208) 0x529190 ADD	X30, X30, #48

(4208) 0x529194 ADD	X28, X28, #48

(4208) 0x529198 LDUR	Q18, [X28, #496]

(4208) 0x52919c STUR	Q18, [X30, #496]

(4208) 0x5291a0 STP	Q16, Q17, [X30, #2000]

(4208) 0x5291a4 LDP	Q19, Q20, [X28]

(4208) 0x5291a8 ADD	X30, X30, #48

(4208) 0x5291ac ADD	X28, X28, #48

(4208) 0x5291b0 LDUR	Q21, [X28, #496]

(4208) 0x5291b4 STUR	Q21, [X30, #496]

(4208) 0x5291b8 STP	Q19, Q20, [X30, #2000]

(4208) 0x5291bc LDP	Q22, Q23, [X28]

(4208) 0x5291c0 ADD	X30, X30, #48

(4208) 0x5291c4 ADD	X28, X28, #48

(4208) 0x5291c8 LDUR	Q24, [X28, #496]

(4208) 0x5291cc STUR	Q24, [X30, #496]

(4208) 0x5291d0 STP	Q22, Q23, [X30, #2000]

(4208) 0x5291d4 CMP	X30, X18

(4208) 0x5291d8 B.EQ	5292a4

  (4216) 0x5291dc LDP	Q25, Q26, [X28]

  (4216) 0x5291e0 ADD	X3, X28, #48

  (4216) 0x5291e4 ADD	X5, X30, #48

  (4216) 0x5291e8 ADD	X2, X28, #96

  (4216) 0x5291ec ADD	X21, X30, #96

  (4216) 0x5291f0 LDR	Q27, [X28, #32]

  (4216) 0x5291f4 ADD	X9, X28, #144

  (4216) 0x5291f8 ADD	X1, X30, #144

  (4216) 0x5291fc ADD	X8, X28, #192

  (4216) 0x529200 ADD	X13, X30, #192

  (4216) 0x529204 ADD	X7, X28, #240

  (4216) 0x529208 ADD	X12, X30, #240

  (4216) 0x52920c ADD	X6, X28, #288

  (4216) 0x529210 ADD	X11, X30, #288

  (4216) 0x529214 ADD	X4, X28, #336

  (4216) 0x529218 ADD	X10, X30, #336

  (4216) 0x52921c STR	Q27, [X30, #32]

  (4216) 0x529220 STP	Q25, Q26, [X30]

  (4216) 0x529224 LDP	Q28, Q15, [X3, #16]

  (4216) 0x529228 LDR	Q30, [X28, #48]

  (4216) 0x52922c STR	Q30, [X30, #48]

  (4216) 0x529230 STP	Q28, Q15, [X5, #16]

  (4216) 0x529234 LDP	Q31, Q0, [X2, #16]

  (4216) 0x529238 LDR	Q29, [X28, #96]

  (4216) 0x52923c ADD	X28, X28, #384

  (4216) 0x529240 STR	Q29, [X30, #96]

  (4216) 0x529244 ADD	X30, X30, #384

  (4216) 0x529248 STP	Q31, Q0, [X21, #16]

  (4216) 0x52924c LDP	Q1, Q2, [X9, #16]

  (4216) 0x529250 LDUR	Q3, [X28, #272]

  (4216) 0x529254 STUR	Q3, [X30, #272]

  (4216) 0x529258 STP	Q1, Q2, [X1, #16]

  (4216) 0x52925c LDP	Q4, Q5, [X8, #16]

  (4216) 0x529260 LDUR	Q6, [X28, #320]

  (4216) 0x529264 STUR	Q6, [X30, #320]

  (4216) 0x529268 STP	Q4, Q5, [X13, #16]

  (4216) 0x52926c LDP	Q7, Q14, [X7, #16]

  (4216) 0x529270 LDUR	Q16, [X28, #368]

  (4216) 0x529274 STUR	Q16, [X30, #368]

  (4216) 0x529278 STP	Q7, Q14, [X12, #16]

  (4216) 0x52927c LDUR	Q17, [X28, #416]

  (4216) 0x529280 LDP	Q18, Q19, [X6, #16]

  (4216) 0x529284 STUR	Q17, [X30, #416]

  (4216) 0x529288 STP	Q18, Q19, [X11, #16]

  (4216) 0x52928c LDP	Q20, Q21, [X4, #16]

  (4216) 0x529290 LDUR	Q22, [X28, #464]

  (4216) 0x529294 STUR	Q22, [X30, #464]

  (4216) 0x529298 STP	Q20, Q21, [X10, #16]

  (4216) 0x52929c CMP	X30, X18

  (4216) 0x5292a0 B.NE	5291dc

(4208) 0x5292a4 TBZ	W24, #0, 5292d4

(4208) 0x5292a8 AND	X24, X24, #8127

(4208) 0x5292ac ADD	X18, X24, X24,LSL #1

(4208) 0x5292b0 UBFM	X14, X18, #61, #60

(4208) 0x5292b4 ADD	X15, X0, X14

(4208) 0x5292b8 ADD	X16, X25, X14

(4208) 0x5292bc LDR	D23, [X0, X14]

(4208) 0x5292c0 STR	D23, [X25, X14]

(4208) 0x5292c4 LDR	D24, [X15, #8]

(4208) 0x5292c8 STR	D24, [X16, #8]

(4208) 0x5292cc LDR	D25, [X15, #16]

(4208) 0x5292d0 STR	D25, [X16, #16]

(4208) 0x5292d4 LDR	X6, [X22, #8]

(4208) 0x5292d8 ADRP	X7,

(4208) 0x5292dc ADD	X12, X7, #2208

(4208) 0x5292e0 LDR	X0, [X6, #632]

(4208) 0x5292e4 ORR	X4, XZR, X0

(4208) 0x5292e8 LDR	X11, [X4], #64

(4208) 0x5292ec LDR	X10, [X11, #72]

(4208) 0x5292f0 CMP	X10, X12

(4208) 0x5292f4 B.NE	529684

(4208) 0x5292f8 LDR	X14, [X22]

(4208) 0x5292fc ADRP	X24,

(4208) 0x529300 ADD	X18, X24, #3872

(4208) 0x529304 LDR	X15, [X22, #16]

(4208) 0x529308 LDR	X16, [X22, #72]

(4208) 0x52930c LDR	X28, [X14, #136]

(4208) 0x529310 ADD	X17, X15, #511

(4208) 0x529314 LDR	X19, [X4, #24]

(4208) 0x529318 UBFM	X24, X17, #9, #63

(4208) 0x52931c LDR	X21, [X16, #24]

(4208) 0x529320 CMP	X28, X18

(4208) 0x529324 B.NE	529674

(4208) 0x529328 ADD	X3, X15, #3

(4208) 0x52932c AND	X5, X3, #8062

(4208) 0x529330 UBFM	X30, X5, #62, #61

(4208) 0x529334 LDR	X28, [X22, #432]

(4208) 0x529338 STR	X30, [SP, #112]

(4208) 0x52933c ORR	X0, XZR, X28

(4208) 0x529340 BL	4c43c0

(4208) 0x529344 CMP	W26, #0

(4208) 0x529348 B.LE	5294d0

(4208) 0x52934c SBFM	X14, X27, #61, #31

(4208) 0x529350 CBZ	X24, 5294d0

(4208) 0x529354 LDR	X2, [SP, #112]

(4208) 0x529358 ADD	W26, W26, W26,LSL #1

(4208) 0x52935c ORR	X7, XZR, X21

(4208) 0x529360 SBFM	X27, X27, #60, #30

(4208) 0x529364 UBFM	X24, X24, #55, #54

(4208) 0x529368 MOVZ	W16, #0

(4208) 0x52936c ADD	X8, X19, X14

(4208) 0x529370 UBFM	X15, X2, #61, #60

(4208) 0x529374 HINT	#0

(4208) 0x529378 HINT	#0

(4208) 0x52937c HINT	#0

  (4213) 0x529380 ADD	W9, W16, #1

  (4213) 0x529384 ADD	W0, W16, #2

  (4213) 0x529388 ADD	X13, X25, W16,UXTW #3

  (4213) 0x52938c ADD	X18, X14, X7

  (4213) 0x529390 ADD	X12, X25, X9,LSL #3

  (4213) 0x529394 ORR	X10, XZR, X27

  (4213) 0x529398 ADD	X11, X25, X0,LSL #3

  (4213) 0x52939c ADD	X17, X18, X14

  (4213) 0x5293a0 MOVZ	X21, #0

    (4212) 0x5293a4 ADD	W1, W21, #512

    (4212) 0x5293a8 LDR	D29, [X11]

    (4212) 0x5293ac CMP	W1, W23

    (4212) 0x5293b0 CSEL	W6, W1, W23, #13

    (4212) 0x5293b4 LDR	D30, [X12]

    (4212) 0x5293b8 LDR	D31, [X13]

    (4212) 0x5293bc CMP	W6, W21

    (4212) 0x5293c0 B.LE	5294b0

    (4212) 0x5293c4 ADD	X4, X22, #200

    (4212) 0x5293c8 ORR	X30, XZR, X10

    (4212) 0x5293cc LDR	D20, [X4, #136]

    (4212) 0x5293d0 ORR	X3, XZR, X21

    (4212) 0x5293d4 LDR	D19, [X22, #200]

    (4212) 0x5293d8 LDP	D18, D17, [X4, #8]

    (4212) 0x5293dc LDP	D16, D7, [X4, #24]

    (4212) 0x5293e0 LDP	D6, D5, [X4, #40]

    (4212) 0x5293e4 LDP	D4, D3, [X4, #56]

    (4212) 0x5293e8 LDP	D28, D27, [X4, #72]

    (4212) 0x5293ec LDP	D26, D25, [X4, #88]

    (4212) 0x5293f0 LDP	D24, D23, [X4, #104]

    (4212) 0x5293f4 LDP	D22, D21, [X4, #120]

    (4212) 0x5293f8 HINT	#0

    (4212) 0x5293fc HINT	#0

      (4214) 0x529400 LDR	D15, [X8, X3,LSL #3]

      (4214) 0x529404 LDR	D2, [X19, X3,LSL #3]

      (4214) 0x529408 LDR	D0, [X19, X30]

      (4214) 0x52940c FSUB	D1, D15, S30

      (4214) 0x529410 FSUB	D2, D2, S31

      (4214) 0x529414 FSUB	D0, D0, S29

      (4214) 0x529418 FMUL	D14, D1, D24

      (4214) 0x52941c FMUL	D15, D1, D27

      (4214) 0x529420 FMUL	D1, D1, D21

      (4214) 0x529424 FMADD	D14, D2, D25, D14

      (4214) 0x529428 FMADD	D15, D2, D28, D15

      (4214) 0x52942c FMADD	D1, D2, D22, D1

      (4214) 0x529430 FMADD	D14, D0, D23, D14

      (4214) 0x529434 FMADD	D15, D0, D26, D15

      (4214) 0x529438 FRINTA	D2, D15

      (4214) 0x52943c FMADD	D1, D0, D20, D1

      (4214) 0x529440 FRINTA	D0, D14

      (4214) 0x529444 FSUB	D0, D14, S0

      (4214) 0x529448 FSUB	D2, D15, S2

      (4214) 0x52944c FRINTA	D14, D1

      (4214) 0x529450 FSUB	D15, D1, S14

      (4214) 0x529454 FMUL	D14, D0, D18

      (4214) 0x529458 FMUL	D1, D0, D7

      (4214) 0x52945c FMUL	D0, D0, D4

      (4214) 0x529460 FMADD	D14, D2, D19, D14

      (4214) 0x529464 FMADD	D1, D2, D16, D1

      (4214) 0x529468 FMADD	D2, D2, D5, D0

      (4214) 0x52946c FMADD	D14, D15, D17, D14

      (4214) 0x529470 FMADD	D1, D15, D6, D1

      (4214) 0x529474 FMADD	D15, D15, D3, D2

      (4214) 0x529478 STR	D14, [X18, X3,LSL #3]

      (4214) 0x52947c STR	D1, [X17, X3,LSL #3]

      (4214) 0x529480 STR	D15, [X18, X30]

      (4214) 0x529484 ADD	X30, X30, #8

      (4214) 0x529488 LDR	D0, [X17, X3,LSL #3]

      (4214) 0x52948c LDR	D2, [X18, X3,LSL #3]

      (4214) 0x529490 FMUL	D14, D0, D0

      (4214) 0x529494 FMADD	D1, D2, D2, D14

      (4214) 0x529498 FMADD	D15, D15, D15, D1

      (4214) 0x52949c FSQRT	D0, D15

      (4214) 0x5294a0 STR	D0, [X7, X3,LSL #3]

      (4214) 0x5294a4 ADD	X3, X3, #1

      (4214) 0x5294a8 CMP	W6, W3

      (4214) 0x5294ac B.GT	529400

    (4212) 0x5294b0 ADD	X21, X21, #512

    (4212) 0x5294b4 ADD	X10, X10, #1

    (4212) 0x5294b8 CMP	X21, X24

    (4212) 0x5294bc B.NE	5293a4

  (4213) 0x5294c0 ADD	W16, W16, #3

  (4213) 0x5294c4 ADD	X7, X7, X15

  (4213) 0x5294c8 CMP	W26, W16

  (4213) 0x5294cc B.NE	529380

(4208) 0x5294d0 ORR	X0, XZR, X28

(4208) 0x5294d4 BL	4c4660

(4208) 0x5294d8 ORR	X0, XZR, X20

(4208) 0x5294dc BL	4c4660

(4208) 0x5294e0 LDP	D14, D15, [SP, #96]

(4208) 0x5294e4 LDP	X19, X20, [SP, #16]

(4208) 0x5294e8 LDP	X21, X22, [SP, #32]

(4208) 0x5294ec LDP	X23, X24, [SP, #48]

(4208) 0x5294f0 LDP	X25, X26, [SP, #64]

(4208) 0x5294f4 LDP	X27, X28, [SP, #80]

(4208) 0x5294f8 LDP	X29, X30, [SP], #144

(4208) 0x5294fc RET

(4208) 0x529500 LDR	X9, [X0]

(4208) 0x529504 ADRP	X6,

(4208) 0x529508 ADD	X7, X2, #3

(4208) 0x52950c ADD	X8, X6, #3872

(4208) 0x529510 FMOV	D15, X7

(4208) 0x529514 AND	Z15.D, Z15.D, #1

(4208) 0x529518 LDR	X10, [X9, #136]

(4208) 0x52951c CMP	X10, X8

(4208) 0x529520 B.NE	5298b8

(4208) 0x529524 FMOV	X0, D15

(4208) 0x529528 UBFM	X27, X0, #62, #61

(4208) 0x52952c ADD	X11, X22, #344

(4208) 0x529530 MOVI	D0, #0

(4208) 0x529534 MADD	X1, X27, X1, XZR

(4208) 0x529538 ORR	X0, XZR, X11

(4208) 0x52953c STR	X11, [SP, #128]

(4208) 0x529540 BL	504b00

(4208) 0x529544 LDR	X1, [X22, #24]

(4208) 0x529548 ORR	X0, XZR, X21

(4208) 0x52954c BL	4a1e20

(4208) 0x529550 ADD	X12, X22, #96

(4208) 0x529554 LDR	X1, [X22, #24]

(4208) 0x529558 ORR	X0, XZR, X12

(4208) 0x52955c STR	X12, [SP, #120]

(4208) 0x529560 BL	4b87e0

(4208) 0x529564 LDR	X13, [X22, #24]

(4208) 0x529568 CBZ	X13, 529068

(4208) 0x52956c FMOV	X14, D15

(4208) 0x529570 MOVZ	X23, #0

(4208) 0x529574 LDP	X4, X2, [SP, #120]

(4208) 0x529578 MOVZ	X25, #0

(4208) 0x52957c UBFM	X27, X27, #61, #60

(4208) 0x529580 MOVZ	W3, #40

(4208) 0x529584 UBFM	X5, X14, #61, #60

  (4209) 0x529588 LDR	X19, [X21]

  (4209) 0x52958c UMADDL	X24, W25, W3, XZR

  (4209) 0x529590 LDR	X18, [X2, #24]

  (4209) 0x529594 LDR	X20, [X22, #16]

  (4209) 0x529598 ADD	X19, X19, X24

  (4209) 0x52959c LDR	X15, [X19, #16]

  (4209) 0x5295a0 ADD	X28, X18, X23

  (4209) 0x5295a4 CBNZ	X15, 52960c

  (4210) 0x5295a8 LDR	X26, [X4]

  (4210) 0x5295ac ADD	X16, X5, X23

  (4210) 0x5295b0 STR	X20, [X19, #8]

  (4210) 0x5295b4 ADD	X20, X18, X16

  (4210) 0x5295b8 STP	XZR, X28, [X19, #16]

  (4210) 0x5295bc ADD	X19, X26, X24

  (4210) 0x5295c0 LDR	X28, [X22, #16]

  (4210) 0x5295c4 LDR	X17, [X19, #16]

  (4210) 0x5295c8 CBNZ	X17, 529630

  (4210) 0x5295cc STR	X28, [X26, X24]

  (4210) 0x5295d0 ADD	X25, X25, #1

  (4210) 0x5295d4 ADD	X23, X23, X27

  (4210) 0x5295d8 STR	D15, [X19, #8]

  (4210) 0x5295dc LDR	X30, [X22, #24]

  (4210) 0x5295e0 STR	X20, [X19, #24]

  (4210) 0x5295e4 CMP	X30, X25

  (4210) 0x5295e8 B.LS	529068

  (4210) 0x5295ec LDR	X19, [X21]

  (4210) 0x5295f0 UMADDL	X24, W25, W3, XZR

  (4210) 0x5295f4 LDR	X18, [X2, #24]

  (4210) 0x5295f8 LDR	X20, [X22, #16]

  (4210) 0x5295fc ADD	X19, X19, X24

  (4210) 0x529600 LDR	X15, [X19, #16]

  (4210) 0x529604 ADD	X28, X18, X23

  (4210) 0x529608 CBZ	X15, 5295a8

    (4211) 0x52960c LDR	X0, [X19, #24]

    (4211) 0x529610 STP	X5, X2, [SP, #120]

    (4211) 0x529614 STR	X4, [SP, #136]

    (4211) 0x529618 BL	404150

(4208) 0x52961c LDP	X5, X2, [SP, #120]

(4208) 0x529620 MOVZ	W3, #40

(4208) 0x529624 LDR	X4, [SP, #136]

(4208) 0x529628 LDR	X18, [X2, #24]

(4208) 0x52962c B	5295a8

  (4209) 0x529630 LDR	X0, [X19, #24]

  (4209) 0x529634 ADD	X25, X25, #1

  (4209) 0x529638 ADD	X23, X23, X27

  (4209) 0x52963c STP	X5, X2, [SP, #120]

  (4209) 0x529640 STR	X4, [SP, #136]

  (4209) 0x529644 BL	404150

  (4209) 0x529648 LDP	X5, X2, [SP, #120]

  (4209) 0x52964c MOVZ	W3, #40

  (4209) 0x529650 STR	XZR, [X19, #16]

  (4209) 0x529654 STR	X28, [X26, X24]

  (4209) 0x529658 STR	D15, [X19, #8]

  (4209) 0x52965c LDR	X6, [X22, #24]

  (4209) 0x529660 STR	X20, [X19, #24]

  (4209) 0x529664 LDR	X4, [SP, #136]

  (4209) 0x529668 CMP	X25, X6

  (4209) 0x52966c B.CC	529588

(4208) 0x529670 B	529068

(4208) 0x529674 ORR	X0, XZR, X22

(4208) 0x529678 BLR	X28

(4208) 0x52967c ORR	X30, XZR, X0

(4208) 0x529680 B	529334

(4208) 0x529684 BLR	X10

(4208) 0x529688 ORR	X4, XZR, X0

(4208) 0x52968c B	5292f8

(4208) 0x529690 ADD	X19, X24, X24,LSL #1

(4208) 0x529694 ORR	X17, XZR, #3841

(4208) 0x529698 ORR	X1, XZR, X25

(4208) 0x52969c MOVK	X17, #43691

(4208) 0x5296a0 ADD	X28, X0, X19,LSL #3

(4208) 0x5296a4 MOVK	X17, #2730

(4208) 0x5296a8 SUB	X30, X28, X0

(4208) 0x5296ac SUB	X3, X30, #24

(4208) 0x5296b0 UBFM	X5, X3, #3, #63

(4208) 0x5296b4 MADD	X2, X5, X17, XZR

(4208) 0x5296b8 ADD	X21, X2, #1

(4208) 0x5296bc ANDS	X9, X21, #4224

(4208) 0x5296c0 B.EQ	5297dc

(4208) 0x5296c4 CMP	X9, #1

(4208) 0x5296c8 B.EQ	5297b4

(4208) 0x5296cc CMP	X9, #2

(4208) 0x5296d0 B.EQ	529794

(4208) 0x5296d4 CMP	X9, #3

(4208) 0x5296d8 B.EQ	529774

(4208) 0x5296dc CMP	X9, #4

(4208) 0x5296e0 B.EQ	529754

(4208) 0x5296e4 CMP	X9, #5

(4208) 0x5296e8 B.EQ	529734

(4208) 0x5296ec CMP	X9, #6

(4208) 0x5296f0 B.EQ	529714

(4208) 0x5296f4 LDR	D26, [X0]

(4208) 0x5296f8 ADD	X1, X25, #24

(4208) 0x5296fc ADD	X0, X0, #24

(4208) 0x529700 STR	D26, [X25]

(4208) 0x529704 LDUR	D27, [X0, #496]

(4208) 0x529708 STR	D27, [X25, #8]

(4208) 0x52970c LDUR	D28, [X0, #504]

(4208) 0x529710 STR	D28, [X25, #16]

(4208) 0x529714 LDR	D15, [X0]

(4208) 0x529718 ADD	X1, X1, #24

(4208) 0x52971c ADD	X0, X0, #24

(4208) 0x529720 STUR	D15, [X1, #488]

(4208) 0x529724 LDUR	D30, [X0, #496]

(4208) 0x529728 STUR	D30, [X1, #496]

(4208) 0x52972c LDUR	D31, [X0, #504]

(4208) 0x529730 STUR	D31, [X1, #504]

(4208) 0x529734 LDR	D0, [X0]

(4208) 0x529738 ADD	X1, X1, #24

(4208) 0x52973c ADD	X0, X0, #24

(4208) 0x529740 STUR	D0, [X1, #488]

(4208) 0x529744 LDUR	D29, [X0, #496]

(4208) 0x529748 STUR	D29, [X1, #496]

(4208) 0x52974c LDUR	D1, [X0, #504]

(4208) 0x529750 STUR	D1, [X1, #504]

(4208) 0x529754 LDR	D2, [X0]

(4208) 0x529758 ADD	X1, X1, #24

(4208) 0x52975c ADD	X0, X0, #24

(4208) 0x529760 STUR	D2, [X1, #488]

(4208) 0x529764 LDUR	D3, [X0, #496]

(4208) 0x529768 STUR	D3, [X1, #496]

(4208) 0x52976c LDUR	D4, [X0, #504]

(4208) 0x529770 STUR	D4, [X1, #504]

(4208) 0x529774 LDR	D5, [X0]

(4208) 0x529778 ADD	X1, X1, #24

(4208) 0x52977c ADD	X0, X0, #24

(4208) 0x529780 STUR	D5, [X1, #488]

(4208) 0x529784 LDUR	D6, [X0, #496]

(4208) 0x529788 STUR	D6, [X1, #496]

(4208) 0x52978c LDUR	D7, [X0, #504]

(4208) 0x529790 STUR	D7, [X1, #504]

(4208) 0x529794 LDR	D14, [X0]

(4208) 0x529798 ADD	X1, X1, #24

(4208) 0x52979c ADD	X0, X0, #24

(4208) 0x5297a0 STUR	D14, [X1, #488]

(4208) 0x5297a4 LDUR	D16, [X0, #496]

(4208) 0x5297a8 STUR	D16, [X1, #496]

(4208) 0x5297ac LDUR	D17, [X0, #504]

(4208) 0x5297b0 STUR	D17, [X1, #504]

(4208) 0x5297b4 LDR	D18, [X0]

(4208) 0x5297b8 ADD	X0, X0, #24

(4208) 0x5297bc ADD	X1, X1, #24

(4208) 0x5297c0 STUR	D18, [X1, #488]

(4208) 0x5297c4 LDUR	D19, [X0, #496]

(4208) 0x5297c8 STUR	D19, [X1, #496]

(4208) 0x5297cc LDUR	D20, [X0, #504]

(4208) 0x5297d0 STUR	D20, [X1, #504]

(4208) 0x5297d4 CMP	X28, X0

(4208) 0x5297d8 B.EQ	5292d4

  (4215) 0x5297dc LDR	D21, [X0]

  (4215) 0x5297e0 ORR	X8, XZR, X0

  (4215) 0x5297e4 ORR	X13, XZR, X1

  (4215) 0x5297e8 ADD	X0, X0, #192

  (4215) 0x5297ec ADD	X1, X1, #192

  (4215) 0x5297f0 STUR	D21, [X1, #320]

  (4215) 0x5297f4 LDUR	D22, [X0, #328]

  (4215) 0x5297f8 STUR	D22, [X1, #328]

  (4215) 0x5297fc LDUR	D23, [X0, #336]

  (4215) 0x529800 STUR	D23, [X1, #336]

  (4215) 0x529804 LDUR	D24, [X0, #344]

  (4215) 0x529808 STUR	D24, [X1, #344]

  (4215) 0x52980c LDUR	D25, [X0, #352]

  (4215) 0x529810 STUR	D25, [X1, #352]

  (4215) 0x529814 LDUR	D26, [X0, #360]

  (4215) 0x529818 STUR	D26, [X1, #360]

  (4215) 0x52981c LDUR	D27, [X0, #368]

  (4215) 0x529820 STUR	D27, [X1, #368]

  (4215) 0x529824 LDUR	D28, [X0, #376]

  (4215) 0x529828 STUR	D28, [X1, #376]

  (4215) 0x52982c LDUR	D15, [X0, #384]

  (4215) 0x529830 STUR	D15, [X1, #384]

  (4215) 0x529834 LDUR	D30, [X0, #392]

  (4215) 0x529838 STUR	D30, [X1, #392]

  (4215) 0x52983c LDUR	D31, [X0, #400]

  (4215) 0x529840 STUR	D31, [X1, #400]

  (4215) 0x529844 LDUR	D0, [X0, #408]

  (4215) 0x529848 STUR	D0, [X1, #408]

  (4215) 0x52984c LDUR	D29, [X0, #416]

  (4215) 0x529850 STUR	D29, [X1, #416]

  (4215) 0x529854 LDUR	D1, [X0, #424]

  (4215) 0x529858 STUR	D1, [X1, #424]

  (4215) 0x52985c LDUR	D2, [X0, #432]

  (4215) 0x529860 STUR	D2, [X1, #432]

  (4215) 0x529864 LDUR	D3, [X0, #440]

  (4215) 0x529868 STUR	D3, [X1, #440]

  (4215) 0x52986c LDUR	D4, [X0, #448]

  (4215) 0x529870 STUR	D4, [X1, #448]

  (4215) 0x529874 LDUR	D5, [X0, #456]

  (4215) 0x529878 STUR	D5, [X1, #456]

  (4215) 0x52987c LDUR	D6, [X0, #464]

  (4215) 0x529880 STUR	D6, [X1, #464]

  (4215) 0x529884 LDUR	D7, [X0, #472]

  (4215) 0x529888 STUR	D7, [X1, #472]

  (4215) 0x52988c LDUR	D14, [X0, #480]

  (4215) 0x529890 STUR	D14, [X1, #480]

  (4215) 0x529894 LDUR	D16, [X0, #488]

  (4215) 0x529898 STUR	D16, [X1, #488]

  (4215) 0x52989c LDR	D17, [X8, #176]

  (4215) 0x5298a0 STR	D17, [X13, #176]

  (4215) 0x5298a4 LDR	D18, [X8, #184]

  (4215) 0x5298a8 STR	D18, [X13, #184]

  (4215) 0x5298ac CMP	X28, X0

  (4215) 0x5298b0 B.NE	5297dc

(4208) 0x5298b4 B	5292d4

(4208) 0x5298b8 BLR	X10

(4208) 0x5298bc LDR	X1, [X22, #24]

(4208) 0x5298c0 ORR	X27, XZR, X0

(4208) 0x5298c4 B	52952c

0x5298c8 ORR	X21, XZR, X0

0x5298cc ORR	X0, XZR, X20

0x5298d0 BL	4c4660

0x5298d4 ORR	X0, XZR, X21

0x5298d8 BL	403e10

0x5298dc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	SoaDistanceTableABOMPTarget.h:61-233
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp:46
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:78-79
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:154,167,174-176,267
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:149,156-157,221-223,248
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1131
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:61-77,180-199,205-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.17 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 31% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 4.00 to 1.12 cycles (3.56x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.75	2.75	2.75	2.75	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50
cycles	2.00	2.00	2.75	2.75	2.75	2.75	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Overall L1	4.00

Vectorization ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 529020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X2, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X3, X2, X1, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CBZ X3, 529068 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X0, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 529500 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	SoaDistanceTableABOMPTarget.h:61-233
Module	exec

The function is defined in:

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/unique_ptr.h:193
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp:46
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:78-79
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:154,167,174-176,267
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:149,156-157,221-223,248
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1131
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:61-77,180-199,205-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.17 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.75	2.75	2.75	2.75	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50
cycles	2.00	2.00	2.75	2.75	2.75	2.75	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Overall L1	4.00

Vectorization ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 529020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X2, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X3, X2, X1, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CBZ X3, 529068 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X0, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 529500 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c4660 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)–	5.22	8.64
▼Loop 4208 - SoaDistanceTableABOMPTarget.h:68-233 - exec–	0	0.01
○Loop 4210 - OhmmsVector.h:149-248 - exec	0	0
○Loop 4216 - SoaDistanceTableABOMPTarget.h:194-196 - exec	0	0
▼Loop 4209 - SoaDistanceTableABOMPTarget.h:73-75 - exec–	0	0
○Loop 4211 - Mallocator.hpp:78-78 - exec	0	0
○Loop 4215 - SoaDistanceTableABOMPTarget.h:194-196 - exec	0	0
▼Loop 4213 - SoaDistanceTableABOMPTarget.h:214-228 - exec–	0	0
▼Loop 4212 - SoaDistanceTableABOMPTarget.h:215-228 - exec–	0.01	0.02
○Loop 4214 - SoaDistanceTableABOMPTarget.h:228-228 - exec	5.21	7.28

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code