OV - exec - Function miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: OneBodyJastrowRef.h:132-155 [...]	Coverage: 0.05%

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h: 132 - 155

--------------------------------------------------------------------------------

132:   inline void evaluateRatios(VirtualParticleSet& VP, std::vector<ValueType>& ratios)

133:   {

134:     for (int k = 0; k < ratios.size(); ++k)

135:       ratios[k] = std::exp(Vat[VP.refPtcl] - computeU(VP.getDistTableAB(myTableID).getDistRow(k).data()));

136:   }

137:

138:   inline valT computeU(const valT* dist)

139:   {

140:     valT curVat(0);

141:     if (NumGroups > 0)

142:     {

143:       for (int jg = 0; jg < NumGroups; ++jg)

144:       {

145:         if (F[jg] != nullptr)

146:           curVat += F[jg]->evaluateV(-1, Ions.first(jg), Ions.last(jg), dist, DistCompressed.data());

147:       }

148:     }

149:     else

150:     {

151:       for (int c = 0; c < Nions; ++c)

152:       {

153:         int gid = Ions.GroupID[c];

154:         if (F[gid] != nullptr)

155:           curVat += F[gid]->evaluate(dist[c]);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 166 - 260

--------------------------------------------------------------------------------

166:     if (r >= cutoff_radius)

167:       return 0.0;

168:     r *= DeltaRInv;

169:     real_type ipart, t;

170:     t     = std::modf(r, &ipart);

171:     int i = (int)ipart;

172:     real_type tp[4];

173:     tp[0] = t * t * t;

[...]

179:       (SplineCoefs[i+0]*(A[ 0]*tp[0] + A[ 1]*tp[1] + A[ 2]*tp[2] + A[ 3]*tp[3])+

180:        SplineCoefs[i+1]*(A[ 4]*tp[0] + A[ 5]*tp[1] + A[ 6]*tp[2] + A[ 7]*tp[3])+

181:        SplineCoefs[i+2]*(A[ 8]*tp[0] + A[ 9]*tp[1] + A[10]*tp[2] + A[11]*tp[3])+

182:        SplineCoefs[i+3]*(A[12]*tp[0] + A[13]*tp[1] + A[14]*tp[2] + A[15]*tp[3]));

[...]

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 993 - 1131

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

0x416b20 STP	X29, X30, [SP, #832]!

0x416b24 ADD	X29, SP, #0

0x416b28 STP	X21, X22, [SP, #32]

0x416b2c ORR	X22, XZR, X1

0x416b30 STP	X23, X24, [SP, #48]

0x416b34 ADD	X23, X0, #216

0x416b38 STP	X25, X26, [SP, #64]

0x416b3c ORR	X26, XZR, X0

0x416b40 STR	X2, [SP, #160]

0x416b44 LDP	X1, X0, [X2]

0x416b48 CMP	X1, X0

0x416b4c B.EQ	417098

0x416b50 STP	X19, X20, [SP, #16]

0x416b54 MOVZ	X20, #0

0x416b58 MOVZ	X19, #0

0x416b5c STP	X27, X28, [SP, #80]

0x416b60 STP	D8, D9, [SP, #96]

0x416b64 STP	D10, D11, [SP, #112]

0x416b68 STP	D12, D13, [SP, #128]

0x416b6c STP	D14, D15, [SP, #144]

    (281) 0x416b70 LDR	X2, [X23, #24]

    (281) 0x416b74 ORR	X0, XZR, X22

    (281) 0x416b78 LDRSW	X3, [X22, #672]

    (281) 0x416b7c LDR	W1, [X26, #168]

    (281) 0x416b80 LDR	D15, [X2, X3,LSL #3]

    (281) 0x416b84 BL	484780

    (281) 0x416b88 LDR	X4, [X0, #72]

    (281) 0x416b8c LDR	W10, [X26, #152]

    (281) 0x416b90 ADD	X5, X4, X20

    (281) 0x416b94 LDR	X27, [X5, #24]

    (281) 0x416b98 CMP	W10, #0

    (281) 0x416b9c B.LE	4170ac

    (281) 0x416ba0 LDR	X11, [X26, #456]

    (281) 0x416ba4 MOVI	D1, #0

    (281) 0x416ba8 MOVZ	X7, #0

    (281) 0x416bac UBFM	X10, X10, #62, #31

    (281) 0x416bb0 CNTW	X9, ALL

    (281) 0x416bb4 PTRUE	P7.B, ALL

    (281) 0x416bb8 HINT	#0

    (281) 0x416bbc HINT	#0

      (280) 0x416bc0 UBFM	X17, X7, #63, #62

      (280) 0x416bc4 LDR	X30, [X11, X17]

      (280) 0x416bc8 CBZ	X30, 417048

      (280) 0x416bcc LDR	X5, [X26, #160]

      (280) 0x416bd0 LDR	X28, [X26, #328]

      (280) 0x416bd4 LDR	X6, [X5, #616]

      (280) 0x416bd8 LDR	X21, [X6, #24]

      (280) 0x416bdc ADD	X8, X21, X7

      (280) 0x416be0 LDR	W13, [X21, X7]

      (280) 0x416be4 LDR	W14, [X8, #4]

      (280) 0x416be8 CMP	W14, W13

      (280) 0x416bec B.LE	417048

      (280) 0x416bf0 SUB	W15, W14, W13

      (280) 0x416bf4 SBFM	X12, X13, #61, #31

      (280) 0x416bf8 LDR	D6, [X30, #8]

      (280) 0x416bfc ANDS	W18, W15, #128

      (280) 0x416c00 ADD	X6, X27, X12

      (280) 0x416c04 MOVZ	W17, #0

      (280) 0x416c08 ORR	W5, WZR, W13

      (280) 0x416c0c B.EQ	416d44

      (280) 0x416c10 CMP	W18, #1

      (280) 0x416c14 B.EQ	416d18

      (280) 0x416c18 CMP	W18, #2

      (280) 0x416c1c B.EQ	416cf4

      (280) 0x416c20 CMP	W18, #3

      (280) 0x416c24 B.EQ	416cd0

      (280) 0x416c28 CMP	W18, #4

      (280) 0x416c2c B.EQ	416cac

      (280) 0x416c30 CMP	W18, #5

      (280) 0x416c34 B.EQ	416c88

      (280) 0x416c38 CMP	W18, #6

      (280) 0x416c3c B.EQ	416c64

      (280) 0x416c40 LDR	D7, [X27, X12]

      (280) 0x416c44 FCMPE	D6, D7

      (280) 0x416c48 B.LS	416c5c

      (280) 0x416c4c CMN	W13, #1

      (280) 0x416c50 B.EQ	416c5c

      (280) 0x416c54 MOVZ	W17, #1

      (280) 0x416c58 STR	D7, [X28]

      (280) 0x416c5c ADD	X6, X6, #8

      (280) 0x416c60 ADD	W5, W13, #1

      (280) 0x416c64 LDR	D8, [X6]

      (280) 0x416c68 FCMPE	D6, D8

      (280) 0x416c6c B.LS	416c80

      (280) 0x416c70 CMN	W5, #1

      (280) 0x416c74 B.EQ	416c80

      (280) 0x416c78 STR	D8, [X28, X17,UXTW #3]

      (280) 0x416c7c ADD	W17, W17, #1

      (280) 0x416c80 ADD	X6, X6, #8

      (280) 0x416c84 ADD	W5, W5, #1

      (280) 0x416c88 LDR	D26, [X6]

      (280) 0x416c8c FCMPE	D6, D26

      (280) 0x416c90 B.LS	416ca4

      (280) 0x416c94 CMN	W5, #1

      (280) 0x416c98 B.EQ	416ca4

      (280) 0x416c9c STR	D26, [X28, X17,UXTW #3]

      (280) 0x416ca0 ADD	W17, W17, #1

      (280) 0x416ca4 ADD	X6, X6, #8

      (280) 0x416ca8 ADD	W5, W5, #1

      (280) 0x416cac LDR	D9, [X6]

      (280) 0x416cb0 FCMPE	D6, D9

      (280) 0x416cb4 B.LS	416cc8

      (280) 0x416cb8 CMN	W5, #1

      (280) 0x416cbc B.EQ	416cc8

      (280) 0x416cc0 STR	D9, [X28, X17,UXTW #3]

      (280) 0x416cc4 ADD	W17, W17, #1

      (280) 0x416cc8 ADD	X6, X6, #8

      (280) 0x416ccc ADD	W5, W5, #1

      (280) 0x416cd0 LDR	D10, [X6]

      (280) 0x416cd4 FCMPE	D6, D10

      (280) 0x416cd8 B.LS	416cec

      (280) 0x416cdc CMN	W5, #1

      (280) 0x416ce0 B.EQ	416cec

      (280) 0x416ce4 STR	D10, [X28, X17,UXTW #3]

      (280) 0x416ce8 ADD	W17, W17, #1

      (280) 0x416cec ADD	X6, X6, #8

      (280) 0x416cf0 ADD	W5, W5, #1

      (280) 0x416cf4 LDR	D20, [X6]

      (280) 0x416cf8 FCMPE	D6, D20

      (280) 0x416cfc B.LS	416d10

      (280) 0x416d00 CMN	W5, #1

      (280) 0x416d04 B.EQ	416d10

      (280) 0x416d08 STR	D20, [X28, X17,UXTW #3]

      (280) 0x416d0c ADD	W17, W17, #1

      (280) 0x416d10 ADD	X6, X6, #8

      (280) 0x416d14 ADD	W5, W5, #1

      (280) 0x416d18 LDR	D11, [X6]

      (280) 0x416d1c FCMPE	D6, D11

      (280) 0x416d20 B.LS	416d34

      (280) 0x416d24 CMN	W5, #1

      (280) 0x416d28 B.EQ	416d34

      (280) 0x416d2c STR	D11, [X28, X17,UXTW #3]

      (280) 0x416d30 ADD	W17, W17, #1

      (280) 0x416d34 ADD	W5, W5, #1

      (280) 0x416d38 ADD	X6, X6, #8

      (280) 0x416d3c CMP	W14, W5

      (280) 0x416d40 B.EQ	416e54

        (282) 0x416d44 LDR	D12, [X6]

        (282) 0x416d48 FCMPE	D6, D12

        (282) 0x416d4c B.LS	416d60

        (282) 0x416d50 CMN	W5, #1

        (282) 0x416d54 B.EQ	416d60

        (282) 0x416d58 STR	D12, [X28, X17,UXTW #3]

        (282) 0x416d5c ADD	W17, W17, #1

        (282) 0x416d60 LDR	D13, [X6, #8]

        (282) 0x416d64 ADD	W1, W5, #1

        (282) 0x416d68 ADD	X16, X6, #8

        (282) 0x416d6c FCMPE	D6, D13

        (282) 0x416d70 B.LS	416d84

        (282) 0x416d74 CMN	W1, #1

        (282) 0x416d78 B.EQ	416d84

        (282) 0x416d7c STR	D13, [X28, X17,UXTW #3]

        (282) 0x416d80 ADD	W17, W17, #1

        (282) 0x416d84 LDR	D16, [X16, #8]

        (282) 0x416d88 ADD	W25, W1, #1

        (282) 0x416d8c FCMPE	D6, D16

        (282) 0x416d90 B.LS	416da4

        (282) 0x416d94 CMN	W25, #1

        (282) 0x416d98 B.EQ	416da4

        (282) 0x416d9c STR	D16, [X28, X17,UXTW #3]

        (282) 0x416da0 ADD	W17, W17, #1

        (282) 0x416da4 LDR	D17, [X16, #16]

        (282) 0x416da8 ADD	W3, W1, #2

        (282) 0x416dac FCMPE	D6, D17

        (282) 0x416db0 B.LS	416dc4

        (282) 0x416db4 CMN	W3, #1

        (282) 0x416db8 B.EQ	416dc4

        (282) 0x416dbc STR	D17, [X28, X17,UXTW #3]

        (282) 0x416dc0 ADD	W17, W17, #1

        (282) 0x416dc4 LDR	D18, [X16, #24]

        (282) 0x416dc8 ADD	W0, W1, #3

        (282) 0x416dcc FCMPE	D6, D18

        (282) 0x416dd0 B.LS	416de4

        (282) 0x416dd4 CMN	W0, #1

        (282) 0x416dd8 B.EQ	416de4

        (282) 0x416ddc STR	D18, [X28, X17,UXTW #3]

        (282) 0x416de0 ADD	W17, W17, #1

        (282) 0x416de4 LDR	D22, [X16, #32]

        (282) 0x416de8 ADD	W4, W1, #4

        (282) 0x416dec FCMPE	D6, D22

        (282) 0x416df0 B.LS	416e04

        (282) 0x416df4 CMN	W4, #1

        (282) 0x416df8 B.EQ	416e04

        (282) 0x416dfc STR	D22, [X28, X17,UXTW #3]

        (282) 0x416e00 ADD	W17, W17, #1

        (282) 0x416e04 LDR	D30, [X16, #40]

        (282) 0x416e08 ADD	W2, W1, #5

        (282) 0x416e0c FCMPE	D6, D30

        (282) 0x416e10 B.LS	416e24

        (282) 0x416e14 CMN	W2, #1

        (282) 0x416e18 B.EQ	416e24

        (282) 0x416e1c STR	D30, [X28, X17,UXTW #3]

        (282) 0x416e20 ADD	W17, W17, #1

        (282) 0x416e24 LDR	D31, [X16, #48]

        (282) 0x416e28 ADD	W24, W1, #6

        (282) 0x416e2c FCMPE	D6, D31

        (282) 0x416e30 B.LS	416e44

        (282) 0x416e34 CMN	W24, #1

        (282) 0x416e38 B.EQ	416e44

        (282) 0x416e3c STR	D31, [X28, X17,UXTW #3]

        (282) 0x416e40 ADD	W17, W17, #1

        (282) 0x416e44 ADD	W5, W1, #7

        (282) 0x416e48 ADD	X6, X16, #56

        (282) 0x416e4c CMP	W14, W5

        (282) 0x416e50 B.NE	416d44

      (280) 0x416e54 CBZ	W17, 417048

      (280) 0x416e58 ADD	X8, X30, #568

      (280) 0x416e5c LD1RD	{Z3.D}, P7/Z, [X30, #3]

      (280) 0x416e60 LD1RD	{Z4.D}, P7/Z, [X30, #4]

      (280) 0x416e64 LD1RD	{Z5.D}, P7/Z, [X30, #5]

      (280) 0x416e68 LD1RD	{Z6.D}, P7/Z, [X30, #6]

      (280) 0x416e6c LD1RD	{Z7.D}, P7/Z, [X30, #7]

      (280) 0x416e70 LD1RD	{Z16.D}, P7/Z, [X30, #8]

      (280) 0x416e74 LD1RD	{Z17.D}, P7/Z, [X30, #9]

      (280) 0x416e78 LD1RD	{Z18.D}, P7/Z, [X30, #10]

      (280) 0x416e7c LD1RD	{Z19.D}, P7/Z, [X30, #11]

      (280) 0x416e80 LD1RD	{Z20.D}, P7/Z, [X30, #12]

      (280) 0x416e84 LD1RD	{Z21.D}, P7/Z, [X30, #13]

      (280) 0x416e88 LD1RD	{Z22.D}, P7/Z, [X30, #14]

      (280) 0x416e8c LD1RD	{Z23.D}, P7/Z, [X30, #15]

      (280) 0x416e90 LD1RD	{Z24.D}, P7/Z, [X30, #16]

      (280) 0x416e94 LD1RD	{Z25.D}, P7/Z, [X30, #17]

      (280) 0x416e98 LD1RD	{Z26.D}, P7/Z, [X30, #18]

      (280) 0x416e9c LDR	X30, [X30, #536]

      (280) 0x416ea0 MOVZ	X14, #0

      (280) 0x416ea4 ADDVL	X21, X28, #1

      (280) 0x416ea8 DUP	Z28.D, #0

      (280) 0x416eac ORR	W13, WZR, W17

      (280) 0x416eb0 LD1RD	{Z2.D}, P7/Z, [X8]

      (280) 0x416eb4 UQDECD	W13, ALL

      (280) 0x416eb8 ORR	Z29.D, Z28.D, Z28.D

      (280) 0x416ebc WHILELO	P5.D, WZR, W13

      (280) 0x416ec0 WHILELO	P6.D, WZR, W17

        (283) 0x416ec4 LD1D	{Z0.D}, P5/Z, [X21, X14,LSL #3]

        (283) 0x416ec8 LD1D	{Z27.D}, P6/Z, [X28, X14,LSL #3]

        (283) 0x416ecc FMUL	Z8.D, Z2.D, Z0.D

        (283) 0x416ed0 FMUL	Z14.D, Z2.D, Z27.D

        (283) 0x416ed4 MOVPRFX	Z9, Z8

        (283) 0x416ed8 FRINTZ	Z9.D, P7/M, Z8.D

        (283) 0x416edc MOVPRFX	Z10, Z8

        (283) 0x416ee0 FCVTZS	Z10.S, P7/M, Z8.D

        (283) 0x416ee4 FSUB	Z31.D, Z8.D, Z9.D

        (283) 0x416ee8 MOVPRFX	Z11, Z14

        (283) 0x416eec FCVTZS	Z11.S, P7/M, Z14.D

        (283) 0x416ef0 FMUL	Z27.D, Z31.D, Z31.D

        (283) 0x416ef4 MOVPRFX	Z8, Z18

        (283) 0x416ef8 FMLA	Z8.D, P7/M, Z17.D, Z31.D

        (283) 0x416efc FMUL	Z0.D, Z27.D, Z31.D

        (283) 0x416f00 FMUL	Z12.D, Z16.D, Z27.D

        (283) 0x416f04 FMLA	Z12.D, P7/M, Z7.D, Z0.D

        (283) 0x416f08 UZP1	Z30.S, Z11.S, Z10.S

        (283) 0x416f0c FADD	Z11.D, Z8.D, Z12.D

        (283) 0x416f10 MOVPRFX	Z13, Z30

        (283) 0x416f14 ADD	Z13.S, Z13.S, #1

        (283) 0x416f18 MOVPRFX	Z8, Z6

        (283) 0x416f1c FMLA	Z8.D, P7/M, Z5.D, Z31.D

        (283) 0x416f20 SUNPKHI	Z9.D, Z13

        (283) 0x416f24 LD1D	{Z12.D}, P5/Z, [X30, Z9.D,LSL #3]

        (283) 0x416f28 FMUL	Z10.D, Z4.D, Z27.D

        (283) 0x416f2c FMUL	Z11.D, Z11.D, Z12.D

        (283) 0x416f30 FMLA	Z10.D, P7/M, Z3.D, Z0.D

        (283) 0x416f34 SUNPKHI	Z9.D, Z30

        (283) 0x416f38 FADD	Z12.D, Z8.D, Z10.D

        (283) 0x416f3c LD1D	{Z8.D}, P5/Z, [X30, Z9.D,LSL #3]

        (283) 0x416f40 FMUL	Z10.D, Z20.D, Z27.D

        (283) 0x416f44 FMAD	Z12.D, P7/M, Z8.D, Z11.D

        (283) 0x416f48 FMLA	Z10.D, P7/M, Z19.D, Z0.D

        (283) 0x416f4c MOVPRFX	Z11, Z22

        (283) 0x416f50 FMLA	Z11.D, P7/M, Z21.D, Z31.D

        (283) 0x416f54 FMUL	Z27.D, Z27.D, Z24.D

        (283) 0x416f58 FADD	Z8.D, Z11.D, Z10.D

        (283) 0x416f5c FMAD	Z0.D, P7/M, Z23.D, Z27.D

        (283) 0x416f60 FADD	Z28.D, P5/M, Z28.D, Z12.D

        (283) 0x416f64 MOVPRFX	Z27, Z30

        (283) 0x416f68 ADD	Z27.S, Z27.S, #3

        (283) 0x416f6c MOVPRFX	Z12, Z30

        (283) 0x416f70 ADD	Z12.S, Z12.S, #2

        (283) 0x416f74 SUNPKHI	Z10.D, Z27

        (283) 0x416f78 SUNPKLO	Z30.D, Z30

        (283) 0x416f7c LD1D	{Z11.D}, P5/Z, [X30, Z10.D,LSL #3]

        (283) 0x416f80 FMAD	Z31.D, P7/M, Z25.D, Z26.D

        (283) 0x416f84 FADD	Z31.D, Z31.D, Z0.D

        (283) 0x416f88 SUNPKHI	Z0.D, Z12

        (283) 0x416f8c LD1D	{Z9.D}, P5/Z, [X30, Z0.D,LSL #3]

        (283) 0x416f90 FMLA	Z28.D, P5/M, Z8.D, Z9.D

        (283) 0x416f94 SUNPKLO	Z8.D, Z12

        (283) 0x416f98 FMLA	Z28.D, P5/M, Z11.D, Z31.D

        (283) 0x416f9c LD1D	{Z0.D}, P6/Z, [X30, Z8.D,LSL #3]

        (283) 0x416fa0 LD1D	{Z11.D}, P6/Z, [X30, Z30.D,LSL #3]

        (283) 0x416fa4 SUNPKLO	Z12.D, Z27

        (283) 0x416fa8 MOVPRFX	Z31, Z14

        (283) 0x416fac FRINTZ	Z31.D, P7/M, Z14.D

        (283) 0x416fb0 SUNPKLO	Z13.D, Z13

        (283) 0x416fb4 FSUB	Z8.D, Z14.D, Z31.D

        (283) 0x416fb8 FMUL	Z30.D, Z8.D, Z8.D

        (283) 0x416fbc FMUL	Z27.D, Z30.D, Z8.D

        (283) 0x416fc0 FMUL	Z14.D, Z16.D, Z30.D

        (283) 0x416fc4 FMLA	Z14.D, P7/M, Z7.D, Z27.D

        (283) 0x416fc8 LD1D	{Z10.D}, P6/Z, [X30, Z13.D,LSL #3]

        (283) 0x416fcc ADD	X14, X14, X9

        (283) 0x416fd0 LD1D	{Z13.D}, P6/Z, [X30, Z12.D,LSL #3]

        (283) 0x416fd4 WHILELO	P5.D, W14, W13

        (283) 0x416fd8 MOVPRFX	Z12, Z18

        (283) 0x416fdc FMLA	Z12.D, P7/M, Z17.D, Z8.D

        (283) 0x416fe0 FADD	Z31.D, Z12.D, Z14.D

        (283) 0x416fe4 MOVPRFX	Z14, Z6

        (283) 0x416fe8 FMLA	Z14.D, P7/M, Z5.D, Z8.D

        (283) 0x416fec FMUL	Z12.D, Z31.D, Z10.D

        (283) 0x416ff0 FMUL	Z9.D, Z4.D, Z30.D

        (283) 0x416ff4 FMUL	Z10.D, Z20.D, Z30.D

        (283) 0x416ff8 FMLA	Z9.D, P7/M, Z3.D, Z27.D

        (283) 0x416ffc MOVPRFX	Z31, Z22

        (283) 0x417000 FMLA	Z31.D, P7/M, Z21.D, Z8.D

        (283) 0x417004 FADD	Z9.D, Z14.D, Z9.D

        (283) 0x417008 FMUL	Z30.D, Z30.D, Z24.D

        (283) 0x41700c FMAD	Z9.D, P7/M, Z11.D, Z12.D

        (283) 0x417010 FMAD	Z8.D, P7/M, Z25.D, Z26.D

        (283) 0x417014 MOVPRFX	Z11, Z10

        (283) 0x417018 FMLA	Z11.D, P7/M, Z19.D, Z27.D

        (283) 0x41701c FADD	Z29.D, P6/M, Z29.D, Z9.D

        (283) 0x417020 FMAD	Z27.D, P7/M, Z23.D, Z30.D

        (283) 0x417024 FADD	Z14.D, Z31.D, Z11.D

        (283) 0x417028 FMLA	Z29.D, P6/M, Z14.D, Z0.D

        (283) 0x41702c FADD	Z0.D, Z8.D, Z27.D

        (283) 0x417030 FMLA	Z29.D, P6/M, Z13.D, Z0.D

        (283) 0x417034 WHILELO	P6.D, W14, W17

        (283) 0x417038 B.NE	416ec4

      (280) 0x41703c FADD	Z2.D, Z29.D, Z28.D

      (280) 0x417040 FADDV	D28, P7, Z2.D

      (280) 0x417044 FADD	D1, D1, D28

      (280) 0x417048 ADD	X7, X7, #4

      (280) 0x41704c CMP	X10, X7

      (280) 0x417050 B.NE	416bc0

    (281) 0x417054 FSUB	D15, D15, S1

    (281) 0x417058 FMOV	D0, D15

    (281) 0x41705c ADD	X20, X20, #40

    (281) 0x417060 BL	403a70

    (281) 0x417064 LDR	X28, [SP, #160]

    (281) 0x417068 LDP	X15, X12, [X28]

    (281) 0x41706c SUB	X18, X12, X15

    (281) 0x417070 STR	D0, [X15, X19,UXTW #3]

    (281) 0x417074 ADD	X19, X19, #1

    (281) 0x417078 CMP	X19, X18,ASR #3

    (281) 0x41707c B.CC	416b70

(284) 0x417080 LDP	D8, D9, [SP, #96]

(284) 0x417084 LDP	X19, X20, [SP, #16]

(284) 0x417088 LDP	X27, X28, [SP, #80]

(284) 0x41708c LDP	D10, D11, [SP, #112]

(284) 0x417090 LDP	D12, D13, [SP, #128]

(284) 0x417094 LDP	D14, D15, [SP, #144]

(284) 0x417098 LDP	X21, X22, [SP, #32]

(284) 0x41709c LDP	X23, X24, [SP, #48]

(284) 0x4170a0 LDP	X25, X26, [SP, #64]

(284) 0x4170a4 LDP	X29, X30, [SP], #192

(284) 0x4170a8 RET

  (279) 0x4170ac LDR	W28, [X26, #144]

  (279) 0x4170b0 CMP	W28, #0

  (279) 0x4170b4 B.LE	417058

  (279) 0x4170b8 LDR	X6, [X26, #160]

  (279) 0x4170bc SBFM	X28, X28, #0, #31

  (279) 0x4170c0 MOVI	D14, #0

  (279) 0x4170c4 MOVZ	X24, #0

  (279) 0x4170c8 LDR	X10, [X26, #456]

  (279) 0x4170cc LDR	X21, [X6, #24]

  (279) 0x4170d0 TBZ	W28, #0, 4171b0

  (279) 0x4170d4 LDRSW	X7, [X21]

  (279) 0x4170d8 LDR	X24, [X10, X7,LSL #3]

  (279) 0x4170dc CBZ	X24, 4171a4

  (279) 0x4170e0 LDR	D31, [X27]

  (279) 0x4170e4 LDR	D30, [X24, #8]

  (279) 0x4170e8 FCMPE	D31, D30

  (279) 0x4170ec B.GE	4171a4

  (279) 0x4170f0 LDR	D0, [X24, #568]

  (279) 0x4170f4 ADD	X0, SP, #184

  (279) 0x4170f8 STR	X10, [SP, #168]

  (279) 0x4170fc FMUL	D0, D31, D0

  (279) 0x417100 BL	403d10

  (279) 0x417104 FMUL	D2, D0, D0

  (279) 0x417108 LDP	D25, D29, [X24, #24]

  (279) 0x41710c LDP	D19, D1, [X24, #88]

  (279) 0x417110 LDP	D28, D23, [X24, #40]

  (279) 0x417114 LDP	D21, D24, [X24, #104]

  (279) 0x417118 FMUL	D27, D2, D0

  (279) 0x41711c FMUL	D4, D2, D29

  (279) 0x417120 LDP	D26, D6, [X24, #56]

  (279) 0x417124 FMUL	D5, D2, D1

  (279) 0x417128 LDP	D9, D20, [X24, #120]

  (279) 0x41712c FMADD	D3, D0, D28, D23

  (279) 0x417130 FMADD	D11, D27, D25, D4

  (279) 0x417134 LDR	D22, [SP, #184]

  (279) 0x417138 FMADD	D8, D0, D21, D24

  (279) 0x41713c FMADD	D16, D27, D19, D5

  (279) 0x417140 LDP	D12, D13, [X24, #72]

  (279) 0x417144 FMUL	D7, D2, D6

  (279) 0x417148 LDP	D28, D23, [X24, #136]

  (279) 0x41714c FMUL	D10, D2, D20

  (279) 0x417150 FCVTZS	W9, D22

  (279) 0x417154 LDR	X8, [X24, #536]

  (279) 0x417158 FMADD	D17, D27, D26, D7

  (279) 0x41715c FMADD	D18, D0, D12, D13

  (279) 0x417160 LDR	X10, [SP, #168]

  (279) 0x417164 FMADD	D30, D27, D9, D10

  (279) 0x417168 FADD	D25, D11, D3

  (279) 0x41716c FMADD	D0, D0, D28, D23

  (279) 0x417170 FADD	D31, D16, D8

  (279) 0x417174 SBFM	X11, X9, #61, #31

  (279) 0x417178 ADD	X12, X8, X11

  (279) 0x41717c LDR	D19, [X8, X11]

  (279) 0x417180 LDP	D1, D2, [X12, #8]

  (279) 0x417184 LDR	D4, [X12, #24]

  (279) 0x417188 FADD	D29, D17, D18

  (279) 0x41718c FADD	D21, D0, D30

  (279) 0x417190 FMADD	D14, D19, D25, D14

  (279) 0x417194 FMUL	D3, D31, D2

  (279) 0x417198 FMADD	D27, D4, D21, D14

  (279) 0x41719c FMADD	D24, D1, D29, D3

  (279) 0x4171a0 FADD	D14, D24, D27

  (279) 0x4171a4 MOVZ	X24, #1

  (279) 0x4171a8 CMP	X28, X24

  (279) 0x4171ac B.EQ	417360

    (285) 0x4171b0 LDRSW	X13, [X21, X24,LSL #2]

    (285) 0x4171b4 LDR	X25, [X10, X13,LSL #3]

    (285) 0x4171b8 CBZ	X25, 417280

    (285) 0x4171bc LDR	D5, [X27, X24,LSL #3]

    (285) 0x4171c0 LDR	D26, [X25, #8]

    (285) 0x4171c4 FCMPE	D5, D26

    (285) 0x4171c8 B.GE	417280

    (285) 0x4171cc LDR	D6, [X25, #568]

    (285) 0x4171d0 ADD	X0, SP, #184

    (285) 0x4171d4 STR	X10, [SP, #168]

    (285) 0x4171d8 FMUL	D0, D5, D6

    (285) 0x4171dc BL	403d10

    (285) 0x4171e0 FMUL	D12, D0, D0

    (285) 0x4171e4 LDP	D7, D8, [X25, #24]

    (285) 0x4171e8 LDP	D10, D11, [X25, #88]

    (285) 0x4171ec LDP	D9, D20, [X25, #40]

    (285) 0x4171f0 LDP	D16, D17, [X25, #104]

    (285) 0x4171f4 FMUL	D22, D12, D0

    (285) 0x4171f8 FMUL	D18, D12, D8

    (285) 0x4171fc LDP	D23, D30, [X25, #56]

    (285) 0x417200 FMUL	D31, D12, D11

    (285) 0x417204 LDP	D1, D25, [X25, #120]

    (285) 0x417208 FMADD	D13, D0, D9, D20

    (285) 0x41720c FMADD	D28, D22, D7, D18

    (285) 0x417210 LDR	D26, [SP, #184]

    (285) 0x417214 FMADD	D19, D0, D16, D17

    (285) 0x417218 FMADD	D24, D22, D10, D31

    (285) 0x41721c LDP	D3, D21, [X25, #72]

    (285) 0x417220 FMUL	D29, D12, D30

    (285) 0x417224 LDP	D9, D20, [X25, #136]

    (285) 0x417228 FMUL	D2, D12, D25

    (285) 0x41722c FCVTZS	W15, D26

    (285) 0x417230 LDR	X14, [X25, #536]

    (285) 0x417234 FMADD	D4, D22, D23, D29

    (285) 0x417238 FMADD	D27, D0, D3, D21

    (285) 0x41723c LDR	X10, [SP, #168]

    (285) 0x417240 FMADD	D5, D22, D1, D2

    (285) 0x417244 FADD	D6, D28, D13

    (285) 0x417248 FMADD	D0, D0, D9, D20

    (285) 0x41724c FADD	D7, D24, D19

    (285) 0x417250 SBFM	X18, X15, #61, #31

    (285) 0x417254 ADD	X1, X14, X18

    (285) 0x417258 LDR	D10, [X14, X18]

    (285) 0x41725c LDP	D11, D12, [X1, #8]

    (285) 0x417260 LDR	D18, [X1, #24]

    (285) 0x417264 FADD	D8, D4, D27

    (285) 0x417268 FADD	D16, D0, D5

    (285) 0x41726c FMADD	D14, D10, D6, D14

    (285) 0x417270 FMUL	D13, D7, D12

    (285) 0x417274 FMADD	D22, D18, D16, D14

    (285) 0x417278 FMADD	D17, D11, D8, D13

    (285) 0x41727c FADD	D14, D17, D22

    (285) 0x417280 ADD	X24, X24, #1

    (285) 0x417284 LDRSW	X16, [X21, X24,LSL #2]

    (285) 0x417288 LDR	X25, [X10, X16,LSL #3]

    (285) 0x41728c CBZ	X25, 417354

    (285) 0x417290 LDR	D31, [X27, X24,LSL #3]

    (285) 0x417294 LDR	D23, [X25, #8]

    (285) 0x417298 FCMPE	D31, D23

    (285) 0x41729c B.GE	417354

    (285) 0x4172a0 LDR	D30, [X25, #568]

    (285) 0x4172a4 ADD	X0, SP, #184

    (285) 0x4172a8 STR	X10, [SP, #168]

    (285) 0x4172ac FMUL	D0, D31, D30

    (285) 0x4172b0 BL	403d10

    (285) 0x4172b4 FMUL	D4, D0, D0

    (285) 0x4172b8 LDP	D1, D29, [X25, #24]

    (285) 0x4172bc LDP	D19, D3, [X25, #88]

    (285) 0x4172c0 LDP	D25, D2, [X25, #40]

    (285) 0x4172c4 LDP	D21, D24, [X25, #104]

    (285) 0x4172c8 FMUL	D27, D4, D0

    (285) 0x4172cc FMUL	D28, D4, D29

    (285) 0x4172d0 LDP	D7, D8, [X25, #56]

    (285) 0x4172d4 FMUL	D6, D4, D3

    (285) 0x4172d8 LDP	D10, D20, [X25, #120]

    (285) 0x4172dc FMADD	D5, D0, D25, D2

    (285) 0x4172e0 FMADD	D12, D27, D1, D28

    (285) 0x4172e4 LDR	D23, [SP, #184]

    (285) 0x4172e8 FMADD	D9, D0, D21, D24

    (285) 0x4172ec FMADD	D17, D27, D19, D6

    (285) 0x4172f0 LDP	D13, D16, [X25, #72]

    (285) 0x4172f4 FMUL	D26, D4, D8

    (285) 0x4172f8 LDP	D25, D2, [X25, #136]

    (285) 0x4172fc FMUL	D11, D4, D20

    (285) 0x417300 FCVTZS	W0, D23

    (285) 0x417304 LDR	X3, [X25, #536]

    (285) 0x417308 FMADD	D18, D27, D7, D26

    (285) 0x41730c FMADD	D22, D0, D13, D16

    (285) 0x417310 LDR	X10, [SP, #168]

    (285) 0x417314 FMADD	D30, D27, D10, D11

    (285) 0x417318 FADD	D1, D12, D5

    (285) 0x41731c FMADD	D0, D0, D25, D2

    (285) 0x417320 FADD	D31, D17, D9

    (285) 0x417324 SBFM	X4, X0, #61, #31

    (285) 0x417328 ADD	X2, X3, X4

    (285) 0x41732c LDR	D19, [X3, X4]

    (285) 0x417330 LDP	D3, D4, [X2, #8]

    (285) 0x417334 LDR	D28, [X2, #24]

    (285) 0x417338 FADD	D29, D18, D22

    (285) 0x41733c FADD	D21, D0, D30

    (285) 0x417340 FMADD	D14, D19, D1, D14

    (285) 0x417344 FMUL	D5, D31, D4

    (285) 0x417348 FMADD	D27, D28, D21, D14

    (285) 0x41734c FMADD	D24, D3, D29, D5

    (285) 0x417350 FADD	D14, D24, D27

    (285) 0x417354 ADD	X24, X24, #1

    (285) 0x417358 CMP	X28, X24

    (285) 0x41735c B.NE	4171b0

  (279) 0x417360 FSUB	D15, D15, S14

  (279) 0x417364 B	417058

0x417368 HINT	#0

0x41736c HINT	#0

0x417370 HINT	#0

0x417374 HINT	#0

0x417378 HINT	#0

0x41737c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1131
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/shared_ptr_base.h:1667

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.50 to 1.87 cycles (2.93x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50
cycles	0.50	0.50	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Overall L1	5.50

Vectorization ratios

all	40%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

3% of peak load performance is reached (2.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
63% of peak store performance is reached (30.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 416b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X23, X0, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 417098 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:993,1131
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/shared_ptr_base.h:1667

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50
cycles	0.50	0.50	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Overall L1	5.50

Vectorization ratios

all	40%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

3% of peak load performance is reached (2.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
63% of peak store performance is reached (30.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 416b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X23, X0, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 417098 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	0.05	0.08
▼Loop 284 - OneBodyJastrowRef.h:134-155 - exec–	0	0.01
▼Loop 279 - BsplineFunctor.h:166-260 - exec–	0	0
▼Loop 281 - OneBodyJastrowRef.h:134-146 - exec–	0.01	0.02
▼Loop 280 - OneBodyJastrowRef.h:143-146 - exec–	0.01	0.01
○Loop 282 - BsplineFunctor.h:236-241 - exec	0.03	0.04
○Loop 283 - BsplineFunctor.h:246-260 - exec	0	0.01
○Loop 285 - OneBodyJastrowRef.h:151-155 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code