OV - exec - Function qmcplusplus::Vector<double, qmcplusplus::OMPallocator<double, qmcplusplus::Mallocator<double, 32ul>

	Function: qmcplusplus::Vector<double, qmcplusplus::OMPallocator<double, qmcplusplus::Mallocator<doub ...	Module: exec	Source: OhmmsVector.h:181-301 [...]	Coverage: 0.09%

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPallocator.hpp: 85 - 112

--------------------------------------------------------------------------------

85:     value_type* pt = HostAllocator::allocate(n);

[...]

93:     device_ptr_ = getOffloadDevicePtr(pt);

94: #endif

95:     OMPallocator_device_mem_allocated += n * sizeof(T);

[...]

111:     HostAllocator::deallocate(pt, n);

112:   }

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/atomic_base.h: 414 - 422

--------------------------------------------------------------------------------

414:       { return __atomic_add_fetch(&_M_i, __i, int(memory_order_seq_cst)); }

[...]

422:       { return __atomic_sub_fetch(&_M_i, __i, int(memory_order_seq_cst)); }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 181 - 301

--------------------------------------------------------------------------------

181:   inline void resize(size_t n, Type_t val = Type_t())

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

200:   }

[...]

294:   inline void resize_impl(size_t n)

295:   {

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 951 - 1151

--------------------------------------------------------------------------------

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

[...]

1151:       std::__fill_a(__first, __first + __n, __value);

0x504b00 STP	X29, X30, [SP, #976]!

0x504b04 ADD	X29, SP, #0

0x504b08 STP	X19, X20, [SP, #16]

0x504b0c ORR	X20, XZR, X1

0x504b10 LDP	X3, X1, [X0, #8]

0x504b14 CMP	X3, X1

0x504b18 B.HI	504d9c

0x504b1c STR	D15, [SP, #40]

0x504b20 ORR	X19, XZR, X0

0x504b24 FMOV	D15, D0

0x504b28 CMP	X1, X20

0x504b2c B.CC	504c50

0x504b30 CMP	X3, X20

0x504b34 B.CS	504c3c

0x504b38 LDR	X0, [X0, #24]

0x504b3c SUB	X5, X20, X3

0x504b40 ADD	X30, X0, X3,LSL #3

0x504b44 ADD	X7, X30, X5,LSL #3

0x504b48 CMP	X30, X7

0x504b4c B.EQ	504c3c

0x504b50 SUB	X1, X7, X30

0x504b54 CNTW	X8, ALL

0x504b58 SUB	X4, X1, #8

0x504b5c ADD	X2, X8, #4

0x504b60 UBFM	X9, X4, #3, #63

0x504b64 ADD	X6, X9, #1

0x504b68 CMP	X9, X2

0x504b6c B.CC	504ba8

0x504b70 ADDPL	X10, X9, #62

0x504b74 MOVZ	X12, #0

0x504b78 DUP	Z31.D, Z0.D[0]

0x504b7c ADD	X10, X10, #1

0x504b80 ADDVL	X11, X30, #1

0x504b84 PTRUE	P7.B, ALL

(3594) 0x504b88 ST1D	{Z31.D}, P7, [X30, X12,LSL #3]

(3594) 0x504b8c ST1D	{Z31.D}, P7, [X11, X12,LSL #3]

(3594) 0x504b90 ADD	X12, X12, X8

(3594) 0x504b94 CMP	X10, X12

(3594) 0x504b98 B.CS	504b88

0x504b9c ADD	X30, X30, X12,LSL #3

0x504ba0 CMP	X6, X12

0x504ba4 B.EQ	504c3c

0x504ba8 SUB	X13, X7, X30

0x504bac SUB	X14, X13, #8

0x504bb0 UBFM	X15, X14, #3, #63

0x504bb4 ADD	X16, X15, #1

0x504bb8 ANDS	X17, X16, #4224

0x504bbc B.EQ	504c14

0x504bc0 CMP	X17, #1

0x504bc4 B.EQ	504c08

0x504bc8 CMP	X17, #2

0x504bcc B.EQ	504c04

0x504bd0 CMP	X17, #3

0x504bd4 B.EQ	504c00

0x504bd8 CMP	X17, #4

0x504bdc B.EQ	504bfc

0x504be0 CMP	X17, #5

0x504be4 B.EQ	504bf8

0x504be8 CMP	X17, #6

0x504bec B.EQ	504bf4

0x504bf0 STR	D15, [X30], #8

0x504bf4 STR	D15, [X30], #8

0x504bf8 STR	D15, [X30], #8

0x504bfc STR	D15, [X30], #8

0x504c00 STR	D15, [X30], #8

0x504c04 STR	D15, [X30], #8

0x504c08 STR	D15, [X30], #8

0x504c0c CMP	X7, X30

0x504c10 B.EQ	504c3c

(3593) 0x504c14 ORR	X18, XZR, X30

(3593) 0x504c18 ADD	X30, X30, #64

(3593) 0x504c1c STR	D15, [X18], #8

(3593) 0x504c20 STUR	D15, [X30, #456]

(3593) 0x504c24 STR	D15, [X18, #8]

(3593) 0x504c28 STP	D15, D15, [X30, #984]

(3593) 0x504c2c STP	D15, D15, [X30, #1000]

(3593) 0x504c30 STUR	D15, [X30, #504]

(3593) 0x504c34 CMP	X7, X30

(3593) 0x504c38 B.NE	504c14

0x504c3c LDR	D15, [SP, #40]

0x504c40 STR	X20, [X19, #8]

0x504c44 LDP	X19, X20, [SP, #16]

0x504c48 LDP	X29, X30, [SP], #48

0x504c4c RET

0x504c50 STR	X21, [SP, #32]

0x504c54 ADRP	X21,

0x504c58 ADD	X21, X21, #3432

0x504c5c CBNZ	X1, 504d88

(3590) 0x504c60 ORR	X0, XZR, X20

(3590) 0x504c64 BL	4e9760

(3590) 0x504c68 STR	X0, [X19, #32]

(3590) 0x504c6c UBFM	X5, X20, #61, #60

(3590) 0x504c70 ORR	X2, XZR, X0

(3590) 0x504c74 LDADDAL	X5, X0, [X21]

(3590) 0x504c78 ADD	X7, X2, X5

(3590) 0x504c7c STP	X20, X20, [X19, #8]

(3590) 0x504c80 STR	X2, [X19, #24]

(3590) 0x504c84 CMP	X7, X2

(3590) 0x504c88 B.EQ	504d74

(3590) 0x504c8c UBFM	X20, X5, #3, #63

(3590) 0x504c90 CNTW	X19, ALL

(3590) 0x504c94 SUB	X0, X20, #1

(3590) 0x504c98 ADD	X1, X19, #4

(3590) 0x504c9c CMP	X0, X1

(3590) 0x504ca0 B.CC	504ce0

(3590) 0x504ca4 MOVZ	X9, #0

(3590) 0x504ca8 SUB	X8, X20, X19

(3590) 0x504cac DUP	Z0.D, Z15.D[0]

(3590) 0x504cb0 ADDVL	X4, X2, #1

(3590) 0x504cb4 PTRUE	P0.B, ALL

(3590) 0x504cb8 HINT	#0

(3590) 0x504cbc HINT	#0

  (3592) 0x504cc0 ST1D	{Z0.D}, P0, [X2, X9,LSL #3]

  (3592) 0x504cc4 ST1D	{Z0.D}, P0, [X4, X9,LSL #3]

  (3592) 0x504cc8 ADD	X9, X9, X19

  (3592) 0x504ccc CMP	X8, X9

  (3592) 0x504cd0 B.CS	504cc0

(3590) 0x504cd4 ADD	X2, X2, X9,LSL #3

(3590) 0x504cd8 CMP	X9, X20

(3590) 0x504cdc B.EQ	504d74

(3590) 0x504ce0 SUB	X6, X7, X2

(3590) 0x504ce4 SUB	X10, X6, #8

(3590) 0x504ce8 UBFM	X11, X10, #3, #63

(3590) 0x504cec ADD	X12, X11, #1

(3590) 0x504cf0 ANDS	X13, X12, #4224

(3590) 0x504cf4 B.EQ	504d4c

(3590) 0x504cf8 CMP	X13, #1

(3590) 0x504cfc B.EQ	504d40

(3590) 0x504d00 CMP	X13, #2

(3590) 0x504d04 B.EQ	504d3c

(3590) 0x504d08 CMP	X13, #3

(3590) 0x504d0c B.EQ	504d38

(3590) 0x504d10 CMP	X13, #4

(3590) 0x504d14 B.EQ	504d34

(3590) 0x504d18 CMP	X13, #5

(3590) 0x504d1c B.EQ	504d30

(3590) 0x504d20 CMP	X13, #6

(3590) 0x504d24 B.EQ	504d2c

(3590) 0x504d28 STR	D15, [X2], #8

(3590) 0x504d2c STR	D15, [X2], #8

(3590) 0x504d30 STR	D15, [X2], #8

(3590) 0x504d34 STR	D15, [X2], #8

(3590) 0x504d38 STR	D15, [X2], #8

(3590) 0x504d3c STR	D15, [X2], #8

(3590) 0x504d40 STR	D15, [X2], #8

(3590) 0x504d44 CMP	X7, X2

(3590) 0x504d48 B.EQ	504d74

  (3591) 0x504d4c ORR	X14, XZR, X2

  (3591) 0x504d50 ADD	X2, X2, #64

  (3591) 0x504d54 STR	D15, [X14], #8

  (3591) 0x504d58 STUR	D15, [X2, #456]

  (3591) 0x504d5c STR	D15, [X14, #8]

  (3591) 0x504d60 STP	D15, D15, [X2, #984]

  (3591) 0x504d64 STP	D15, D15, [X2, #1000]

  (3591) 0x504d68 STUR	D15, [X2, #504]

  (3591) 0x504d6c CMP	X7, X2

  (3591) 0x504d70 B.NE	504d4c

(3590) 0x504d74 LDR	X21, [SP, #32]

(3590) 0x504d78 LDP	X19, X20, [SP, #16]

(3590) 0x504d7c LDR	D15, [SP, #40]

(3590) 0x504d80 LDP	X29, X30, [SP], #48

(3590) 0x504d84 RET

(3590) 0x504d88 LDR	X0, [X0, #24]

(3590) 0x504d8c SUB	X3, XZR, X1,LSL #3

(3590) 0x504d90 LDADDAL	X3, X2, [X21]

(3590) 0x504d94 BL	4e9680

(3590) 0x504d98 B	504c60

0x504d9c MOVZ	X0, #16

0x504da0 BL	404030

0x504da4 ADRP	X15,

0x504da8 ORR	X19, XZR, X0

0x504dac ADD	X1, X15, #3768

0x504db0 BL	403c00

0x504db4 ADRP	X16,

0x504db8 ADRP	X17,

0x504dbc STR	X21, [SP, #32]

0x504dc0 ORR	X0, XZR, X19

0x504dc4 ADD	X2, X16, #2656

0x504dc8 STR	D15, [SP, #40]

0x504dcc ADD	X1, X17, #2752

0x504dd0 BL	4040a0

0x504dd4 ORR	X18, XZR, X0

0x504dd8 ORR	X0, XZR, X19

0x504ddc STR	X21, [SP, #32]

0x504de0 ORR	X20, XZR, X18

0x504de4 STR	D15, [SP, #40]

0x504de8 BL	403fe0

0x504dec ORR	X0, XZR, X20

0x504df0 BL	403e10

0x504df4 HINT	#0

0x504df8 HINT	#0

0x504dfc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	OhmmsVector.h:181-301
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPallocator.hpp:85,93-95,111-112
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/atomic_base.h:414,422
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:181-188,195-200,294-301
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:951-952,1151

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 5.50 cycles (2.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.25 to 10.50 cycles (1.36x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.25 to 2.50 cycles (5.70x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	14.25	14.25	14.25	14.25	5.50	5.50	0.50	0.50	8.00	8.00	5.00	3.00	3.00
cycles	10.50	10.50	14.25	14.25	14.25	14.25	5.50	5.50	0.50	0.50	8.00	8.00	5.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	14.25

Vectorization ratios

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.25 cycles. At this rate:

4% of peak load performance is reached (4.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 504b00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 504d9c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CMP X1, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 504c50 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X0, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X30, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X30, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X1, X7, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X4, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X4, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 504ba8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDPL X10, X9, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z31.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X11, X30, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X30, X30, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X7, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X14, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X17, X16, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c14 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c08 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c04 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c00 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504bfc <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504bf8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504bf4 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X7, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X20, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X21, <562c54>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, #3432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X1, 504d88 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404030 <@plt_start@+0x640>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X15, <52cda4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X15, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c00 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X16, <200403db4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X17, <560db8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X16, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X1, X17, #2752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4040a0 <@plt_start@+0x6b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 403fe0 <@plt_start@+0x5f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	OhmmsVector.h:181-301
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPallocator.hpp:85,93-95,111-112
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/atomic_base.h:414,422
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:181-188,195-200,294-301
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:951-952,1151

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 5.50 cycles (2.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.25 to 2.50 cycles (5.70x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	14.25	14.25	14.25	14.25	5.50	5.50	0.50	0.50	8.00	8.00	5.00	3.00	3.00
cycles	10.50	10.50	14.25	14.25	14.25	14.25	5.50	5.50	0.50	0.50	8.00	8.00	5.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	14.25

Vectorization ratios

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.25 cycles. At this rate:

4% of peak load performance is reached (4.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 504b00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 504d9c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CMP X1, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 504c50 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X0, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X30, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X30, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X1, X7, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X4, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X4, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 504ba8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDPL X10, X9, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z31.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X11, X30, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X30, X30, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X7, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X14, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X17, X16, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c14 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c08 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c04 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c00 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504bfc <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504bf8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504bf4 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D15, [X30], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X7, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 504c3c <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X20, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X21, <562c54>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, #3432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X1, 504d88 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404030 <@plt_start@+0x640>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X15, <52cda4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X15, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c00 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X16, <200403db4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X17, <560db8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X16, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X1, X17, #2752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4040a0 <@plt_start@+0x6b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 403fe0 <@plt_start@+0x5f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e10 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::Vector > >::resize(unsigned long, double)–	0.09	0.15
○Loop 3593 - stl_algobase.h:951-952 - exec	0	0
▼Loop 3590 - OMPallocator.hpp:85-112 - exec–	0	0
○Loop 3592 - stl_algobase.h:951-952 - exec	0.09	0.13
○Loop 3591 - stl_algobase.h:951-952 - exec	0	0
○Loop 3594 - stl_algobase.h:951-952 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code