OV - exec - Loop 948

	Loop Id: 948	Module: exec	Source: MultiBsplineRef.hpp:233-270 [...]	Coverage: 0.01%

0x432520 LDR	X4, [SP, #304]

0x432524 LDP	X13, X18, [SP, #352]

0x432528 LDP	X16, X1, [SP, #336]

0x43252c LDP	X26, X30, [SP, #320]

  (945) 0x432530 LDR	X9, [SP, #312]

  (945) 0x432534 ADD	X18, X18, #1

  (945) 0x432538 CMP	X18, #4

  (945) 0x43253c ADD	X13, X13, X9

  (945) 0x432540 ADD	X1, X1, X9

  (945) 0x432544 ADD	X16, X16, X9

  (945) 0x432548 ADD	X30, X30, X9

  (945) 0x43254c ADD	X26, X26, X9

  (945) 0x432550 B.EQ	4328ac

  (945) 0x432554 CMP	W4, #1

  (945) 0x432558 B.LT	432530

0x43255c SUB	X9, X29, #240

0x432560 ORR	X7, XZR, XZR

0x432564 ORR	X15, XZR, X1

0x432568 STP	X26, X30, [SP, #320]

0x43256c STP	X13, X18, [SP, #352]

0x432570 STP	X16, X1, [SP, #336]

0x432574 ORR	X14, XZR, X13

0x432578 LDR	D0, [X9, X18,LSL #3]

0x43257c SUB	X9, X29, #176

0x432580 LDR	D2, [X9, X18,LSL #3]

0x432584 SUB	X9, X29, #112

0x432588 LDR	D26, [X9, X18,LSL #3]

0x43258c STP	D2, D0, [SP, #384]

0x432590 STR	D26, [SP, #376]

0x432594 B	4325c0

0x4325a0 ADD	X7, X7, #1

0x4325a4 ADD	X14, X14, X12

0x4325a8 ADD	X15, X15, X12

0x4325ac CMP	X7, #4

0x4325b0 ADD	X16, X16, X12

0x4325b4 ADD	X30, X30, X12

0x4325b8 ADD	X26, X26, X12

0x4325bc B.EQ	432520

0x4325c0 SUB	X9, X29, #144

0x4325c4 LDR	D16, [X6, X7,LSL #3]

0x4325c8 CMP	X8, #4

0x4325cc LDR	D5, [X9, X7,LSL #3]

0x4325d0 SUB	X9, X29, #208

0x4325d4 LDR	D7, [X9, X7,LSL #3]

0x4325d8 FMUL	D16, D16, D26

0x4325dc FMUL	D3, D5, D0

0x4325e0 FMUL	D4, D2, D5

0x4325e4 FMUL	D5, D26, D5

0x4325e8 FMUL	D6, D7, D2

0x4325ec FMUL	D7, D7, D26

0x4325f0 B.CS	432600

0x4325f4 ORR	X10, XZR, XZR

0x4325f8 B	432798

0x432798 UBFM	X9, X10, #61, #60

0x43279c ORR	X13, XZR, XZR

0x4327a0 SUB	X10, X8, X10

0x4327a4 ADD	X2, X26, X9

0x4327a8 ADD	X21, X15, X9

0x4327ac ADD	X11, X16, X9

0x4327b0 ADD	X1, X30, X9

0x4327b4 ADD	X25, X20, X9

0x4327b8 ADD	X28, X19, X9

0x4327bc ADD	X17, X23, X9

0x4327c0 ADD	X18, X0, X9

0x4327c4 ADD	X9, X22, X9

  (947) 0x4327c8 UBFM	X4, X13, #61, #60

  (947) 0x4327cc ADD	X13, X13, #1

  (947) 0x4327d0 LDR	D17, [X2, X4]

  (947) 0x4327d4 LDR	D18, [X21, X4]

  (947) 0x4327d8 LDR	D19, [X11, X4]

  (947) 0x4327dc LDR	D20, [X1, X4]

  (947) 0x4327e0 ADD	X5, X25, X4

  (947) 0x4327e4 CMP	X10, X13

  (947) 0x4327e8 FMUL	D21, D17, D11

  (947) 0x4327ec FMUL	D22, D17, D31

  (947) 0x4327f0 FMUL	D23, D18, D30

  (947) 0x4327f4 FMUL	D17, D17, D25

  (947) 0x4327f8 FMADD	D21, D18, D13, D21

  (947) 0x4327fc FMADD	D23, D12, D20, D23

  (947) 0x432800 FMADD	D22, D19, D9, D22

  (947) 0x432804 FMADD	D17, D18, D8, D17

  (947) 0x432808 FMADD	D21, D19, D14, D21

  (947) 0x43280c FMADD	D22, D23, D10, D22

  (947) 0x432810 LDR	D23, [X5]

  (947) 0x432814 FMADD	D17, D19, D1, D17

  (947) 0x432818 LDR	D19, [X28, X4]

  (947) 0x43281c FMADD	D21, D15, D20, D21

  (947) 0x432820 FMADD	D17, D20, D10, D17

  (947) 0x432824 FMADD	D23, D3, D21, D23

  (947) 0x432828 FMADD	D19, D21, D4, D19

  (947) 0x43282c STR	D23, [X5]

  (947) 0x432830 ADD	X5, X5, X27

  (947) 0x432834 STR	D19, [X28, X4]

  (947) 0x432838 LDR	D19, [X17, X4]

  (947) 0x43283c LDR	D23, [X5]

  (947) 0x432840 FMADD	D19, D21, D7, D19

  (947) 0x432844 FMADD	D23, D6, D21, D23

  (947) 0x432848 STR	D19, [X17, X4]

  (947) 0x43284c STR	D23, [X5]

  (947) 0x432850 ADD	X5, X5, X27

  (947) 0x432854 LDR	D19, [X18, X4]

  (947) 0x432858 LDR	D18, [X5]

  (947) 0x43285c FMADD	D19, D22, D5, D19

  (947) 0x432860 FMADD	D18, D22, D4, D18

  (947) 0x432864 STR	D19, [X18, X4]

  (947) 0x432868 STR	D18, [X5]

  (947) 0x43286c ADD	X5, X5, X27

  (947) 0x432870 LDR	D18, [X5]

  (947) 0x432874 FMADD	D18, D16, D21, D18

  (947) 0x432878 STR	D18, [X5]

  (947) 0x43287c ADD	X5, X5, X27

  (947) 0x432880 LDR	D18, [X5]

  (947) 0x432884 FMADD	D18, D22, D7, D18

  (947) 0x432888 STR	D18, [X5]

  (947) 0x43288c LDR	D18, [X5, X27]

  (947) 0x432890 FMADD	D17, D17, D5, D18

  (947) 0x432894 LDR	D18, [X9, X4]

  (947) 0x432898 STR	D17, [X5, X27]

  (947) 0x43289c FMADD	D18, D21, D5, D18

  (947) 0x4328a0 STR	D18, [X9, X4]

  (947) 0x4328a4 B.NE	4327c8

0x4328a8 B	4325a0

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 233 - 270

--------------------------------------------------------------------------------

233:   for (int i = 0; i < 4; i++)

234:     for (int j = 0; j < 4; j++)

[...]

241:       const T pre20 = d2a[i] * b[j];

242:       const T pre10 = da[i] * b[j];

243:       const T pre00 = a[i] * b[j];

244:       const T pre11 = da[i] * db[j];

245:       const T pre01 = a[i] * db[j];

246:       const T pre02 = a[i] * d2b[j];

247:

248:       const int iSplitPoint = num_splines;

249: #pragma omp simd aligned(coefs, coefszs, coefs2zs, coefs3zs: QMC_SIMD_ALIGNMENT) simdlen(simdlen_)

250:       for (int n = 0; n < iSplitPoint; n++)

251:       {

252:         T coefsv    = coefs[n];

253:         T coefsvzs  = coefszs[n];

254:         T coefsv2zs = coefs2zs[n];

255:         T coefsv3zs = coefs3zs[n];

256:

257:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

258:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

259:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

260:

261:         hxx[n] += pre20 * sum0;

262:         hxy[n] += pre11 * sum0;

263:         hxz[n] += pre10 * sum1;

264:         hyy[n] += pre02 * sum0;

265:         hyz[n] += pre01 * sum1;

266:         hzz[n] += pre00 * sum2;

267:         gx[n] += pre10 * sum0;

268:         gy[n] += pre01 * sum0;

269:         gz[n] += pre00 * sum1;

270:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.72
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P4, P5,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:233-234,MultiBsplineRef.hpp:241-246,MultiBsplineRef.hpp:249-249
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	1.81
Front-end cycles	6.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	5.17
P10 cycles	4.83
P11 cycles	5.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.83
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.28
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.70
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.93
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.72
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P4, P5,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:233-234,MultiBsplineRef.hpp:241-246,MultiBsplineRef.hpp:249-249
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	1.81
Front-end cycles	6.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	5.17
P10 cycles	4.83
P11 cycles	5.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.83
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.28
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.70
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.93
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:233-270
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:233-234,241-270.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:233-234,241-246,249.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 2.67 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.25 to 1.81 cycles (4.00x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 104 bytes. The binary loop is storing 72 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	2.00	2.00	2.00	2.00	5.17	4.83	5.00	1.50	1.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	2.00	2.00	2.00	2.00	5.17	4.83	5.00	1.50	1.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Overall L1	7.25

Vectorization ratios

all	3%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

14% of peak load performance is reached (14.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.93 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4325a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X4, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X1, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X30, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X9, X29, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X26, X30, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X16, X1, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X14, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X9, X29, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X9, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D26, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STP D2, D0, [SP, #384]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D26, [SP, #376]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4325c0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 432520 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X9, X29, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X6, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D5, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X9, X29, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D16, D16, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D3, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D4, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D5, D26, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D6, D7, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D7, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
B.CS 432600 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 432798 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x978>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X26, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4325a0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:233-270
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 2.67 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 104 bytes. The binary loop is storing 72 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	2.00	2.00	2.00	2.00	5.17	4.83	5.00	1.50	1.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	2.00	2.00	2.00	2.00	5.17	4.83	5.00	1.50	1.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Overall L1	7.25

Vectorization ratios

all	3%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

14% of peak load performance is reached (14.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.93 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4325a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X4, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X1, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X30, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X9, X29, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X26, X30, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X16, X1, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X14, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X9, X29, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X9, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D26, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STP D2, D0, [SP, #384]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D26, [SP, #376]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4325c0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 432520 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X9, X29, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X6, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D5, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X9, X29, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D16, D16, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D3, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D4, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D5, D26, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D6, D7, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D7, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
B.CS 432600 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 432798 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x978>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X26, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4325a0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code