OV - exec - Loop 944

	Loop Id: 944	Module: exec	Source: MultiBsplineRef.hpp:250-270	Coverage: 19.33%

0x43260c ADD	X9, X14, X2

0x432610 ORR	V2.16B, V1.16B, V1.16B

0x432614 ORR	V1.16B, V8.16B, V8.16B

0x432618 ADD	X10, X19, X2

0x43261c SUBS	X13, X13, #4

0x432620 LDP	Q25, Q28, [X9]    [1]

0x432624 ADD	X9, X15, X2

0x432628 ORR	V8.16B, V30.16B, V30.16B

0x43262c LDP	Q24, Q27, [X9]    [13]

0x432630 ADD	X9, X16, X2

0x432634 LDP	Q26, Q23, [X9]    [7]

0x432638 ADD	X9, X30, X2

0x43263c FMUL	V17.2D, V28.2D, V11.D[0]

0x432640 FMUL	V19.2D, V28.2D, V31.D[0]

0x432644 FMUL	V28.2D, V28.2D, V0.D[0]

0x432648 LDP	Q22, Q21, [X9]    [4]

0x43264c FMUL	V18.2D, V25.2D, V11.D[0]

0x432650 FMUL	V20.2D, V25.2D, V31.D[0]

0x432654 ADD	X9, X20, X2

0x432658 FMUL	V25.2D, V25.2D, V0.D[0]

0x43265c FMLA	V17.2D, V27.2D, V13.D[0]

0x432660 FMUL	V29.2D, V24.2D, V30.D[0]

0x432664 FMUL	V30.2D, V27.2D, V30.D[0]

0x432668 FMLA	V19.2D, V23.2D, V9.D[0]

0x43266c FMLA	V18.2D, V24.2D, V13.D[0]

0x432670 FMLA	V20.2D, V26.2D, V9.D[0]

0x432674 FMLA	V30.2D, V21.2D, V12.D[0]

0x432678 FMLA	V17.2D, V23.2D, V14.D[0]

0x43267c FMLA	V29.2D, V22.2D, V12.D[0]

0x432680 FMLA	V18.2D, V26.2D, V14.D[0]

0x432684 FMLA	V19.2D, V30.2D, V10.D[0]

0x432688 FMLA	V17.2D, V21.2D, V15.D[0]

0x43268c FMLA	V20.2D, V29.2D, V10.D[0]

0x432690 LDP	Q29, Q30, [X9]    [14]

0x432694 FMLA	V18.2D, V22.2D, V15.D[0]

0x432698 FMLA	V30.2D, V17.2D, V3.D[0]

0x43269c FMLA	V29.2D, V18.2D, V3.D[0]

0x4326a0 STP	Q29, Q30, [X9]    [14]

0x4326a4 ADD	X9, X9, X27

0x4326a8 LDP	Q29, Q30, [X9]    [5]

0x4326ac FMLA	V30.2D, V17.2D, V6.D[0]

0x4326b0 FMLA	V29.2D, V18.2D, V6.D[0]

0x4326b4 STP	Q29, Q30, [X9]    [5]

0x4326b8 ADD	X9, X9, X27

0x4326bc LDP	Q29, Q30, [X9]    [3]

0x4326c0 FMLA	V30.2D, V19.2D, V4.D[0]

0x4326c4 FMLA	V29.2D, V20.2D, V4.D[0]

0x4326c8 STP	Q29, Q30, [X9]    [3]

0x4326cc ORR	V30.16B, V8.16B, V8.16B

0x4326d0 ORR	V8.16B, V1.16B, V1.16B

0x4326d4 ADD	X9, X9, X27

0x4326d8 ORR	V1.16B, V2.16B, V2.16B

0x4326dc FMLA	V28.2D, V27.2D, V8.D[0]

0x4326e0 LDP	Q27, Q29, [X9]    [11]

0x4326e4 FMLA	V25.2D, V24.2D, V8.D[0]

0x4326e8 FMLA	V29.2D, V17.2D, V16.D[0]

0x4326ec FMLA	V25.2D, V26.2D, V2.D[0]

0x4326f0 FMLA	V28.2D, V23.2D, V2.D[0]

0x4326f4 FMLA	V27.2D, V18.2D, V16.D[0]

0x4326f8 FMLA	V28.2D, V21.2D, V10.D[0]

0x4326fc FMLA	V25.2D, V22.2D, V10.D[0]

0x432700 STP	Q27, Q29, [X9]    [11]

0x432704 ADD	X9, X9, X27

0x432708 LDP	Q29, Q27, [X10]    [10]

0x43270c LDP	Q24, Q26, [X9]    [12]

0x432710 FMLA	V27.2D, V17.2D, V4.D[0]

0x432714 FMLA	V29.2D, V18.2D, V4.D[0]

0x432718 FMLA	V26.2D, V19.2D, V7.D[0]

0x43271c FMLA	V24.2D, V20.2D, V7.D[0]

0x432720 STP	Q29, Q27, [X10]    [10]

0x432724 ADD	X10, X23, X2

0x432728 STP	Q24, Q26, [X9]    [12]

0x43272c LDP	Q23, Q24, [X10]    [8]

0x432730 ADD	X9, X9, X27

0x432734 FMLA	V24.2D, V17.2D, V7.D[0]

0x432738 FMLA	V23.2D, V18.2D, V7.D[0]

0x43273c STP	Q23, Q24, [X10]    [8]

0x432740 ADD	X10, X22, X2

0x432744 LDP	Q22, Q21, [X10]    [2]

0x432748 FMLA	V21.2D, V17.2D, V5.D[0]

0x43274c FMLA	V22.2D, V18.2D, V5.D[0]

0x432750 STP	Q22, Q21, [X10]    [2]

0x432754 ADD	X10, X24, X2

0x432758 ADD	X2, X2, #32

0x43275c LDP	Q17, Q18, [X10]    [9]

0x432760 FMLA	V18.2D, V19.2D, V5.D[0]

0x432764 FMLA	V17.2D, V20.2D, V5.D[0]

0x432768 STP	Q17, Q18, [X10]    [9]

0x43276c LDP	Q17, Q18, [X9]    [6]

0x432770 FMLA	V18.2D, V28.2D, V5.D[0]

0x432774 FMLA	V17.2D, V25.2D, V5.D[0]

0x432778 STP	Q17, Q18, [X9]    [6]

0x43277c B.NE	43260c

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 250 - 270

--------------------------------------------------------------------------------

250:       for (int n = 0; n < iSplitPoint; n++)

251:       {

252:         T coefsv    = coefs[n];

253:         T coefsvzs  = coefszs[n];

254:         T coefsv2zs = coefs2zs[n];

255:         T coefsv3zs = coefs3zs[n];

256:

257:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

258:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

259:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

260:

261:         hxx[n] += pre20 * sum0;

262:         hxy[n] += pre11 * sum0;

263:         hxz[n] += pre10 * sum1;

264:         hyy[n] += pre02 * sum0;

265:         hyz[n] += pre01 * sum1;

266:         hzz[n] += pre00 * sum2;

267:         gx[n] += pre10 * sum0;

268:         gy[n] += pre01 * sum0;

269:         gz[n] += pre00 * sum1;

270:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►91.30+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so
►4.35+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:210	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	.omp_outlined.	miniqmc.cpp:375	exec
○	__kmp_invoke_microtask		libomp.so
►4.35+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:210	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	.omp_outlined.	miniqmc.cpp:375	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.82
CQA speedup if fully vectorized	1.72
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:250-270
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	15.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	9.00
Front-end cycles	11.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	15.50
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	15.50
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	10.84
Nb FLOP add-sub	0.00
Nb FLOP mul	16.00
Nb FLOP fma	76.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	49.55
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	320.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	98.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	65.26
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.82
CQA speedup if fully vectorized	1.72
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:250-270
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	15.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	9.00
Front-end cycles	11.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	15.50
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	15.50
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	10.84
Nb FLOP add-sub	0.00
Nb FLOP mul	16.00
Nb FLOP fma	76.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	49.55
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	320.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	98.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	65.26
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:250-270
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:250-270.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 65% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 15.50 to 9.00 cycles (1.72x speedup).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 76 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

76: addition or subtraction (all inside FMA instructions)
92: multiply (76 inside FMA instructions)

The binary loop is loading 448 bytes. The binary loop is storing 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	93
loop length	372
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.00	4.00	4.00	4.00	15.50	15.50	15.50	15.50	8.00	8.00	8.00	0.00	0.00
cycles	0.50	0.50	4.00	4.00	4.00	4.00	15.50	15.50	15.50	15.50	8.00	8.00	8.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	11.63
Data deps.	4.00
Overall L1	15.50

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

30% of peak load performance is reached (28.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (20.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43260c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X9, X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V2.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR V1.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X10, X19, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X13, X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP Q25, Q28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X15, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V8.16B, V30.16B, V30.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP Q24, Q27, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q26, Q23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V17.2D, V28.2D, V11.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V19.2D, V28.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V28.2D, V28.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDP Q22, Q21, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V18.2D, V25.2D, V11.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V20.2D, V25.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X9, X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V25.2D, V25.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V17.2D, V27.2D, V13.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL V29.2D, V24.2D, V30.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V30.2D, V27.2D, V30.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V19.2D, V23.2D, V9.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V18.2D, V24.2D, V13.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V20.2D, V26.2D, V9.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V30.2D, V21.2D, V12.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V23.2D, V14.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V22.2D, V12.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V18.2D, V26.2D, V14.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V30.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V21.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V20.2D, V29.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q29, Q30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V18.2D, V22.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V30.2D, V17.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V18.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q30, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q29, Q30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V30.2D, V17.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V18.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q30, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q29, Q30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V30.2D, V19.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V20.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q30, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ORR V30.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR V8.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V1.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMLA V28.2D, V27.2D, V8.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q27, Q29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V25.2D, V24.2D, V8.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V17.2D, V16.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V25.2D, V26.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V28.2D, V23.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V27.2D, V18.2D, V16.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V28.2D, V21.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V25.2D, V22.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q27, Q29, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q29, Q27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
LDP Q24, Q26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V27.2D, V17.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V18.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V26.2D, V19.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V24.2D, V20.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q27, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X10, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP Q24, Q26, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q23, Q24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMLA V24.2D, V17.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V23.2D, V18.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q23, Q24, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X10, X22, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q22, Q21, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V21.2D, V17.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V22.2D, V18.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q22, Q21, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X10, X24, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q17, Q18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V18.2D, V19.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V20.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q17, Q18, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q17, Q18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V18.2D, V28.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V25.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q17, Q18, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 43260c <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:250-270
Module	exec

gain
potential
hint
expert

Vectorization

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 76 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

76: addition or subtraction (all inside FMA instructions)
92: multiply (76 inside FMA instructions)

The binary loop is loading 448 bytes. The binary loop is storing 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	93
loop length	372
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.00	4.00	4.00	4.00	15.50	15.50	15.50	15.50	8.00	8.00	8.00	0.00	0.00
cycles	0.50	0.50	4.00	4.00	4.00	4.00	15.50	15.50	15.50	15.50	8.00	8.00	8.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	11.63
Data deps.	4.00
Overall L1	15.50

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

30% of peak load performance is reached (28.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (20.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43260c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X9, X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V2.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR V1.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X10, X19, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X13, X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP Q25, Q28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X15, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V8.16B, V30.16B, V30.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP Q24, Q27, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q26, Q23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V17.2D, V28.2D, V11.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V19.2D, V28.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V28.2D, V28.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDP Q22, Q21, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V18.2D, V25.2D, V11.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V20.2D, V25.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X9, X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V25.2D, V25.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V17.2D, V27.2D, V13.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL V29.2D, V24.2D, V30.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V30.2D, V27.2D, V30.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V19.2D, V23.2D, V9.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V18.2D, V24.2D, V13.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V20.2D, V26.2D, V9.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V30.2D, V21.2D, V12.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V23.2D, V14.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V22.2D, V12.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V18.2D, V26.2D, V14.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V30.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V21.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V20.2D, V29.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q29, Q30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V18.2D, V22.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V30.2D, V17.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V18.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q30, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q29, Q30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V30.2D, V17.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V18.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q30, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q29, Q30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V30.2D, V19.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V20.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q30, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ORR V30.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR V8.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V1.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMLA V28.2D, V27.2D, V8.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q27, Q29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V25.2D, V24.2D, V8.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V17.2D, V16.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V25.2D, V26.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V28.2D, V23.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V27.2D, V18.2D, V16.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V28.2D, V21.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V25.2D, V22.2D, V10.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q27, Q29, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q29, Q27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
LDP Q24, Q26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V27.2D, V17.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V29.2D, V18.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V26.2D, V19.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V24.2D, V20.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q29, Q27, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X10, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP Q24, Q26, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q23, Q24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMLA V24.2D, V17.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V23.2D, V18.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q23, Q24, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X10, X22, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q22, Q21, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V21.2D, V17.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V22.2D, V18.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q22, Q21, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X10, X24, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q17, Q18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V18.2D, V19.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V20.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q17, Q18, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q17, Q18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V18.2D, V28.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V17.2D, V25.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q17, Q18, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 43260c <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code