OV - exec - Loop 942

	Loop Id: 942	Module: exec	Source: MultiBsplineRef.hpp:285-295	Coverage: 0.33%

0x432904 ADD	X13, X20, X11

0x432908 ADD	X14, X19, X11

0x43290c SUBS	X12, X12, #4

0x432910 LDP	Q6, Q7, [X13]    [5]

0x432914 FMUL	V7.2D, V7.2D, V0.D[0]

0x432918 FMUL	V6.2D, V6.2D, V0.D[0]

0x43291c STP	Q6, Q7, [X13]    [5]

0x432920 ADD	X13, X17, X11

0x432924 LDP	Q6, Q7, [X13]    [7]

0x432928 FMUL	V7.2D, V7.2D, V1.D[0]

0x43292c FMUL	V6.2D, V6.2D, V1.D[0]

0x432930 STP	Q6, Q7, [X13]    [7]

0x432934 ADD	X13, X0, X11

0x432938 LDP	Q6, Q7, [X13]    [2]

0x43293c FMUL	V7.2D, V7.2D, V2.D[0]

0x432940 FMUL	V6.2D, V6.2D, V2.D[0]

0x432944 STP	Q6, Q7, [X13]    [2]

0x432948 LDP	Q6, Q16, [X14]    [1]

0x43294c ADD	X13, X15, X11

0x432950 FMUL	V16.2D, V16.2D, V17.D[0]

0x432954 FMUL	V6.2D, V6.2D, V17.D[0]

0x432958 STP	Q6, Q16, [X14]    [1]

0x43295c LDP	Q6, Q7, [X13]    [9]

0x432960 ADD	X14, X23, X11

0x432964 FMUL	V7.2D, V7.2D, V3.D[0]

0x432968 FMUL	V6.2D, V6.2D, V3.D[0]

0x43296c STP	Q6, Q7, [X13]    [9]

0x432970 LDP	Q6, Q7, [X14]    [8]

0x432974 ADD	X13, X16, X11

0x432978 FMUL	V7.2D, V7.2D, V18.D[0]

0x43297c FMUL	V6.2D, V6.2D, V18.D[0]

0x432980 STP	Q6, Q7, [X14]    [8]

0x432984 LDP	Q6, Q7, [X13]    [4]

0x432988 ADD	X14, X18, X11

0x43298c FMUL	V7.2D, V7.2D, V4.D[0]

0x432990 FMUL	V6.2D, V6.2D, V4.D[0]

0x432994 STP	Q6, Q7, [X13]    [4]

0x432998 ADD	X13, X24, X11

0x43299c ADD	X11, X11, #32

0x4329a0 LDP	Q6, Q7, [X13]    [3]

0x4329a4 FMUL	V7.2D, V7.2D, V19.D[0]

0x4329a8 FMUL	V6.2D, V6.2D, V19.D[0]

0x4329ac STP	Q6, Q7, [X13]    [3]

0x4329b0 LDP	Q6, Q7, [X14]    [6]

0x4329b4 FMUL	V7.2D, V7.2D, V5.D[0]

0x4329b8 FMUL	V6.2D, V6.2D, V5.D[0]

0x4329bc STP	Q6, Q7, [X14]    [6]

0x4329c0 B.NE	432904

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 285 - 295

--------------------------------------------------------------------------------

285:   for (int n = 0; n < num_splines; n++)

286:   {

287:     gx[n] *= dxInv;

288:     gy[n] *= dyInv;

289:     gz[n] *= dzInv;

290:     hxx[n] *= dxx;

291:     hyy[n] *= dyy;

292:     hzz[n] *= dzz;

293:     hxy[n] *= dxy;

294:     hxz[n] *= dxz;

295:     hyz[n] *= dyz;

Coverage (%)	Name	Source Location	Module
►81.82+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so
►12.12+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:210	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	.omp_outlined.	miniqmc.cpp:375	exec
○	__kmp_invoke_microtask		libomp.so
►6.06+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:210	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	.omp_outlined.	miniqmc.cpp:375	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:285-295
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	6.17
Front-end cycles	6.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	6.75
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.17
P10 cycles	5.83
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	36.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	85.33
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	288.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	97.30
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	73.65
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:285-295
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	6.17
Front-end cycles	6.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	6.75
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.17
P10 cycles	5.83
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	36.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	85.33
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	288.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	97.30
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	73.65
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:285-295
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:285-295.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 73% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.75 to 6.17 cycles (1.09x speedup).

Details

97% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

36: multiply

The binary loop is loading 288 bytes. The binary loop is storing 288 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	2.75	2.75	6.75	6.75	6.75	6.75	6.17	5.83	6.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	2.75	2.75	6.75	6.75	6.75	6.75	6.17	5.83	6.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.00
Data deps.	1.00
Overall L1	6.75

Vectorization ratios

INT

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	100%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
88% of peak store performance is reached (42.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 432904

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X13, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X19, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X12, X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X13, X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V16.2D, V16.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q16, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X14, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V7.2D, V7.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X13, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V7.2D, V7.2D, V18.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V18.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X14, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V7.2D, V7.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V19.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V19.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 432904 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:285-295
Module	exec

gain
potential
hint
expert

Vectorization

Details

97% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

36: multiply

The binary loop is loading 288 bytes. The binary loop is storing 288 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	2.75	2.75	6.75	6.75	6.75	6.75	6.17	5.83	6.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	2.75	2.75	6.75	6.75	6.75	6.75	6.17	5.83	6.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.00
Data deps.	1.00
Overall L1	6.75

Vectorization ratios

INT

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	100%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
88% of peak store performance is reached (42.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 432904

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X13, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X19, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X12, X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X13, X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V16.2D, V16.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q16, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X14, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V7.2D, V7.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X13, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V7.2D, V7.2D, V18.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V18.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X14, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V7.2D, V7.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q6, Q7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V19.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V19.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP Q6, Q7, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMUL V7.2D, V7.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V6.2D, V6.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP Q6, Q7, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 432904 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code