OV - exec - Loop 361

0x419340 LD1D	{Z5.D}, P0/Z, [X8, X4,LSL #3]    [7]

0x419344 LD1D	{Z6.D}, P0/Z, [X6, X4,LSL #3]    [10]

0x419348 LD1D	{Z7.D}, P0/Z, [X1, X4,LSL #3]    [6]

0x41934c FMUL	Z5.D, Z7.D, Z5.D

0x419350 LD1D	{Z16.D}, P0/Z, [X7, X4,LSL #3]    [3]

0x419354 FMUL	Z6.D, Z16.D, Z6.D

0x419358 LD1D	{Z7.D}, P0/Z, [X10, X4,LSL #3]    [1]

0x41935c LD1D	{Z16.D}, P0/Z, [X20, X4,LSL #3]    [5]

0x419360 LD1D	{Z17.D}, P0/Z, [X2, X4,LSL #3]    [8]

0x419364 LD1D	{Z18.D}, P0/Z, [X21, X4,LSL #3]    [2]

0x419368 LD1D	{Z19.D}, P0/Z, [X3, X4,LSL #3]    [9]

0x41936c LD1D	{Z20.D}, P0/Z, [X22, X4,LSL #3]    [4]

0x419370 FADD	Z3.D, Z5.D, Z3.D

0x419374 FADD	Z4.D, Z6.D, Z4.D

0x419378 FNMSB	Z7.D, P0/M, Z17.D, Z5.D

0x41937c FNMSB	Z16.D, P0/M, Z18.D, Z6.D

0x419380 FADD	Z7.D, Z7.D, Z19.D

0x419384 FADD	Z16.D, Z16.D, Z20.D

0x419388 ST1D	{Z7.D}, P0, [X3, X4,LSL #3]    [9]

0x41938c ST1D	{Z16.D}, P0, [X22, X4,LSL #3]    [4]

0x419390 ADD	X4, X4, X11

0x419394 CMP	X0, X4

0x419398 B.NE	419340

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 340 - 345

--------------------------------------------------------------------------------

340:     for (int jat = 0; jat < N; jat++)

341:     {

342:       const valT newg = cur_du_pt[jat] * new_dX[jat];

343:       const valT dg   = newg - old_du_pt[jat] * old_dX[jat];

344:       save_g[jat] -= dg;

345:       cur_g += newg;

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	.omp_outlined..62	miniqmc.cpp:445	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:340-345
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	2.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	16.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:340-345
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	2.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	16.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:340-345
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:340-345.

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (8 inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	6.00	6.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.88
Data deps.	2.00
Overall L1	6.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z5.D}, P0/Z, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z5.D, Z7.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z16.D}, P0/Z, [X7, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z7.D}, P0/Z, [X10, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z4.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNMSB Z7.D, P0/M, Z17.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FNMSB Z16.D, P0/M, Z18.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z7.D, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z16.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z7.D}, P0, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z16.D}, P0, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X4, X4, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 419340 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:340-345
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:340-345.

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (8 inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	6.00	6.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.88
Data deps.	2.00
Overall L1	6.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z5.D}, P0/Z, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z5.D, Z7.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z16.D}, P0/Z, [X7, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z7.D}, P0/Z, [X10, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z4.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNMSB Z7.D, P0/M, Z17.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FNMSB Z16.D, P0/M, Z18.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z7.D, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z16.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z7.D}, P0, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z16.D}, P0, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X4, X4, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 419340 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code