OV - exec - Loop 139

0x40cf00 LDR	X8, [X21, #88]    [3]

0x40cf04 LDR	X22, [X8, X23,LSL #3]    [2]

0x40cf08 ORR	X0, XZR, X22

0x40cf0c BL	44ec60

0x40cf10 LDR	X8, [X21, #16]    [3]

0x40cf14 LDR	X0, [X8, X23,LSL #3]    [4]

0x40cf18 LDR	X8, [X0]    [5]

0x40cf1c LDR	X8, [X8, #40]    [1]

0x40cf20 ORR	X1, XZR, X20

0x40cf24 ORR	W2, WZR, W19

0x40cf28 BLR	X8

0x40cf2c ORR	X0, XZR, X22

0x40cf30 BL	44ed80

0x40cf34 LDP	X9, X8, [X21, #16]    [3]

0x40cf38 ADD	X23, X23, #1

0x40cf3c SUB	X8, X8, X9

0x40cf40 CMP	X23, X8,ASR #3

0x40cf44 B.CC	40cf00

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 231 - 234

--------------------------------------------------------------------------------

231:   for (size_t i = 0; i < Jastrows.size(); i++)

232:   {

233:     ScopedTimer local_timer(jastrow_timers[i]);

234:     Jastrows[i]->acceptMove(P, iat);

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

Coverage (%)	Name	Source Location	Module
►100.00+	.omp_outlined..62	miniqmc.cpp:445	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P2, P3, P4, P5,
Function	qmcplusplus::WaveFunction::acceptMove(qmcplusplus::ParticleSet&, int)
Source	stl_vector.h:919-919,stl_vector.h:1046-1046,WaveFunction.cpp:231-234,refwrap.h:338-338,NewTimer.h:242-242,NewTimer.h:249-249
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.34
Front-end cycles	2.25
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.60
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P2, P3, P4, P5,
Function	qmcplusplus::WaveFunction::acceptMove(qmcplusplus::ParticleSet&, int)
Source	stl_vector.h:919-919,stl_vector.h:1046-1046,WaveFunction.cpp:231-234,refwrap.h:338-338,NewTimer.h:242-242,NewTimer.h:249-249
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.34
Front-end cycles	2.25
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.60
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::WaveFunction::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	WaveFunction.cpp:231-234
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:231-234
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.34 cycles (7.27x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.50 to 1.50 cycles (1.67x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

26% of peak load performance is reached (25.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40cf00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X8, [X21, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X22, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 44ec60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 44ed80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDP X9, X8, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X23, X8,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50
B.CC 40cf00 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::WaveFunction::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	WaveFunction.cpp:231-234
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:231-234
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.34 cycles (7.27x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.50 to 1.50 cycles (1.67x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

26% of peak load performance is reached (25.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40cf00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X8, [X21, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X22, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 44ec60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 44ed80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDP X9, X8, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X23, X8,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50
B.CC 40cf00 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code