OV - exec - Function qmcplusplus::WaveFunction::ratio(qmcplusplus::ParticleSet&, int)

	Function: qmcplusplus::WaveFunction::ratio(qmcplusplus::ParticleSet&, int)	Module: exec	Source: WaveFunction.cpp:213-221 [...]	Coverage: 0.04%

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 213 - 221

--------------------------------------------------------------------------------

213: {

214:   valT ratio = (iat < nelup ? Det_up->ratio(P, iat) : Det_dn->ratio(P, iat));

215:

216:   for (size_t i = 0; i < Jastrows.size(); i++)

217:   {

218:     ScopedTimer local_timer(jastrow_timers[i]);

219:     ratio *= Jastrows[i]->ratio(P, iat);

220:   }

221:   return ratio;

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

0x40cdd0 STP	D9, D8, [SP, #944]!

0x40cdd4 STP	X29, X30, [SP, #16]

0x40cdd8 STR	X23, [SP, #32]

0x40cddc STP	X22, X21, [SP, #48]

0x40cde0 STP	X20, X19, [SP, #64]

0x40cde4 ADD	X29, SP, #16

0x40cde8 LDR	W8, [X0, #52]

0x40cdec ADD	X9, X0, #8

0x40cdf0 ORR	X21, XZR, X0

0x40cdf4 ORR	W19, WZR, W2

0x40cdf8 ORR	X20, XZR, X1

0x40cdfc CMP	W8, W2

0x40ce00 CSEL	X8, X0, X9, #12

0x40ce04 LDR	X0, [X8]

0x40ce08 LDR	X8, [X0]

0x40ce0c LDR	X8, [X8, #48]

0x40ce10 BLR	X8

0x40ce14 LDP	X9, X8, [X21, #16]

0x40ce18 FMOV	D8, D0

0x40ce1c CMP	X8, X9

0x40ce20 B.EQ	40ce78

0x40ce24 ORR	X23, XZR, XZR

(138) 0x40ce28 LDR	X8, [X21, #88]

(138) 0x40ce2c LDR	X22, [X8, X23,LSL #3]

(138) 0x40ce30 ORR	X0, XZR, X22

(138) 0x40ce34 BL	44ec60

(138) 0x40ce38 LDR	X8, [X21, #16]

(138) 0x40ce3c LDR	X0, [X8, X23,LSL #3]

(138) 0x40ce40 LDR	X8, [X0]

(138) 0x40ce44 LDR	X8, [X8, #48]

(138) 0x40ce48 ORR	X1, XZR, X20

(138) 0x40ce4c ORR	W2, WZR, W19

(138) 0x40ce50 BLR	X8

(138) 0x40ce54 ORR	X0, XZR, X22

(138) 0x40ce58 FMOV	D9, D0

(138) 0x40ce5c BL	44ed80

(138) 0x40ce60 LDP	X9, X8, [X21, #16]

(138) 0x40ce64 FMUL	D8, D9, D8

(138) 0x40ce68 ADD	X23, X23, #1

(138) 0x40ce6c SUB	X8, X8, X9

(138) 0x40ce70 CMP	X23, X8,ASR #3

(138) 0x40ce74 B.CC	40ce28

0x40ce78 FMOV	D0, D8

0x40ce7c LDP	X20, X19, [SP, #64]

0x40ce80 LDP	X22, X21, [SP, #48]

0x40ce84 LDR	X23, [SP, #32]

0x40ce88 LDP	X29, X30, [SP, #16]

0x40ce8c LDP	D9, D8, [SP], #80

0x40ce90 RET

0x40ce94 BL	409350

0x40ce98 ORR	X19, XZR, X0

0x40ce9c ORR	X0, XZR, X22

0x40cea0 BL	44ed80

0x40cea4 ORR	X0, XZR, X19

0x40cea8 BL	403d00

0x40ceac BL	409350

Coverage (%)	Name	Source Location	Module
►100.00+	.omp_outlined..62	miniqmc.cpp:485	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	WaveFunction.cpp:213-221
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:213-221
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.17 to 1.83 cycles (2.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.17 to 0.91 cycles (5.70x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.50 cycles (2.07x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	4.75	4.75	0.75	0.75	0.75	0.75	5.17	4.83	5.00	2.00	2.00
cycles	3.50	3.50	4.75	4.75	4.75	4.75	0.75	0.75	0.75	0.75	5.17	4.83	5.00	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	25%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

23% of peak load performance is reached (22.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (13.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40cdd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D9, D8, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X0, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40ce78 <_ZN11qmcplusplus12WaveFunction5ratioERNS_11ParticleSetEi+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D9, D8, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409350 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d00 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409350 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	WaveFunction.cpp:213-221
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:213-221
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.17 to 1.83 cycles (2.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.50 cycles (2.07x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	4.75	4.75	0.75	0.75	0.75	0.75	5.17	4.83	5.00	2.00	2.00
cycles	3.50	3.50	4.75	4.75	4.75	4.75	0.75	0.75	0.75	0.75	5.17	4.83	5.00	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	25%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

23% of peak load performance is reached (22.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (13.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40cdd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D9, D8, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X0, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40ce78 <_ZN11qmcplusplus12WaveFunction5ratioERNS_11ParticleSetEi+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D9, D8, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409350 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d00 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409350 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼qmcplusplus::WaveFunction::ratio(qmcplusplus::ParticleSet&, int)–	0.04	0.02
○Loop 138 - WaveFunction.cpp:216-219 - exec	0.03	0.01

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code