OV - exec - Function qmcplusplus::TimerType<qmcplusplus::CPUClock>::stop()

	Function: qmcplusplus::TimerType<qmcplusplus::CPUClock>::stop()	Module: exec	Source: NewTimer.cpp:85-120 [...]	Coverage: 0.84%

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_tree.h: 735 - 1903

--------------------------------------------------------------------------------

735:       { return static_cast<_Link_type>(this->_M_impl._M_header._M_parent); }

[...]

780:       { return static_cast<_Link_type>(__x->_M_left); }

[...]

788:       { return static_cast<_Link_type>(__x->_M_right); }

[...]

1902:       while (__x != 0)

1903: 	if (!_M_impl._M_key_compare(_S_key(__x), __k))

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 119

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/tuple: 183 - 183

--------------------------------------------------------------------------------

183:       : _M_head_impl(__h) { }

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h: 33 - 33

--------------------------------------------------------------------------------

33:     return omp_get_wtime();

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 85 - 120

--------------------------------------------------------------------------------

85: {

86:   if (active)

[...]

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       double elapsed = CLOCK()() - start_time;

105:       total_time += elapsed;

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed;

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_map.h: 499 - 501

--------------------------------------------------------------------------------

499: 	if (__i == end() || key_comp()(__k, (*__i).first))

500: #if __cplusplus >= 201103L

501: 	  __i = _M_t._M_emplace_hint_unique(__i, std::piecewise_construct,

0x44ed80 SUB	SP, SP, #64

0x44ed84 STR	D8, [SP, #16]

0x44ed88 STP	X29, X30, [SP, #24]

0x44ed8c STR	X21, [SP, #40]

0x44ed90 STP	X20, X19, [SP, #48]

0x44ed94 ADD	X29, SP, #24

0x44ed98 LDRB	W8, [X0, #56]

0x44ed9c CBZ	W8, 44ef8c

0x44eda0 ORR	X19, XZR, X0

0x44eda4 BL	403ca0

0x44eda8 CMP	W0, #1

0x44edac B.LT	44ede0

0x44edb0 ORR	W20, WZR, W0

0x44edb4 MOVZ	W21, #1

0x44edb8 HINT	#0

0x44edbc HINT	#0

(1374) 0x44edc0 ORR	W0, WZR, W20

(1374) 0x44edc4 BL	403cb0

(1374) 0x44edc8 CMP	W0, #0

(1374) 0x44edcc CSINC	W8, WZR, WZR, #1

(1374) 0x44edd0 SUBS	W20, W20, #1

(1374) 0x44edd4 AND	W21, W8, W21

(1374) 0x44edd8 B.HI	44edc0

0x44eddc TBZ	W21, #0, 44ef8c

0x44ede0 BL	403a80

0x44ede4 LDP	D1, D2, [X19]

0x44ede8 LDR	X8, [X19, #16]

0x44edec LDR	X10, [X19, #120]

0x44edf0 ADD	X20, X19, #80

0x44edf4 ADD	X1, X19, #112

0x44edf8 ADD	X8, X8, #1

0x44edfc STR	X8, [X19, #16]

0x44ee00 FSUB	D8, D0, S1

0x44ee04 FADD	D0, D2, D8

0x44ee08 STR	D0, [X19, #8]

0x44ee0c CBZ	X10, 44ee94

0x44ee10 LDP	X8, X9, [X19, #80]

0x44ee14 ORR	X0, XZR, X1

0x44ee18 B	44ee30

0x44ee1c HINT	#0

0x44ee20 ADD	X11, X10, #16

0x44ee24 ORR	X0, XZR, X10

0x44ee28 LDR	X10, [X11]

0x44ee2c CBZ	X10, 44ee64

(1373) 0x44ee30 LDR	X11, [X10, #32]

(1373) 0x44ee34 ORR	X12, XZR, X8

(1373) 0x44ee38 CMP	X11, X8

(1373) 0x44ee3c B.NE	44ee50

(1373) 0x44ee40 LDR	X11, [X10, #40]

(1373) 0x44ee44 ORR	X12, XZR, X9

(1373) 0x44ee48 CMP	X11, X9

(1373) 0x44ee4c B.EQ	44ee20

(1373) 0x44ee50 CMP	X11, X12

(1373) 0x44ee54 B.GE	44ee20

(1373) 0x44ee58 ADD	X11, X10, #24

(1373) 0x44ee5c LDR	X10, [X11]

(1373) 0x44ee60 CBNZ	X10, 44ee30

0x44ee64 CMP	X0, X1

0x44ee68 B.EQ	44ee94

0x44ee6c LDR	X10, [X0, #32]

0x44ee70 CMP	X8, X10

0x44ee74 B.NE	44ee88

0x44ee78 LDR	X10, [X0, #40]

0x44ee7c ORR	X8, XZR, X9

0x44ee80 CMP	X9, X10

0x44ee84 B.EQ	44eeb0

0x44ee88 ORR	X1, XZR, X0

0x44ee8c CMP	X8, X10

0x44ee90 B.GE	44eeb0

0x44ee94 ADD	X0, X19, #104

0x44ee98 ADRP	X2,

0x44ee9c ADD	X2, X2, #3824

0x44eea0 ADD	X3, SP, #8

0x44eea4 STR	X20, [SP, #8]

0x44eea8 ADD	X4, SP, #0

0x44eeac BL	44efb0

0x44eeb0 LDR	D0, [X0, #56]

0x44eeb4 ADD	X1, X19, #160

0x44eeb8 FADD	D0, D0, D8

0x44eebc STR	D0, [X0, #56]

0x44eec0 LDR	X10, [X19, #168]

0x44eec4 CBZ	X10, 44ef54

0x44eec8 LDP	X8, X9, [X19, #80]

0x44eecc ORR	X0, XZR, X1

0x44eed0 B	44eef0

0x44eed4 HINT	#0

0x44eed8 HINT	#0

0x44eedc HINT	#0

0x44eee0 ADD	X11, X10, #16

0x44eee4 ORR	X0, XZR, X10

0x44eee8 LDR	X10, [X11]

0x44eeec CBZ	X10, 44ef24

(1372) 0x44eef0 LDR	X11, [X10, #32]

(1372) 0x44eef4 ORR	X12, XZR, X8

(1372) 0x44eef8 CMP	X11, X8

(1372) 0x44eefc B.NE	44ef10

(1372) 0x44ef00 LDR	X11, [X10, #40]

(1372) 0x44ef04 ORR	X12, XZR, X9

(1372) 0x44ef08 CMP	X11, X9

(1372) 0x44ef0c B.EQ	44eee0

(1372) 0x44ef10 CMP	X11, X12

(1372) 0x44ef14 B.GE	44eee0

(1372) 0x44ef18 ADD	X11, X10, #24

(1372) 0x44ef1c LDR	X10, [X11]

(1372) 0x44ef20 CBNZ	X10, 44eef0

0x44ef24 CMP	X0, X1

0x44ef28 B.EQ	44ef54

0x44ef2c LDR	X10, [X0, #32]

0x44ef30 CMP	X8, X10

0x44ef34 B.NE	44ef48

0x44ef38 LDR	X10, [X0, #40]

0x44ef3c ORR	X8, XZR, X9

0x44ef40 CMP	X9, X10

0x44ef44 B.EQ	44ef70

0x44ef48 ORR	X1, XZR, X0

0x44ef4c CMP	X8, X10

0x44ef50 B.GE	44ef70

0x44ef54 ADD	X0, X19, #152

0x44ef58 ADRP	X2,

0x44ef5c ADD	X2, X2, #3824

0x44ef60 ADD	X3, SP, #8

0x44ef64 STR	X20, [SP, #8]

0x44ef68 ADD	X4, SP, #0

0x44ef6c BL	44f470

0x44ef70 LDR	X8, [X0, #56]

0x44ef74 ADD	X8, X8, #1

0x44ef78 STR	X8, [X0, #56]

0x44ef7c LDR	X0, [X19, #72]

0x44ef80 CBZ	X0, 44ef8c

0x44ef84 ORR	X1, XZR, X19

0x44ef88 BL	4546c0

0x44ef8c LDR	D8, [SP, #16]

0x44ef90 LDP	X20, X19, [SP, #48]

0x44ef94 LDR	X21, [SP, #40]

0x44ef98 LDP	X29, X30, [SP, #24]

0x44ef9c ADD	SP, SP, #64

0x44efa0 RET

0x44efa4 HINT	#0

0x44efa8 HINT	#0

0x44efac HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:485	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_tree.h:735,780,788,1902-1903
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/tuple:183
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_map.h:499-501

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 3.50 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.25 to 2.28 cycles (5.37x speedup).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.25 to 2.50 cycles (4.90x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 193 bytes. The binary function is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	11.50	11.50	11.50	11.50	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50
cycles	12.00	12.00	11.50	11.50	11.50	11.50	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

all	2%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.25 cycles. At this rate:

16% of peak load performance is reached (15.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44ed80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRB W8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W8, 44ef8c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ca0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 44ede0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
TBZ W21, #0, 44ef8c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 403a80 <@plt_start@+0x150>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D1, D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X19, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FSUB D8, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D0, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X19, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X10, 44ee94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 44ee30 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
ADD X11, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 44ee64 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44ee94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 44ee88 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44eeb0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 44eeb0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <464e98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44efb0 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_dESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X1, X19, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X0, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X10, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 44ef54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 44eef0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADD X11, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 44ef24 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44ef54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 44ef48 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44ef70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 44ef70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <464f58>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44f470 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_lESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 44ef8c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4546c0 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_tree.h:735,780,788,1902-1903
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/tuple:183
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_map.h:499-501

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 3.50 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.25 to 2.50 cycles (4.90x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 193 bytes. The binary function is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	11.50	11.50	11.50	11.50	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50
cycles	12.00	12.00	11.50	11.50	11.50	11.50	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

all	2%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.25 cycles. At this rate:

16% of peak load performance is reached (15.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44ed80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRB W8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W8, 44ef8c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ca0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 44ede0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
TBZ W21, #0, 44ef8c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 403a80 <@plt_start@+0x150>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D1, D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X19, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FSUB D8, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D0, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X19, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X10, 44ee94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 44ee30 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
ADD X11, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 44ee64 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44ee94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 44ee88 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44eeb0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 44eeb0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <464e98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44efb0 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_dESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X1, X19, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X0, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X10, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 44ef54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 44eef0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADD X11, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 44ef24 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44ef54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 44ef48 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44ef70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 44ef70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <464f58>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44f470 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_lESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 44ef8c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4546c0 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::stop()–	0.84	0
○Loop 1373 - stl_tree.h:788-1903 - exec	0	0
○Loop 1372 - stl_tree.h:788-1903 - exec	0	0
○Loop 1374 - NewTimer.cpp:99-100 - exec	0	0

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code