OV - exec - Function .omp

	Function: .omp_outlined..11	Module: exec	Source: BsplineAllocator.hpp:171-180	Coverage: 0.84%

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp: 171 - 180

--------------------------------------------------------------------------------

171: #pragma omp parallel for collapse(3)

172:   for (int ix = 0; ix < spline->x_grid.num + 3; ix++)

173:     for (int iy = 0; iy < spline->y_grid.num + 3; iy++)

174:       for (int iz = 0; iz < spline->z_grid.num + 3; iz++)

175:       {

176:         intptr_t xs = spline->x_stride;

177:         intptr_t ys = spline->y_stride;

178:         intptr_t zs = spline->z_stride;

179:         for (int ind = first; ind < last; ind++)

180:           spline->coefs[ix * xs + iy * ys + iz * zs + ind] = coeff(ix, iy, iz) * prefactor[ind];

0x42ecc0 SUB	SP, SP, #192

0x42ecc4 STP	X29, X30, [SP, #96]

0x42ecc8 STP	X28, X27, [SP, #112]

0x42eccc STP	X26, X25, [SP, #128]

0x42ecd0 STP	X24, X23, [SP, #144]

0x42ecd4 STP	X22, X21, [SP, #160]

0x42ecd8 STP	X20, X19, [SP, #176]

0x42ecdc ADD	X29, SP, #96

0x42ece0 LDR	X25, [X2]

0x42ece4 LDR	W8, [X25, #56]

0x42ece8 LDR	W9, [X25, #96]

0x42ecec LDR	W10, [X25, #136]

0x42ecf0 CMN	W8, #2

0x42ecf4 CCMN	W9, #2, #8, #10

0x42ecf8 CCMN	W10, #2, #8, #10

0x42ecfc B.LT	42f00c

0x42ed00 LDR	W27, [X0]

0x42ed04 ADD	W21, W9, #3

0x42ed08 ADD	W8, W8, #3

0x42ed0c ADD	W9, W10, #3

0x42ed10 LDRSW	X20, [X3]

0x42ed14 LDRSW	X22, [X4]

0x42ed18 ORR	X19, XZR, X5

0x42ed1c ADRP	X0,

0x42ed20 ADD	X0, X0, #2416

0x42ed24 LDR	X23, [X6]

0x42ed28 UMADDL	X8, W21, W8, XZR

0x42ed2c SBFM	X24, X9, #0, #31

0x42ed30 STUR	WZR, [X29, #484]

0x42ed34 MOVN	X9, #0

0x42ed38 SUB	X3, X29, #28

0x42ed3c SUB	X4, X29, #8

0x42ed40 SUB	X5, X29, #16

0x42ed44 SUB	X6, X29, #24

0x42ed48 MOVZ	W2, #34

0x42ed4c MOVZ	W7, #1

0x42ed50 MADD	X26, X8, X24, X9

0x42ed54 STP	X26, XZR, [X29, #1008]

0x42ed58 ORR	W1, WZR, W27

0x42ed5c MOVZ	W8, #1

0x42ed60 STUR	X8, [X29, #488]

0x42ed64 STR	X8, [SP]

0x42ed68 BL	404110

0x42ed6c LDP	X8, X9, [X29, #1008]

0x42ed70 CMP	X8, X26

0x42ed74 CSEL	X8, X8, X26, #11

0x42ed78 CMP	X9, X8

0x42ed7c B.GT	42effc

0x42ed80 CMP	W20, W22

0x42ed84 B.GE	42effc

0x42ed88 LDP	X12, X13, [X25, #16]

0x42ed8c LDP	X3, X10, [X19, #16]

0x42ed90 MADD	W11, W24, W21, WZR

0x42ed94 ADD	X15, X23, X22,LSL #3

0x42ed98 LDR	X14, [X25, #32]

0x42ed9c LDR	X4, [X19, #8]

0x42eda0 CNTW	X17, ALL

0x42eda4 SBFM	X0, X11, #0, #31

0x42eda8 CMP	X17, #16

0x42edac SUB	X16, X22, X20

0x42edb0 SUB	W6, WZR, W21

0x42edb4 PTRUE	P0.D, ALL

0x42edb8 STR	W27, [SP, #12]

0x42edbc STUR	X12, [X29, #472]

0x42edc0 LDR	X12, [X25, #8]

0x42edc4 ADD	X11, X10, #8

0x42edc8 STR	X13, [SP, #48]

0x42edcc UBFM	X13, X20, #61, #60

0x42edd0 ADD	X18, X23, X13

0x42edd4 STP	X11, X15, [SP, #32]

0x42edd8 MOVZ	W11, #16

0x42eddc CSEL	X5, X17, X11, #8

0x42ede0 ADD	X11, X23, #16

0x42ede4 ADDVL	X25, X18, #1

0x42ede8 STR	X11, [SP, #24]

0x42edec ADD	X1, X12, X13

0x42edf0 ADD	X11, X12, #16

0x42edf4 STR	X11, [SP, #16]

0x42edf8 B	42ee0c

0x42edfc HINT	#0

(905) 0x42ee00 CMP	X9, X8

(905) 0x42ee04 ADD	X9, X9, #1

(905) 0x42ee08 B.EQ	42eff8

(905) 0x42ee0c SDIV	X27, X9, X0

(905) 0x42ee10 LDUR	X7, [X29, #472]

(905) 0x42ee14 ORR	X21, XZR, X20

(905) 0x42ee18 CMP	X16, X5

(905) 0x42ee1c MSUB	X11, X27, X0, X9

(905) 0x42ee20 SBFM	X15, X27, #0, #31

(905) 0x42ee24 MADD	X30, X7, X15, XZR

(905) 0x42ee28 SDIV	X28, X11, X24

(905) 0x42ee2c MSUB	W11, W28, W24, W11

(905) 0x42ee30 SBFM	X2, X28, #0, #31

(905) 0x42ee34 SBFM	X13, X11, #0, #31

(905) 0x42ee38 MADD	X11, X15, X4, X2

(905) 0x42ee3c LDR	X15, [SP, #48]

(905) 0x42ee40 MADD	X11, X11, X3, X13

(905) 0x42ee44 ADD	X26, X10, X11,LSL #3

(905) 0x42ee48 MADD	X19, X15, X2, XZR

(905) 0x42ee4c B.CC	42ef08

(905) 0x42ee50 ADD	X15, X30, X19

(905) 0x42ee54 MADD	X13, X14, X13, XZR

(905) 0x42ee58 ADD	X2, X19, X30

(905) 0x42ee5c ORR	X21, XZR, X20

(905) 0x42ee60 ADD	X15, X15, X13

(905) 0x42ee64 ADD	X13, X13, X22

(905) 0x42ee68 ADD	X13, X13, X2

(905) 0x42ee6c LDR	X2, [SP, #32]

(905) 0x42ee70 ADD	X15, X1, X15,LSL #3

(905) 0x42ee74 ADD	X13, X12, X13,LSL #3

(905) 0x42ee78 ADD	X2, X2, X11,LSL #3

(905) 0x42ee7c LDR	X11, [SP, #40]

(905) 0x42ee80 CMP	X15, X11

(905) 0x42ee84 CCMP	X18, X13, #2, #3

(905) 0x42ee88 CSINC	W11, WZR, WZR, #2

(905) 0x42ee8c CMP	X26, X13

(905) 0x42ee90 CCMP	X15, X2, #2, #3

(905) 0x42ee94 B.CC	42ef08

(905) 0x42ee98 ORR	X21, XZR, X20

(905) 0x42ee9c TBNZ	W11, #0, 42ef08

0x42eea0 UDIV	X11, X16, X17

0x42eea4 LD1RD	{Z0.D}, P0/Z, [X26]

0x42eea8 ORR	X7, XZR, XZR

0x42eeac MADD	X2, X11, X17, XZR

0x42eeb0 SUB	W11, WZR, W28

0x42eeb4 MADD	W11, W6, W27, W11

0x42eeb8 SUB	X15, X16, X2

0x42eebc ADD	X21, X2, X20

0x42eec0 MADD	W11, W24, W11, W9

0x42eec4 SBFM	X11, X11, #0, #31

0x42eec8 MADD	X11, X14, X11, X30

0x42eecc ADD	X11, X11, X19

0x42eed0 UBFM	X13, X11, #61, #60

0x42eed4 ADDVL	X11, X13, #1

0x42eed8 ADD	X13, X1, X13

0x42eedc ADD	X11, X1, X11

(904) 0x42eee0 LD1D	{Z1.D}, P0/Z, [X18, X7,LSL #3]

(904) 0x42eee4 LD1D	{Z2.D}, P0/Z, [X25, X7,LSL #3]

(904) 0x42eee8 FMUL	Z1.D, Z1.D, Z0.D

(904) 0x42eeec FMUL	Z2.D, Z2.D, Z0.D

(904) 0x42eef0 ST1D	{Z1.D}, P0, [X13, X7,LSL #3]

(904) 0x42eef4 ST1D	{Z2.D}, P0, [X11, X7,LSL #3]

(904) 0x42eef8 ADD	X7, X7, X17

(904) 0x42eefc CMP	X2, X7

(904) 0x42ef00 B.NE	42eee0

0x42ef04 CBZ	X15, 42ee00

(905) 0x42ef08 SUB	W11, W22, W21

(905) 0x42ef0c ORR	X15, XZR, X21

(905) 0x42ef10 ANDS	X7, X11, #4160

(905) 0x42ef14 B.EQ	42ef5c

(905) 0x42ef18 SUB	W11, WZR, W28

(905) 0x42ef1c ORR	X15, XZR, X21

(905) 0x42ef20 MADD	W11, W6, W27, W11

(905) 0x42ef24 MADD	W11, W24, W11, W9

(905) 0x42ef28 SBFM	X11, X11, #0, #31

(905) 0x42ef2c MADD	X11, X14, X11, X30

(905) 0x42ef30 ADD	X11, X11, X19

(905) 0x42ef34 ADD	X11, X12, X11,LSL #3

(905) 0x42ef38 HINT	#0

(905) 0x42ef3c HINT	#0

  (907) 0x42ef40 LDR	D0, [X26]

  (907) 0x42ef44 LDR	D1, [X23, X15,LSL #3]

  (907) 0x42ef48 SUBS	X7, X7, #1

  (907) 0x42ef4c FMUL	D0, D1, D0

  (907) 0x42ef50 STR	D0, [X11, X15,LSL #3]

  (907) 0x42ef54 ADD	X15, X15, #1

  (907) 0x42ef58 B.NE	42ef40

(905) 0x42ef5c ORN	X11, XZR, X21

(905) 0x42ef60 ADD	X11, X11, X22

(905) 0x42ef64 CMP	X11, #3

(905) 0x42ef68 B.CC	42ee00

(905) 0x42ef6c LDR	X13, [SP, #24]

(905) 0x42ef70 UBFM	X11, X15, #61, #60

(905) 0x42ef74 SUB	X21, X22, X15

(905) 0x42ef78 ADD	X7, X13, X11

(905) 0x42ef7c SUB	W13, WZR, W28

(905) 0x42ef80 MADD	W13, W6, W27, W13

(905) 0x42ef84 MADD	W13, W24, W13, W9

(905) 0x42ef88 SBFM	X13, X13, #0, #31

(905) 0x42ef8c MADD	X13, X14, X13, XZR

(905) 0x42ef90 ADD	X13, X13, X30

(905) 0x42ef94 ADD	X13, X13, X19

(905) 0x42ef98 ADD	X11, X11, X13,LSL #3

(905) 0x42ef9c LDR	X13, [SP, #16]

(905) 0x42efa0 ADD	X19, X13, X11

  (906) 0x42efa4 LDR	D0, [X26]

  (906) 0x42efa8 LDUR	D1, [X7, #496]

  (906) 0x42efac SUBS	X21, X21, #4

  (906) 0x42efb0 FMUL	D0, D1, D0

  (906) 0x42efb4 STUR	D0, [X19, #496]

  (906) 0x42efb8 LDR	D0, [X26]

  (906) 0x42efbc LDUR	D1, [X7, #504]

  (906) 0x42efc0 FMUL	D0, D1, D0

  (906) 0x42efc4 STUR	D0, [X19, #504]

  (906) 0x42efc8 LDR	D0, [X26]

  (906) 0x42efcc LDR	D1, [X7]

  (906) 0x42efd0 FMUL	D0, D1, D0

  (906) 0x42efd4 STR	D0, [X19]

  (906) 0x42efd8 LDR	D0, [X26]

  (906) 0x42efdc LDR	D1, [X7, #8]

  (906) 0x42efe0 ADD	X7, X7, #32

  (906) 0x42efe4 FMUL	D0, D1, D0

  (906) 0x42efe8 STR	D0, [X19, #8]

  (906) 0x42efec ADD	X19, X19, #32

  (906) 0x42eff0 B.NE	42efa4

(905) 0x42eff4 B	42ee00

0x42eff8 LDR	W27, [SP, #12]

0x42effc ORR	W1, WZR, W27

0x42f000 ADRP	X0,

0x42f004 ADD	X0, X0, #2440

0x42f008 BL	403ff0

0x42f00c LDP	X20, X19, [SP, #176]

0x42f010 LDP	X22, X21, [SP, #160]

0x42f014 LDP	X24, X23, [SP, #144]

0x42f018 LDP	X26, X25, [SP, #128]

0x42f01c LDP	X28, X27, [SP, #112]

0x42f020 LDP	X29, X30, [SP, #96]

0x42f024 ADD	SP, SP, #192

0x42f028 RET

0x42f02c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.25 to 1.00 cycles (16.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 16.25 to 12.46 cycles (1.30x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.25 to 1.00 cycles (16.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	16.25	16.25	16.25	16.25	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.00	8.00
cycles	4.00	4.00	16.25	16.25	16.25	16.25	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.00	8.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.63
Overall L1	16.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

14% of peak load performance is reached (13.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ecc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X25, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X25, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMN W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMN W9, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMN W10, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 42f00c <.omp_outlined..11+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W21, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <488d1c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X8, W21, W8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X24, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X26, X8, X24, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404110 <@plt_start@+0x7e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42effc <.omp_outlined..11+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42effc <.omp_outlined..11+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X13, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD W11, W24, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X23, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X25, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X0, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB X16, X22, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W27, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X13, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X11, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X5, X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X23, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X25, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42ee0c <.omp_outlined..11+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
UDIV X11, X16, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LD1RD {Z0.D}, P0/Z, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X2, X11, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W11, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W11, W6, W27, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X2, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W11, W24, W11, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X11, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X14, X11, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X11, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X11, X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 42ee00 <.omp_outlined..11+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W27, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <488000>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ff0 <@plt_start@+0x6c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.25 to 1.00 cycles (16.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	16.25	16.25	16.25	16.25	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.00	8.00
cycles	4.00	4.00	16.25	16.25	16.25	16.25	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.00	8.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.63
Overall L1	16.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

14% of peak load performance is reached (13.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ecc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X25, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X25, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMN W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMN W9, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMN W10, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 42f00c <.omp_outlined..11+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W21, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <488d1c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X8, W21, W8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X24, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X26, X8, X24, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404110 <@plt_start@+0x7e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42effc <.omp_outlined..11+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42effc <.omp_outlined..11+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X13, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X10, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD W11, W24, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X23, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X25, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X0, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB X16, X22, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W27, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X13, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X11, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X5, X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X23, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X25, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42ee0c <.omp_outlined..11+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
UDIV X11, X16, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LD1RD {Z0.D}, P0/Z, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X2, X11, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W11, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W11, W6, W27, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X15, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X2, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W11, W24, W11, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X11, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X14, X11, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X11, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X11, X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 42ee00 <.omp_outlined..11+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W27, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <488000>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ff0 <@plt_start@+0x6c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..11–	0.84	0
○Loop 904 - BsplineAllocator.hpp:179-180 - exec	0.84	0
▼Loop 905 - BsplineAllocator.hpp:172-180 - exec–	0	0
○Loop 906 - BsplineAllocator.hpp:179-180 - exec	0	0
○Loop 907 - BsplineAllocator.hpp:179-180 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code