OV - exec - Function qmcplusplus::Vector<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >::resize(unsigned long, qmcplusplus::TinyVector<double, 3u>)

	Function: qmcplusplus::Vector<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyV ...	Module: exec	Source: OhmmsVector.h:182-301 [...]	Coverage: 0.02%

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/ext/new_allocator.h: 105 - 139

--------------------------------------------------------------------------------

105: 	if (__builtin_expect(__n > this->_M_max_size(), false))

106: 	  {

107: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

108: 	    // 3190. allocator::allocate sometimes returns too little storage

109: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

110: 	      std::__throw_bad_array_new_length();

111: 	    std::__throw_bad_alloc();

[...]

121: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

139: 	::operator delete(__p

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183

--------------------------------------------------------------------------------

183:     return (const_cast<T1&>(a) = b);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 176 - 176

--------------------------------------------------------------------------------

176:   inline Type_t& operator[](unsigned int i) { return X[i]; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 182 - 301

--------------------------------------------------------------------------------

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_algobase.h: 911 - 1120

--------------------------------------------------------------------------------

911:       for (; __first != __last; ++__first)

[...]

1120:       std::__fill_a(__first, __first + __n, __value);

0x415800 STP	X29, X30, [SP, #976]!

0x415804 STP	X22, X21, [SP, #16]

0x415808 STP	X20, X19, [SP, #32]

0x41580c ADD	X29, SP, #0

0x415810 LDP	X12, X8, [X0, #8]

0x415814 CMP	X12, X8

0x415818 B.HI	415a80

0x41581c ORR	X20, XZR, X2

0x415820 ORR	X19, XZR, X1

0x415824 ORR	X21, XZR, X0

0x415828 CMP	X8, X1

0x41582c B.CS	41589c

0x415830 CBZ	X8, 41583c

0x415834 LDR	X0, [X21, #24]

0x415838 BL	403dd0

0x41583c ORR	X8, XZR, #3840

0x415840 MOVK	X8, #21846

0x415844 MOVK	X8, #1365

0x415848 CMP	X19, X8

0x41584c B.CS	415a64

0x415850 ADD	X8, X19, X19,LSL #1

0x415854 UBFM	X22, X8, #61, #60

0x415858 ORR	X0, XZR, X22

0x41585c BL	403d70

0x415860 ORR	X9, XZR, #3841

0x415864 SUB	X8, X22, #24

0x415868 LDP	D0, D1, [X20]

0x41586c LDR	D2, [X20, #16]

0x415870 STP	X19, X0, [X21, #16]

0x415874 MOVK	X9, #43691

0x415878 STR	X19, [X21, #8]

0x41587c UMULH	X8, X8, X9

0x415880 CNTW	X9, ALL

0x415884 UBFM	X8, X8, #4, #63

0x415888 ADD	X8, X8, #1

0x41588c CMP	X8, X9

0x415890 B.CS	415994

0x415894 ORR	X8, XZR, X0

0x415898 B	4159fc

0x41589c CMP	X12, X19

0x4158a0 B.CS	415a50

0x4158a4 LDR	X8, [X21, #24]

0x4158a8 MOVZ	W9, #24

0x4158ac MOVN	X11, #23

0x4158b0 ORR	X13, XZR, #3841

0x4158b4 MOVZ	W15, #20

0x4158b8 MOVK	X13, #43691

0x4158bc MADD	X10, X12, X9, X8

0x4158c0 ADD	X9, X19, X19,LSL #1

0x4158c4 UBFM	X9, X9, #61, #60

0x4158c8 MADD	X11, X12, X11, X9

0x4158cc SUB	X11, X11, #24

0x4158d0 UMULH	X11, X11, X13

0x4158d4 UBFM	X14, X11, #4, #63

0x4158d8 CNTW	X11, ALL

0x4158dc ADD	X13, X14, #1

0x4158e0 CMP	X11, #20

0x4158e4 CSEL	X15, X11, X15, #8

0x4158e8 CMP	X13, X15

0x4158ec B.CC	415a24

0x4158f0 MOVZ	W17, #24

0x4158f4 ADD	X16, X20, #16

0x4158f8 ADD	X15, X20, #8

0x4158fc ADD	X18, X20, #24

0x415900 MADD	X14, X14, X17, XZR

0x415904 CMP	X10, X16

0x415908 MADD	X12, X12, X17, X14

0x41590c ADD	X12, X12, X8

0x415910 ADD	X17, X12, #24

0x415914 CCMP	X15, X17, #2, #3

0x415918 CSINC	W12, WZR, WZR, #2

0x41591c CMP	X10, X15

0x415920 CCMP	X17, X20, #0, #3

0x415924 CSINC	W14, WZR, WZR, #9

0x415928 CMP	X16, X17

0x41592c CCMP	X10, X18, #2, #3

0x415930 B.CC	415a24

0x415934 TBNZ	W12, #0, 415a24

0x415938 TBNZ	W14, #0, 415a24

0x41593c RDVL	X12, #1

0x415940 PTRUE	P0.D, ALL

0x415944 UBFM	X15, X12, #4, #63

0x415948 UDIV	X12, X13, X11

0x41594c ADD	X16, X15, X15,LSL #1

0x415950 UBFM	X15, X16, #59, #58

0x415954 UBFM	X16, X16, #60, #59

0x415958 MADD	X14, X12, X11, XZR

0x41595c MOVZ	W12, #24

0x415960 SUB	X13, X13, X14

0x415964 MADD	X12, X14, X12, X10

(292) 0x415968 LD1RD	{Z0.D}, P0/Z, [X20]

(292) 0x41596c LD1RD	{Z1.D}, P0/Z, [X20, #1]

(292) 0x415970 LD1RD	{Z2.D}, P0/Z, [X20, #2]

(292) 0x415974 ADD	X17, X10, X16

(292) 0x415978 SUBS	X14, X14, X11

(292) 0x41597c ST3D	{Z0.D, Z1.D, Z2.D}, P0, [X10, MUL VL]

(292) 0x415980 ADD	X10, X10, X15

(292) 0x415984 ST3D	{Z0.D, Z1.D, Z2.D}, P0, [X17, MUL VL]

(292) 0x415988 B.NE	415968

0x41598c CBNZ	X13, 415a28

0x415990 B	415a50

0x415994 RDVL	X10, #1

0x415998 DUP	Z3.D, Z0.D[0]

0x41599c DUP	Z4.D, Z1.D[0]

0x4159a0 PTRUE	P0.D, ALL

0x4159a4 ORR	X14, XZR, X0

0x4159a8 DUP	Z5.D, Z2.D[0]

0x4159ac UBFM	X12, X10, #4, #63

0x4159b0 UDIV	X10, X8, X9

0x4159b4 ADD	X13, X12, X12,LSL #1

0x4159b8 UBFM	X12, X13, #59, #58

0x4159bc UBFM	X13, X13, #60, #59

0x4159c0 MADD	X11, X10, X9, XZR

0x4159c4 SUB	X10, X8, X11

0x4159c8 MOVZ	W8, #24

0x4159cc MADD	X8, X11, X8, X0

0x4159d0 HINT	#0

0x4159d4 HINT	#0

0x4159d8 HINT	#0

0x4159dc HINT	#0

(294) 0x4159e0 ST3D	{Z3.D, Z4.D, Z5.D}, P0, [X14, MUL VL]

(294) 0x4159e4 ADD	X15, X14, X13

(294) 0x4159e8 ADD	X14, X14, X12

(294) 0x4159ec SUBS	X11, X11, X9

(294) 0x4159f0 ST3D	{Z3.D, Z4.D, Z5.D}, P0, [X15, MUL VL]

(294) 0x4159f4 B.NE	4159e0

0x4159f8 CBZ	X10, 415a14

0x4159fc ADD	X9, X0, X22

(295) 0x415a00 STP	D0, D1, [X8]

(295) 0x415a04 STR	D2, [X8, #16]

(295) 0x415a08 ADD	X8, X8, #24

(295) 0x415a0c CMP	X8, X9

(295) 0x415a10 B.NE	415a00

0x415a14 LDP	X20, X19, [SP, #32]

0x415a18 LDP	X22, X21, [SP, #16]

0x415a1c LDP	X29, X30, [SP], #48

0x415a20 RET

0x415a24 ORR	X12, XZR, X10

0x415a28 ADD	X8, X8, X9

(293) 0x415a2c LDR	D0, [X20]

(293) 0x415a30 STR	D0, [X12]

(293) 0x415a34 LDR	D0, [X20, #8]

(293) 0x415a38 STR	D0, [X12, #8]

(293) 0x415a3c LDR	D0, [X20, #16]

(293) 0x415a40 STR	D0, [X12, #16]

(293) 0x415a44 ADD	X12, X12, #24

(293) 0x415a48 CMP	X12, X8

(293) 0x415a4c B.NE	415a2c

0x415a50 STR	X19, [X21, #8]

0x415a54 LDP	X20, X19, [SP, #32]

0x415a58 LDP	X22, X21, [SP, #16]

0x415a5c LDP	X29, X30, [SP], #48

0x415a60 RET

0x415a64 ORR	X8, XZR, #3841

0x415a68 MOVK	X8, #43691

0x415a6c MOVK	X8, #2730

0x415a70 CMP	X19, X8

0x415a74 B.CC	415a7c

0x415a78 BL	404090

0x415a7c BL	404130

0x415a80 MOVZ	W0, #16

0x415a84 BL	403f90

0x415a88 ORR	X19, XZR, X0

0x415a8c ADRP	X1,

0x415a90 ADD	X1, X1, #1282

0x415a94 BL	403b30

0x415a98 ADRP	X1,

0x415a9c ADRP	X2,

0x415aa0 ORR	X0, XZR, X19

0x415aa4 LDR	X1, [X1, #3960]

0x415aa8 LDR	X2, [X2, #3880]

0x415aac BL	404000

0x415ab0 ORR	X20, XZR, X0

0x415ab4 ORR	X0, XZR, X19

0x415ab8 BL	403f10

0x415abc ORR	X0, XZR, X20

0x415ac0 BL	403d00

0x415ac4 HINT	#0

0x415ac8 HINT	#0

0x415acc HINT	#0

0x415ad0 HINT	#0

0x415ad4 HINT	#0

0x415ad8 HINT	#0

0x415adc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:104	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	unique_ptr.h:360	exec
○	.omp_outlined.	miniqmc.cpp:389	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	OhmmsVector.h:182-301
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/ext/new_allocator.h:105-111,121,139
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:176
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-301
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_algobase.h:911,1120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.50 to 2.50 cycles (10.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 26.50 to 16.19 cycles (1.64x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 26.50 to 4.50 cycles (5.89x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	155
loop length	620
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	26.50	26.50	26.50	26.50	1.50	1.50	0.00	0.00	6.33	6.33	6.33	3.00	3.00
cycles	13.00	13.00	26.50	26.50	26.50	26.50	1.50	1.50	0.00	0.00	6.33	6.33	6.33	3.00	3.00

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	18.00
Overall L1	26.50

Vectorization ratios

all	5%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.50 cycles. At this rate:

6% of peak load performance is reached (6.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.02 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 415800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X12, X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 415a80 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 41589c <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X8, 41583c <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 403dd0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, #3840	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #21846	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #1365	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 415a64 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X19, X19,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d70 <@plt_start@+0x440>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X22, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D0, D1, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D2, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STP X19, X0, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVK X9, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMULH X8, X8, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
CNTW X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X8, X8, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 415994 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4159fc <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 415a50 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X11, #23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X13, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X12, X9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X19, X19,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X12, X11, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMULH X11, X11, X13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
UBFM X14, X11, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X15, X11, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W17, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X20, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X14, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X12, X12, X17, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X15, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X17, X20, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W14, WZR, WZR, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X18, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ W12, #0, 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ W14, #0, 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X15, X12, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X12, X13, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X16, X15, X15,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X16, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X16, X16, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X12, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X14, X12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CBNZ X13, 415a28 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 415a50 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RDVL X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z3.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z4.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X14, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z5.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UBFM X12, X10, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X10, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X13, X12, X12,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X13, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X13, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X10, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X11, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X10, 415a14 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 415a7c <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404090 <@plt_start@+0x760>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404130 <@plt_start@+0x800>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403f90 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <464a8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1282	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b30 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X1, <489a98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <489a9c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X1, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X2, #3880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 404000 <@plt_start@+0x6d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403f10 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d00 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	OhmmsVector.h:182-301
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/ext/new_allocator.h:105-111,121,139
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:176
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-301
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_algobase.h:911,1120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 26.50 to 4.50 cycles (5.89x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	155
loop length	620
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	26.50	26.50	26.50	26.50	1.50	1.50	0.00	0.00	6.33	6.33	6.33	3.00	3.00
cycles	13.00	13.00	26.50	26.50	26.50	26.50	1.50	1.50	0.00	0.00	6.33	6.33	6.33	3.00	3.00

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	18.00
Overall L1	26.50

Vectorization ratios

all	5%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.50 cycles. At this rate:

6% of peak load performance is reached (6.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.02 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 415800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X12, X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 415a80 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 41589c <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X8, 41583c <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 403dd0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, #3840	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #21846	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #1365	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 415a64 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X19, X19,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d70 <@plt_start@+0x440>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X22, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D0, D1, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D2, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STP X19, X0, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVK X9, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMULH X8, X8, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
CNTW X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X8, X8, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 415994 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4159fc <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 415a50 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X11, #23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X13, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X12, X9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X19, X19,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X12, X11, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMULH X11, X11, X13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
UBFM X14, X11, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X15, X11, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W17, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X20, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X14, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X12, X12, X17, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X15, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X17, X20, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W14, WZR, WZR, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X18, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ W12, #0, 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ W14, #0, 415a24 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X15, X12, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X12, X13, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X16, X15, X15,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X16, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X16, X16, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X12, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X14, X12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CBNZ X13, 415a28 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 415a50 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RDVL X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z3.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z4.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X14, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z5.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UBFM X12, X10, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X10, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X13, X12, X12,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X13, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X13, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X10, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X10, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X11, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X10, 415a14 <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, #3841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X8, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 415a7c <_ZN11qmcplusplus6VectorINS_10TinyVectorIdLj3EEESaIS2_EE6resizeEmS2_+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404090 <@plt_start@+0x760>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404130 <@plt_start@+0x800>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403f90 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <464a8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1282	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b30 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X1, <489a98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <489a9c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X1, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X2, #3880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 404000 <@plt_start@+0x6d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403f10 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403d00 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::Vector, std::allocator > >::resize(unsigned long, qmcplusplus::TinyVector)–	0.02	0.01
○Loop 294 - OperatorTags.h:183-183 - exec	0.02	0.01
○Loop 295 - stl_algobase.h:911-911 - exec	0	0
○Loop 292 - stl_algobase.h:911-911 - exec	0	0
○Loop 293 - stl_algobase.h:911-911 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code