OV - exec - Loop 923

	Loop Id: 923	Module: exec	Source: MultiBsplineRef.hpp:187-286 [...]	Coverage: 0.01%

0x440510 XOR	%EAX,%EAX

0x440512 MOV	%RDI,%RCX

0x440515 SUB	%RAX,%RCX

0x440518 VPBROADCASTQ	%RCX,%YMM9

0x44051e VPCMPNLEUQ	0xbdeb7(%RIP),%YMM9,%K1

0x440529 VMOVUPD	(%RBX,%RAX,8),%YMM9{%K1}{z}

0x440530 VMULPD	%YMM8,%YMM9,%YMM8

0x440535 VMOVUPD	%YMM8,(%RBX,%RAX,8){%K1}

0x44053c MOV	-0x30(%RBP),%RCX

0x440540 ADD	%RAX,%RCX

0x440543 VMOVUPD	(%RBX,%RCX,8),%YMM8{%K1}{z}

0x44054a VMULPD	%YMM7,%YMM8,%YMM7

0x44054e VMOVUPD	%YMM7,(%RBX,%RCX,8){%K1}

0x440555 MOV	-0x98(%RBP),%RDX

0x44055c ADD	%RAX,%RDX

0x44055f VMOVUPD	(%RBX,%RDX,8),%YMM7{%K1}{z}

0x440566 VMULPD	%YMM6,%YMM7,%YMM6

0x44056a VMOVUPD	%YMM6,(%RBX,%RDX,8){%K1}

0x440571 VMOVUPD	(%R13,%RAX,8),%YMM6{%K1}{z}

0x440579 VMULPD	%YMM6,%YMM5,%YMM5

0x44057d VMOVUPD	%YMM5,(%R13,%RAX,8){%K1}

0x440585 MOV	-0x88(%RBP),%RSI

0x44058c ADD	%RAX,%RSI

0x44058f VMOVUPD	(%R13,%RSI,8),%YMM5{%K1}{z}

0x440597 VMULPD	%YMM5,%YMM4,%YMM4

0x44059b VMOVUPD	%YMM4,(%R13,%RSI,8){%K1}

0x4405a3 MOV	-0x80(%RBP),%RSI

0x4405a7 ADD	%RAX,%RSI

0x4405aa VMOVUPD	(%R13,%RSI,8),%YMM4{%K1}{z}

0x4405b2 VMULPD	%YMM4,%YMM3,%YMM3

0x4405b6 VMOVUPD	%YMM3,(%R13,%RSI,8){%K1}

0x4405be VMOVUPD	(%R13,%RCX,8),%YMM3{%K1}{z}

0x4405c6 VMULPD	%YMM3,%YMM2,%YMM2

0x4405ca VMOVUPD	%YMM2,(%R13,%RCX,8){%K1}

0x4405d2 VMOVUPD	(%R13,%RDX,8),%YMM2{%K1}{z}

0x4405da VMULPD	%YMM2,%YMM1,%YMM1

0x4405de VMOVUPD	%YMM1,(%R13,%RDX,8){%K1}

0x4405e6 MOV	-0x90(%RBP),%RCX

0x4405ed ADD	%RAX,%RCX

0x4405f0 VMOVUPD	(%R13,%RCX,8),%YMM1{%K1}{z}

0x4405f8 VMULPD	%YMM1,%YMM0,%YMM0

0x4405fc VMOVUPD	%YMM0,(%R13,%RCX,8){%K1}

0x440604 MOV	-0x158(%RBP),%RCX

0x44060b LEA	0x1(%RCX),%RDX

0x44060f CMP	-0xc8(%RBP),%RCX

0x440616 JE	441312

0x44061c LEA	(,%RDX,8),%RAX

0x440624 MOV	-0x148(%RBP),%RCX

0x44062b MOV	(%RCX,%RDX,8),%RSI

0x44062f MOV	%RDX,-0x158(%RBP)

0x440636 LEA	(%RDX,%RDX,2),%RCX

0x44063a MOV	-0x140(%RBP),%RDX

0x440641 MOV	(%RDX,%RCX,8),%R14

0x440645 LEA	(%RAX,%RAX,4),%RAX

0x440649 MOV	-0x138(%RBP),%RCX

0x440650 MOV	0x18(%RCX,%RAX,1),%RBX

0x440655 MOV	-0x130(%RBP),%RCX

0x44065c MOV	0x18(%RCX,%RAX,1),%R13

0x440661 VMOVUPD	-0x210(%RBP),%XMM0

0x440669 VSUBSD	0x28(%RSI),%XMM0,%XMM0

0x44066e VMOVUPD	-0x200(%RBP),%XMM1

0x440676 VSUBSD	0x50(%RSI),%XMM1,%XMM1

0x44067b VMOVUPD	-0x1f0(%RBP),%XMM2

0x440683 VSUBSD	0x78(%RSI),%XMM2,%XMM2

0x440688 VMOVSD	0x48(%RSI),%XMM3

0x44068d VMOVSD	0x70(%RSI),%XMM4

0x440692 VMOVUPD	%XMM3,-0x240(%RBP)

0x44069a VMULSD	%XMM0,%XMM3,%XMM0

0x44069e MOVSXD	0x38(%RSI),%RAX

0x4406a2 MOV	%RAX,-0x40(%RBP)

0x4406a6 VROUNDSD	$0x9,%XMM0,%XMM0,%XMM15

0x4406ac VSUBSD	%XMM15,%XMM0,%XMM3

0x4406b1 VMOVUPD	%XMM4,-0x230(%RBP)

0x4406b9 VMULSD	%XMM1,%XMM4,%XMM1

0x4406bd VRNDSCALESD	$0x9,%XMM1,%XMM1,%XMM16

0x4406c4 MOVSXD	0x60(%RSI),%R9

0x4406c8 VMOVSD	0x98(%RSI),%XMM0

0x4406d0 VMOVUPD	%XMM0,-0x220(%RBP)

0x4406d8 VMULSD	%XMM2,%XMM0,%XMM0

0x4406dc MOVSXD	0x88(%RSI),%RAX

0x4406e3 MOV	%RAX,-0xb0(%RBP)

0x4406ea VRNDSCALESD	$0x9,%XMM0,%XMM0,%XMM17

0x4406f1 VMULSD	%XMM28,%XMM3,%XMM2

0x4406f7 VSUBSD	%XMM2,%XMM29,%XMM4

0x4406fd VMULSD	%XMM3,%XMM3,%XMM5

0x440701 VMOVDDUP	%XMM3,%XMM6

0x440705 VMOVUPD	-0x1e0(%RBP),%XMM8

0x44070d VBLENDPD	$0x1,%XMM4,%XMM8,%XMM4

0x440713 VMULPD	%XMM4,%XMM6,%XMM4

0x440717 VMOVUPD	0xbf851(%RIP),%XMM9

0x44071f VADDPD	%XMM4,%XMM9,%XMM7

0x440723 VPUNPCKLQDQ	%XMM5,%XMM6,%XMM6

0x440727 VMOVUPD	0xbf851(%RIP),%XMM10

0x44072f VFMADD213PD	%XMM10,%XMM7,%XMM6

0x440734 VMOVUPD	%XMM6,-0x2c0(%RBP)

0x44073c VMULSD	%XMM30,%XMM3,%XMM6

0x440742 VADDSD	%XMM29,%XMM6,%XMM7

0x440748 VFMADD213SD	%XMM29,%XMM3,%XMM7

0x44074e VFMADD213SD	%XMM28,%XMM3,%XMM7

0x440754 VMOVSD	%XMM7,-0x2b0(%RBP)

0x44075c VMULSD	%XMM5,%XMM2,%XMM2

0x440760 VMOVSD	%XMM2,-0x2a8(%RBP)

0x440768 VADDSD	%XMM31,%XMM6,%XMM2

0x44076e VFMADD213SD	%XMM30,%XMM3,%XMM2

0x440774 VMOVSD	%XMM2,-0x1c0(%RBP)

0x44077c VMOVSD	0xbf7b4(%RIP),%XMM7

0x440784 VMULSD	%XMM7,%XMM3,%XMM2

0x440788 VMOVSD	0xbc900(%RIP),%XMM11

0x440790 VADDSD	%XMM2,%XMM11,%XMM5

0x440794 VMULSD	%XMM3,%XMM5,%XMM5

0x440798 VMOVSD	%XMM5,-0x1b8(%RBP)

0x4407a0 VSUBSD	%XMM16,%XMM1,%XMM1

0x4407a6 VSUBSD	%XMM2,%XMM31,%XMM2

0x4407ac VFMADD213SD	%XMM29,%XMM3,%XMM2

0x4407b2 VMOVSD	%XMM2,-0x1b0(%RBP)

0x4407ba VSHUFPD	$0x1,%XMM4,%XMM4,%XMM2

0x4407bf VMULSD	%XMM3,%XMM2,%XMM2

0x4407c3 VMOVSD	%XMM2,-0x1a8(%RBP)

0x4407cb VMOVSD	0xbdb15(%RIP),%XMM12

0x4407d3 VMULSD	%XMM3,%XMM12,%XMM2

0x4407d7 VMOVDDUP	%XMM2,%XMM4

0x4407db VSUBSD	%XMM3,%XMM31,%XMM5

0x4407e1 VMOVUPD	-0x1d0(%RBP),%XMM13

0x4407e9 VADDSD	%XMM4,%XMM13,%XMM4

0x4407ed VMOVDDUP	%XMM4,%XMM4

0x4407f1 VBLENDPD	$0x1,%XMM5,%XMM4,%XMM4

0x4407f7 VMOVUPD	%XMM4,-0x280(%RBP)

0x4407ff VSUBSD	%XMM2,%XMM31,%XMM2

0x440805 VMOVSD	%XMM2,-0x270(%RBP)

0x44080d VMOVSD	%XMM3,-0x268(%RBP)

0x440815 VMULSD	%XMM28,%XMM1,%XMM2

0x44081b VSUBSD	%XMM2,%XMM29,%XMM3

0x440821 VMULSD	%XMM1,%XMM1,%XMM4

0x440825 VMOVDDUP	%XMM1,%XMM5

0x440829 VBLENDPD	$0x1,%XMM3,%XMM8,%XMM3

0x44082f VMULPD	%XMM3,%XMM5,%XMM3

0x440833 VADDPD	%XMM3,%XMM9,%XMM6

0x440837 VPUNPCKLQDQ	%XMM4,%XMM5,%XMM5

0x44083b VFMADD213PD	%XMM10,%XMM6,%XMM5

0x440840 VMOVUPD	%XMM5,-0x2a0(%RBP)

0x440848 VMULSD	%XMM30,%XMM1,%XMM5

0x44084e VADDSD	%XMM29,%XMM5,%XMM6

0x440854 VFMADD213SD	%XMM29,%XMM1,%XMM6

0x44085a VFMADD213SD	%XMM28,%XMM1,%XMM6

0x440860 VMOVSD	%XMM6,-0x290(%RBP)

0x440868 VMULSD	%XMM4,%XMM2,%XMM2

0x44086c VMOVSD	%XMM2,-0x288(%RBP)

0x440874 VADDSD	%XMM31,%XMM5,%XMM2

0x44087a VFMADD213SD	%XMM30,%XMM1,%XMM2

0x440880 VMOVSD	%XMM2,-0x1a0(%RBP)

0x440888 VMULSD	%XMM7,%XMM1,%XMM2

0x44088c VADDSD	%XMM2,%XMM11,%XMM4

0x440890 VMULSD	%XMM1,%XMM4,%XMM4

0x440894 VMOVSD	%XMM4,-0x198(%RBP)

0x44089c VSUBSD	%XMM2,%XMM31,%XMM2

0x4408a2 VFMADD213SD	%XMM29,%XMM1,%XMM2

0x4408a8 VMOVSD	%XMM2,-0x190(%RBP)

0x4408b0 VSHUFPD	$0x1,%XMM3,%XMM3,%XMM2

0x4408b5 VMULSD	%XMM1,%XMM2,%XMM2

0x4408b9 VMOVSD	%XMM2,-0x188(%RBP)

0x4408c1 VMULSD	%XMM1,%XMM12,%XMM2

0x4408c5 VMOVDDUP	%XMM2,%XMM3

0x4408c9 VSUBSD	%XMM1,%XMM31,%XMM4

0x4408cf VADDSD	%XMM3,%XMM13,%XMM3

0x4408d3 VMOVDDUP	%XMM3,%XMM3

0x4408d7 VBLENDPD	$0x1,%XMM4,%XMM3,%XMM3

0x4408dd VMOVUPD	%XMM3,-0x260(%RBP)

0x4408e5 VSUBSD	%XMM2,%XMM31,%XMM2

0x4408eb VMOVSD	%XMM2,-0x250(%RBP)

0x4408f3 VSUBSD	%XMM17,%XMM0,%XMM8

0x4408f9 VMOVSD	%XMM1,-0x248(%RBP)

0x440901 VMULSD	%XMM29,%XMM8,%XMM12

0x440907 VADDSD	0xbf619(%RIP),%XMM12,%XMM13

0x44090f VMULSD	%XMM8,%XMM8,%XMM14

0x440914 VFMADD213SD	0xbf613(%RIP),%XMM14,%XMM13

0x44091d MOV	0x10(%RSI),%RAX

0x440921 MOV	%RAX,-0xd0(%RBP)

0x440928 MOV	0x18(%RSI),%RAX

0x44092c MOV	%RAX,-0xa0(%RBP)

0x440933 MOV	0x20(%RSI),%RAX

0x440937 MOV	%RAX,-0x38(%RBP)

0x44093b MOV	%RSI,-0xa8(%RBP)

0x440942 MOVSXD	0xe8(%RSI),%RCX

0x440949 TEST	%R12,%R12

0x44094c MOV	%RCX,-0x30(%RBP)

0x440950 JE	440ad0

0x440956 MOV	%R14,%RDI

0x440959 XOR	%ESI,%ESI

0x44095b MOV	%R12,%RDX

0x44095e MOV	%R9,-0x60(%RBP)

0x440962 VMOVUPD	%XMM8,-0xc0(%RBP)

0x44096a VMOVUPD	%XMM12,-0x100(%RBP)

0x440972 VMOVUPD	%XMM13,-0xf0(%RBP)

0x44097a VMOVSD	%XMM14,-0x70(%RBP)

0x44097f VMOVSD	%XMM15,-0x68(%RBP)

0x440984 VMOVSD	%XMM16,-0x58(%RBP)

0x44098b VMOVSD	%XMM17,-0x50(%RBP)

0x440992 VZEROUPPER

0x440995 CALL	4efda0 <_intel_fast_memset>

0x44099a MOV	%RBX,%RDI

0x44099d XOR	%ESI,%ESI

0x44099f MOV	%R12,%RDX

0x4409a2 CALL	4efda0 <_intel_fast_memset>

0x4409a7 MOV	-0x30(%RBP),%RAX

0x4409ab LEA	(%RBX,%RAX,8),%RDI

0x4409af XOR	%ESI,%ESI

0x4409b1 MOV	%R12,%RDX

0x4409b4 CALL	4efda0 <_intel_fast_memset>

0x4409b9 MOV	-0x30(%RBP),%RAX

0x4409bd ADD	%RAX,%RAX

0x4409c0 MOV	%RAX,-0x98(%RBP)

0x4409c7 MOV	-0x30(%RBP),%R15

0x4409cb SAL	$0x4,%R15

0x4409cf LEA	(%RBX,%R15,1),%RDI

0x4409d3 XOR	%ESI,%ESI

0x4409d5 MOV	%R12,%RDX

0x4409d8 CALL	4efda0 <_intel_fast_memset>

0x4409dd MOV	%R13,%RDI

0x4409e0 XOR	%ESI,%ESI

0x4409e2 MOV	%R12,%RDX

0x4409e5 CALL	4efda0 <_intel_fast_memset>

0x4409ea MOV	-0x30(%RBP),%RAX

0x4409ee LEA	(%R13,%RAX,8),%RDI

0x4409f3 XOR	%ESI,%ESI

0x4409f5 MOV	%R12,%RDX

0x4409f8 CALL	4efda0 <_intel_fast_memset>

0x4409fd ADD	%R13,%R15

0x440a00 MOV	%R15,%RDI

0x440a03 XOR	%ESI,%ESI

0x440a05 MOV	%R12,%RDX

0x440a08 CALL	4efda0 <_intel_fast_memset>

0x440a0d MOV	-0x30(%RBP),%RAX

0x440a11 LEA	(%RAX,%RAX,2),%RAX

0x440a15 MOV	%RAX,-0x88(%RBP)

0x440a1c LEA	(%R13,%RAX,8),%RDI

0x440a21 XOR	%ESI,%ESI

0x440a23 MOV	%R12,%RDX

0x440a26 CALL	4efda0 <_intel_fast_memset>

0x440a2b MOV	-0x30(%RBP),%RAX

0x440a2f LEA	(,%RAX,4),%RAX

0x440a37 MOV	%RAX,-0x90(%RBP)

0x440a3e MOV	-0x30(%RBP),%RDI

0x440a42 SAL	$0x5,%RDI

0x440a46 ADD	%R13,%RDI

0x440a49 XOR	%ESI,%ESI

0x440a4b MOV	%R12,%RDX

0x440a4e CALL	4efda0 <_intel_fast_memset>

0x440a53 MOV	-0x30(%RBP),%RAX

0x440a57 LEA	(%RAX,%RAX,4),%RAX

0x440a5b MOV	%RAX,-0x80(%RBP)

0x440a5f LEA	(%R13,%RAX,8),%RDI

0x440a64 XOR	%ESI,%ESI

0x440a66 MOV	%R12,%RDX

0x440a69 CALL	4efda0 <_intel_fast_memset>

0x440a6e VMOVSD	-0x50(%RBP),%XMM17

0x440a75 VMOVSD	-0x58(%RBP),%XMM16

0x440a7c VMOVSD	-0x68(%RBP),%XMM15

0x440a81 VMOVSD	-0x70(%RBP),%XMM14

0x440a86 VMOVUPD	-0xf0(%RBP),%XMM13

0x440a8e VMOVUPD	-0x100(%RBP),%XMM12

0x440a96 VMOVUPD	-0xc0(%RBP),%XMM8

0x440a9e MOV	-0x60(%RBP),%R9

0x440aa2 VMOVSD	0xbc594(%RIP),%XMM31

0x440aac VMOVSD	0xbc582(%RIP),%XMM30

0x440ab6 VMOVSD	0xbc560(%RIP),%XMM29

0x440ac0 VMOVSD	0xbf456(%RIP),%XMM28

0x440aca MOV	-0x78(%RBP),%RDI

0x440ace JMP	440afd

0x440ad0 LEA	(%RCX,%RCX,1),%RAX

0x440ad4 MOV	%RAX,-0x98(%RBP)

0x440adb LEA	(%RCX,%RCX,2),%RAX

0x440adf MOV	%RAX,-0x88(%RBP)

0x440ae6 LEA	(,%RCX,4),%RAX

0x440aee MOV	%RAX,-0x90(%RBP)

0x440af5 LEA	(%RCX,%RCX,4),%RAX

0x440af9 MOV	%RAX,-0x80(%RBP)

0x440afd VCVTTSD2SI	%XMM15,%EAX

0x440b02 VCVTTSD2SI	%XMM16,%ECX

0x440b08 VCVTTSD2SI	%XMM17,%EDX

0x440b0e MOV	-0xb0(%RBP),%R8

0x440b15 DEC	%R8

0x440b18 MOV	%EDX,%ESI

0x440b1a SAR	$0x1f,%ESI

0x440b1d ANDN	%EDX,%ESI,%EDX

0x440b22 CMP	%RDX,%R8

0x440b25 CMOVGE	%RDX,%R8

0x440b29 MOV	-0x38(%RBP),%R15

0x440b2d MOV	%R15,%RDX

0x440b30 IMUL	%R8,%RDX

0x440b34 DEC	%R9

0x440b37 MOV	%ECX,%ESI

0x440b39 SAR	$0x1f,%ESI

0x440b3c ANDN	%ECX,%ESI,%ECX

0x440b41 CMP	%RCX,%R9

0x440b44 CMOVGE	%RCX,%R9

0x440b48 MOV	-0xa0(%RBP),%RSI

0x440b4f MOV	%RSI,%R10

0x440b52 IMUL	%R9,%R10

0x440b56 MOV	-0x40(%RBP),%R11

0x440b5a DEC	%R11

0x440b5d MOV	%EAX,%ECX

0x440b5f SAR	$0x1f,%ECX

0x440b62 ANDN	%EAX,%ECX,%EAX

0x440b67 CMP	%RAX,%R11

0x440b6a CMOVGE	%RAX,%R11

0x440b6e MOV	-0xd0(%RBP),%RCX

0x440b75 MOV	%RCX,%RAX

0x440b78 IMUL	%R11,%RAX

0x440b7c LEA	(%R15,%R15,2),%R12

0x440b80 MOV	%R12,-0xc0(%RBP)

0x440b87 ADD	%RDX,%R10

0x440b8a ADD	%RAX,%R10

0x440b8d LEA	(%R10,%R15,1),%RAX

0x440b91 MOV	%RAX,-0xf0(%RBP)

0x440b98 LEA	(%R10,%R15,2),%RAX

0x440b9c MOV	%RAX,-0x70(%RBP)

0x440ba0 LEA	(,%RSI,8),%RAX

0x440ba8 MOV	%RAX,-0xb0(%RBP)

0x440baf IMUL	%RAX,%R9

0x440bb3 LEA	(,%RCX,8),%RAX

0x440bbb MOV	%RAX,-0x168(%RBP)

0x440bc2 IMUL	%RAX,%R11

0x440bc6 LEA	(%R9,%R11,1),%RAX

0x440bca SAL	$0x3,%R15

0x440bce LEA	0x3(%R8),%R12

0x440bd2 IMUL	%R15,%R12

0x440bd6 ADD	%RAX,%R12

0x440bd9 LEA	0x2(%R8),%RSI

0x440bdd IMUL	%R15,%RSI

0x440be1 ADD	%RAX,%RSI

0x440be4 LEA	0x1(%R8),%RDX

0x440be8 IMUL	%R15,%RDX

0x440bec ADD	%RAX,%RDX

0x440bef VMULSD	%XMM28,%XMM8,%XMM0

0x440bf5 VSUBSD	%XMM0,%XMM29,%XMM1

0x440bfb VFMADD213SD	%XMM30,%XMM8,%XMM1

0x440c01 VFMADD213SD	%XMM28,%XMM8,%XMM1

0x440c07 VMULSD	%XMM30,%XMM8,%XMM2

0x440c0d VADDSD	%XMM29,%XMM2,%XMM3

0x440c13 VFMADD213SD	%XMM29,%XMM8,%XMM3

0x440c19 VFMADD213SD	%XMM28,%XMM8,%XMM3

0x440c1f VADDSD	%XMM31,%XMM2,%XMM4

0x440c25 VFMADD213SD	%XMM30,%XMM8,%XMM4

0x440c2b VMULSD	0xbf305(%RIP),%XMM8,%XMM2

0x440c33 VMOVSD	0xbc455(%RIP),%XMM7

0x440c3b VADDSD	%XMM7,%XMM2,%XMM5

0x440c3f VSUBSD	%XMM2,%XMM31,%XMM6

0x440c45 VFMADD213SD	%XMM29,%XMM8,%XMM6

0x440c4b VSUBSD	%XMM8,%XMM31,%XMM9

0x440c51 VMULSD	0xbd68f(%RIP),%XMM8,%XMM2

0x440c59 VADDSD	%XMM7,%XMM2,%XMM10

0x440c5d VSUBSD	%XMM2,%XMM31,%XMM11

0x440c63 MOV	-0xa8(%RBP),%RAX

0x440c6a MOV	0x8(%RAX),%RCX

0x440c6e VMULSD	%XMM0,%XMM14,%XMM7

0x440c72 VBROADCASTSD	%XMM1,%YMM0

0x440c77 VBROADCASTSD	%XMM13,%YMM1

0x440c7c VBROADCASTSD	%XMM3,%YMM2

0x440c81 VBROADCASTSD	%XMM7,%YMM3

0x440c86 VBROADCASTSD	%XMM4,%YMM4

0x440c8b VBROADCASTSD	%XMM5,%YMM5

0x440c90 VBROADCASTSD	%XMM6,%YMM6

0x440c95 VBROADCASTSD	%XMM12,%YMM7

0x440c9a VBROADCASTSD	%XMM8,%YMM8

0x440c9f VBROADCASTSD	%XMM9,%YMM9

0x440ca4 VBROADCASTSD	%XMM10,%YMM10

0x440ca9 VBROADCASTSD	%XMM11,%YMM11

0x440cae MOV	%R10,-0x100(%RBP)

0x440cb5 MOV	-0xc0(%RBP),%RAX

0x440cbc ADD	%R10,%RAX

0x440cbf MOV	%RAX,-0xc0(%RBP)

0x440cc6 IMUL	%R8,%R15

0x440cca MOV	-0x30(%RBP),%R8

0x440cce MOV	%R8,%RAX

0x440cd1 SAL	$0x4,%RAX

0x440cd5 ADD	%R11,%R15

0x440cd8 MOV	%RAX,-0x150(%RBP)

0x440cdf LEA	(%RBX,%RAX,1),%R10

0x440ce3 ADD	%RCX,%R9

0x440ce6 ADD	%R15,%R9

0x440ce9 LEA	(,%R8,8),%R11

0x440cf1 ADD	%RCX,%R12

0x440cf4 ADD	%RCX,%RSI

0x440cf7 MOV	%RCX,-0x68(%RBP)

0x440cfb ADD	%RCX,%RDX

0x440cfe LEA	(%RBX,%R8,8),%R8

0x440d02 XOR	%EAX,%EAX

0x440d04 MOV	%RBX,-0x180(%RBP)

0x440d0b JMP	440d4b

  (925) 0x440d10 MOV	-0x170(%RBP),%R15

  (925) 0x440d17 LEA	0x1(%R15),%RAX

  (925) 0x440d1b MOV	-0x168(%RBP),%RCX

  (925) 0x440d22 MOV	-0x58(%RBP),%R12

  (925) 0x440d26 ADD	%RCX,%R12

  (925) 0x440d29 MOV	-0x50(%RBP),%RSI

  (925) 0x440d2d ADD	%RCX,%RSI

  (925) 0x440d30 MOV	-0x178(%RBP),%RDX

  (925) 0x440d37 ADD	%RCX,%RDX

  (925) 0x440d3a MOV	-0x60(%RBP),%R9

  (925) 0x440d3e ADD	%RCX,%R9

  (925) 0x440d41 CMP	$0x3,%R15

  (925) 0x440d45 JE	4411d0

  (925) 0x440d4b VMOVSD	-0x280(%RBP,%RAX,8),%XMM12

  (925) 0x440d54 VMOVSD	-0x1c0(%RBP,%RAX,8),%XMM13

  (925) 0x440d5d VMOVSD	-0x2c0(%RBP,%RAX,8),%XMM14

  (925) 0x440d66 MOV	-0xd0(%RBP),%RCX

  (925) 0x440d6d MOV	%RAX,-0x170(%RBP)

  (925) 0x440d74 IMUL	%RAX,%RCX

  (925) 0x440d78 MOV	%RCX,-0x38(%RBP)

  (925) 0x440d7c MOV	%R9,-0x60(%RBP)

  (925) 0x440d80 MOV	%R9,%RCX

  (925) 0x440d83 MOV	%RDX,-0x178(%RBP)

  (925) 0x440d8a MOV	%RSI,-0x50(%RBP)

  (925) 0x440d8e MOV	%R12,-0x58(%RBP)

  (925) 0x440d92 MOV	%R12,%R15

  (925) 0x440d95 XOR	%R9D,%R9D

  (925) 0x440d98 JMP	440fdf

    (926) 0x440da0 MOV	-0xa0(%RBP),%RAX

    (926) 0x440da7 IMUL	%R9,%RAX

    (926) 0x440dab ADD	-0x38(%RBP),%RAX

    (926) 0x440daf MOV	%RAX,-0x40(%RBP)

    (926) 0x440db3 VBROADCASTSD	%XMM17,%YMM20

    (926) 0x440db9 VBROADCASTSD	%XMM19,%YMM19

    (926) 0x440dbf VBROADCASTSD	%XMM16,%YMM17

    (926) 0x440dc5 VBROADCASTSD	%XMM18,%YMM18

    (926) 0x440dcb VBROADCASTSD	%XMM21,%YMM16

    (926) 0x440dd1 VBROADCASTSD	%XMM15,%YMM15

    (926) 0x440dd6 XOR	%R12D,%R12D

    (926) 0x440dd9 MOV	-0xd8(%RBP),%RDI

    (926) 0x440de0 SUB	%R12,%RDI

    (926) 0x440de3 VPBROADCASTQ	%RDI,%YMM21

    (926) 0x440de9 VPCMPGTQ	0xbd5ed(%RIP),%YMM21,%K1

    (926) 0x440df3 MOV	-0x100(%RBP),%RAX

    (926) 0x440dfa LEA	(%RAX,%R12,1),%RDI

    (926) 0x440dfe MOV	-0x40(%RBP),%RBX

    (926) 0x440e02 ADD	%RBX,%RDI

    (926) 0x440e05 MOV	%R9,-0xa8(%RBP)

    (926) 0x440e0c MOV	-0x68(%RBP),%R9

    (926) 0x440e10 VMOVUPD	(%R9,%RDI,8),%YMM22{%K1}{z}

    (926) 0x440e17 MOV	-0xf0(%RBP),%RAX

    (926) 0x440e1e LEA	(%RAX,%R12,1),%RDI

    (926) 0x440e22 ADD	%RBX,%RDI

    (926) 0x440e25 VMOVUPD	(%R9,%RDI,8),%YMM23{%K1}{z}

    (926) 0x440e2c MOV	-0x70(%RBP),%RAX

    (926) 0x440e30 LEA	(%RAX,%R12,1),%RDI

    (926) 0x440e34 ADD	%RBX,%RDI

    (926) 0x440e37 VMOVUPD	(%R9,%RDI,8),%YMM24{%K1}{z}

    (926) 0x440e3e MOV	-0xc0(%RBP),%RAX

    (926) 0x440e45 LEA	(%RAX,%R12,1),%RDI

    (926) 0x440e49 ADD	%RBX,%RDI

    (926) 0x440e4c MOV	-0x180(%RBP),%RBX

    (926) 0x440e53 VMOVUPD	(%R9,%RDI,8),%YMM25{%K1}{z}

    (926) 0x440e5a VMULPD	%YMM0,%YMM22,%YMM21

    (926) 0x440e60 VFMADD231PD	%YMM1,%YMM23,%YMM21

    (926) 0x440e66 VFMADD231PD	%YMM2,%YMM24,%YMM21

    (926) 0x440e6c VFMADD231PD	%YMM25,%YMM3,%YMM21

    (926) 0x440e72 VMULPD	%YMM4,%YMM22,%YMM26

    (926) 0x440e78 VMULPD	%YMM5,%YMM23,%YMM27

    (926) 0x440e7e VFMADD231PD	%YMM7,%YMM25,%YMM27

    (926) 0x440e84 VFMADD231PD	%YMM6,%YMM24,%YMM26

    (926) 0x440e8a VFMADD231PD	%YMM27,%YMM8,%YMM26

    (926) 0x440e90 VMULPD	%YMM9,%YMM22,%YMM22

    (926) 0x440e96 VFMADD231PD	%YMM23,%YMM10,%YMM22

    (926) 0x440e9c VFMADD231PD	%YMM24,%YMM11,%YMM22

    (926) 0x440ea2 VFMADD231PD	%YMM25,%YMM8,%YMM22

    (926) 0x440ea8 VMOVUPD	(%R13,%R12,8),%YMM23{%K1}{z}

    (926) 0x440eb0 VFMADD231PD	%YMM20,%YMM21,%YMM23

    (926) 0x440eb6 VMOVUPD	%YMM23,(%R13,%R12,8){%K1}

    (926) 0x440ebe MOV	-0x30(%RBP),%RAX

    (926) 0x440ec2 LEA	(%RAX,%R12,1),%R9

    (926) 0x440ec6 VMOVUPD	(%R13,%R9,8),%YMM20{%K1}{z}

    (926) 0x440ece VFMADD231PD	%YMM19,%YMM21,%YMM20

    (926) 0x440ed4 VMOVUPD	%YMM20,(%R13,%R9,8){%K1}

    (926) 0x440edc MOV	-0x98(%RBP),%RAX

    (926) 0x440ee3 LEA	(%RAX,%R12,1),%RDI

    (926) 0x440ee7 VMOVUPD	(%R13,%RDI,8),%YMM19{%K1}{z}

    (926) 0x440eef VFMADD231PD	%YMM17,%YMM26,%YMM19

    (926) 0x440ef5 VMOVUPD	%YMM19,(%R13,%RDI,8){%K1}

    (926) 0x440efd MOV	-0x88(%RBP),%RAX

    (926) 0x440f04 LEA	(%RAX,%R12,1),%RAX

    (926) 0x440f08 VMOVUPD	(%R13,%RAX,8),%YMM19{%K1}{z}

    (926) 0x440f10 VFMADD231PD	%YMM18,%YMM21,%YMM19

    (926) 0x440f16 VMOVUPD	%YMM19,(%R13,%RAX,8){%K1}

    (926) 0x440f1e MOV	-0x90(%RBP),%RAX

    (926) 0x440f25 LEA	(%RAX,%R12,1),%RAX

    (926) 0x440f29 VMOVUPD	(%R13,%RAX,8),%YMM18{%K1}{z}

    (926) 0x440f31 VFMADD231PD	%YMM16,%YMM26,%YMM18

    (926) 0x440f37 VMOVUPD	%YMM18,(%R13,%RAX,8){%K1}

    (926) 0x440f3f MOV	-0x80(%RBP),%RAX

    (926) 0x440f43 LEA	(%RAX,%R12,1),%RAX

    (926) 0x440f47 VMOVUPD	(%R13,%RAX,8),%YMM18{%K1}{z}

    (926) 0x440f4f VFMADD231PD	%YMM22,%YMM15,%YMM18

    (926) 0x440f55 VMOVUPD	%YMM18,(%R13,%RAX,8){%K1}

    (926) 0x440f5d VMOVUPD	(%RBX,%R12,8),%YMM18{%K1}{z}

    (926) 0x440f64 VFMADD231PD	%YMM17,%YMM21,%YMM18

    (926) 0x440f6a VMOVUPD	%YMM18,(%RBX,%R12,8){%K1}

    (926) 0x440f71 VMOVUPD	(%RBX,%R9,8),%YMM17{%K1}{z}

    (926) 0x440f78 VFMADD231PD	%YMM16,%YMM21,%YMM17

    (926) 0x440f7e VMOVUPD	%YMM17,(%RBX,%R9,8){%K1}

    (926) 0x440f85 MOV	-0xa8(%RBP),%R9

    (926) 0x440f8c VMOVUPD	(%RBX,%RDI,8),%YMM16{%K1}{z}

    (926) 0x440f93 VFMADD231PD	%YMM26,%YMM15,%YMM16

    (926) 0x440f99 VMOVUPD	%YMM16,(%RBX,%RDI,8){%K1}

    (926) 0x440fa0 MOV	-0x78(%RBP),%RDI

    (926) 0x440fa4 VMOVUPD	(%R14,%R12,8),%YMM16{%K1}{z}

    (926) 0x440fab VFMADD231PD	%YMM21,%YMM15,%YMM16

    (926) 0x440fb1 VMOVUPD	%YMM16,(%R14,%R12,8){%K1}

    (926) 0x440fb8 LEA	0x1(%R9),%RAX

    (926) 0x440fbc MOV	%R9,%R12

    (926) 0x440fbf MOV	-0xb0(%RBP),%R9

    (926) 0x440fc6 ADD	%R9,%R15

    (926) 0x440fc9 ADD	%R9,%RSI

    (926) 0x440fcc ADD	%R9,%RDX

    (926) 0x440fcf ADD	%R9,%RCX

    (926) 0x440fd2 CMP	$0x3,%R12

    (926) 0x440fd6 MOV	%RAX,%R9

    (926) 0x440fd9 JE	440d10

    (926) 0x440fdf TEST	%EDI,%EDI

    (926) 0x440fe1 JLE	440fb8

    (926) 0x440fe3 VMOVSD	-0x2a0(%RBP,%R9,8),%XMM15

    (926) 0x440fed VMULSD	%XMM12,%XMM15,%XMM17

    (926) 0x440ff3 VMULSD	%XMM13,%XMM15,%XMM16

    (926) 0x440ff9 VMULSD	%XMM14,%XMM15,%XMM15

    (926) 0x440ffe VMOVSD	-0x1a0(%RBP,%R9,8),%XMM18

    (926) 0x441006 VMULSD	%XMM13,%XMM18,%XMM19

    (926) 0x44100c VMULSD	%XMM14,%XMM18,%XMM21

    (926) 0x441012 VMULSD	-0x260(%RBP,%R9,8),%XMM14,%XMM18

    (926) 0x44101a MOV	-0xe0(%RBP),%RAX

    (926) 0x441021 TEST	%RAX,%RAX

    (926) 0x441024 JE	440da0

    (926) 0x44102a VBROADCASTSD	%XMM17,%YMM20

    (926) 0x441030 VBROADCASTSD	%XMM19,%YMM19

    (926) 0x441036 VBROADCASTSD	%XMM16,%YMM17

    (926) 0x44103c VBROADCASTSD	%XMM18,%YMM18

    (926) 0x441042 VBROADCASTSD	%XMM21,%YMM16

    (926) 0x441048 VBROADCASTSD	%XMM15,%YMM15

    (926) 0x44104d MOV	-0xa0(%RBP),%RAX

    (926) 0x441054 IMUL	%R9,%RAX

    (926) 0x441058 ADD	-0x38(%RBP),%RAX

    (926) 0x44105c MOV	%RAX,-0x40(%RBP)

    (926) 0x441060 XOR	%R12D,%R12D

    (926) 0x441063 NOPW	%CS:(%RAX,%RAX,1)

      (927) 0x441070 VMOVUPD	(%RCX,%R12,8),%YMM22

      (927) 0x441077 VMOVUPD	(%RDX,%R12,8),%YMM23

      (927) 0x44107e VMOVUPD	(%RSI,%R12,8),%YMM24

      (927) 0x441085 VMOVUPD	(%R15,%R12,8),%YMM25

      (927) 0x44108c VMULPD	%YMM0,%YMM22,%YMM21

      (927) 0x441092 VFMADD231PD	%YMM1,%YMM23,%YMM21

      (927) 0x441098 VFMADD231PD	%YMM2,%YMM24,%YMM21

      (927) 0x44109e VFMADD231PD	%YMM25,%YMM3,%YMM21

      (927) 0x4410a4 VMULPD	%YMM4,%YMM22,%YMM26

      (927) 0x4410aa VMULPD	%YMM5,%YMM23,%YMM27

      (927) 0x4410b0 VFMADD231PD	%YMM7,%YMM25,%YMM27

      (927) 0x4410b6 VFMADD231PD	%YMM6,%YMM24,%YMM26

      (927) 0x4410bc VFMADD231PD	%YMM27,%YMM8,%YMM26

      (927) 0x4410c2 LEA	(%R13,%R12,8),%RAX

      (927) 0x4410c7 VMOVUPD	(%R13,%R12,8),%YMM27

      (927) 0x4410cf VFMADD231PD	%YMM21,%YMM20,%YMM27

      (927) 0x4410d5 VMOVUPD	%YMM27,(%R13,%R12,8)

      (927) 0x4410dd VMOVUPD	(%R11,%RAX,1),%YMM27

      (927) 0x4410e4 VFMADD231PD	%YMM21,%YMM19,%YMM27

      (927) 0x4410ea VMOVUPD	%YMM27,(%R11,%RAX,1)

      (927) 0x4410f1 VMULPD	%YMM9,%YMM22,%YMM22

      (927) 0x4410f7 LEA	(%RAX,%R11,1),%RAX

      (927) 0x4410fb VMOVUPD	(%R11,%RAX,1),%YMM27

      (927) 0x441102 VFMADD231PD	%YMM17,%YMM26,%YMM27

      (927) 0x441108 VMOVUPD	%YMM27,(%R11,%RAX,1)

      (927) 0x44110f VFMADD231PD	%YMM23,%YMM10,%YMM22

      (927) 0x441115 LEA	(%RAX,%R11,1),%RAX

      (927) 0x441119 VMOVUPD	(%R11,%RAX,1),%YMM23

      (927) 0x441120 VFMADD231PD	%YMM21,%YMM18,%YMM23

      (927) 0x441126 VMOVUPD	%YMM23,(%R11,%RAX,1)

      (927) 0x44112d VFMADD231PD	%YMM24,%YMM11,%YMM22

      (927) 0x441133 LEA	(%RAX,%R11,1),%RAX

      (927) 0x441137 VMOVUPD	(%R11,%RAX,1),%YMM23

      (927) 0x44113e VFMADD231PD	%YMM16,%YMM26,%YMM23

      (927) 0x441144 VMOVUPD	%YMM23,(%R11,%RAX,1)

      (927) 0x44114b VFMADD231PD	%YMM25,%YMM8,%YMM22

      (927) 0x441151 LEA	(%RAX,%R11,1),%RAX

      (927) 0x441155 VFMADD213PD	(%R11,%RAX,1),%YMM15,%YMM22

      (927) 0x44115c VMOVUPD	%YMM22,(%R11,%RAX,1)

      (927) 0x441163 MOV	-0xe0(%RBP),%RAX

      (927) 0x44116a VMOVUPD	(%RBX,%R12,8),%YMM22

      (927) 0x441171 VFMADD231PD	%YMM17,%YMM21,%YMM22

      (927) 0x441177 VMOVUPD	%YMM22,(%RBX,%R12,8)

      (927) 0x44117e VMOVUPD	(%R8,%R12,8),%YMM22

      (927) 0x441185 VFMADD231PD	%YMM16,%YMM21,%YMM22

      (927) 0x44118b VMOVUPD	%YMM22,(%R8,%R12,8)

      (927) 0x441192 VFMADD213PD	(%R10,%R12,8),%YMM15,%YMM26

      (927) 0x441199 VMOVUPD	%YMM26,(%R10,%R12,8)

      (927) 0x4411a0 VFMADD213PD	(%R14,%R12,8),%YMM15,%YMM21

      (927) 0x4411a7 VMOVUPD	%YMM21,(%R14,%R12,8)

      (927) 0x4411ae ADD	$0x4,%R12

      (927) 0x4411b2 CMP	%RAX,%R12

      (927) 0x4411b5 JB	441070

    (926) 0x4411bb MOV	%RAX,%R12

    (926) 0x4411be CMP	-0xd8(%RBP),%EAX

    (926) 0x4411c4 JNE	440dd9

    (926) 0x4411ca JMP	440fb8

0x4411d0 TEST	%EDI,%EDI

0x4411d2 MOV	-0x48(%RBP),%R15

0x4411d6 MOV	-0x128(%RBP),%R12

0x4411dd MOV	-0x120(%RBP),%R9

0x4411e4 JE	440604

0x4411ea VMOVUPD	-0x230(%RBP),%XMM7

0x4411f2 VMOVUPD	-0x220(%RBP),%XMM9

0x4411fa VMULSD	%XMM7,%XMM9,%XMM0

0x4411fe VMOVUPD	-0x240(%RBP),%XMM6

0x441206 VMULSD	%XMM6,%XMM9,%XMM1

0x44120a VMULSD	%XMM6,%XMM7,%XMM2

0x44120e VMULSD	%XMM9,%XMM9,%XMM3

0x441213 VMULSD	%XMM7,%XMM7,%XMM4

0x441217 VMULSD	%XMM6,%XMM6,%XMM5

0x44121b VBROADCASTSD	%XMM6,%YMM8

0x441220 VBROADCASTSD	%XMM7,%YMM7

0x441225 VBROADCASTSD	%XMM9,%YMM6

0x44122a VBROADCASTSD	%XMM5,%YMM5

0x44122f VBROADCASTSD	%XMM4,%YMM4

0x441234 VBROADCASTSD	%XMM3,%YMM3

0x441239 VBROADCASTSD	%XMM2,%YMM2

0x44123e VBROADCASTSD	%XMM1,%YMM1

0x441243 VBROADCASTSD	%XMM0,%YMM0

0x441248 TEST	%R9,%R9

0x44124b JE	440510

0x441251 MOV	-0x30(%RBP),%RSI

0x441255 MOV	%RSI,%RAX

0x441258 SAL	$0x5,%RAX

0x44125c ADD	%R13,%RAX

0x44125f LEA	(%RSI,%RSI,4),%RCX

0x441263 LEA	(%R13,%RCX,8),%RCX

0x441268 LEA	(%RSI,%RSI,2),%RDX

0x44126c LEA	(%R13,%RDX,8),%RDX

0x441271 MOV	-0x150(%RBP),%R11

0x441278 ADD	%R13,%R11

0x44127b LEA	(%R13,%RSI,8),%RSI

0x441280 XOR	%EDI,%EDI

0x441282 NOPW	%CS:(%RAX,%RAX,1)

  (924) 0x441290 VMULPD	(%RBX,%RDI,8),%YMM8,%YMM9

  (924) 0x441295 VMOVUPD	%YMM9,(%RBX,%RDI,8)

  (924) 0x44129a VMULPD	(%R8,%RDI,8),%YMM7,%YMM9

  (924) 0x4412a0 VMOVUPD	%YMM9,(%R8,%RDI,8)

  (924) 0x4412a6 VMULPD	(%R10,%RDI,8),%YMM6,%YMM9

  (924) 0x4412ac VMOVUPD	%YMM9,(%R10,%RDI,8)

  (924) 0x4412b2 VMULPD	(%R13,%RDI,8),%YMM5,%YMM9

  (924) 0x4412b9 VMOVUPD	%YMM9,(%R13,%RDI,8)

  (924) 0x4412c0 VMULPD	(%RDX,%RDI,8),%YMM4,%YMM9

  (924) 0x4412c5 VMOVUPD	%YMM9,(%RDX,%RDI,8)

  (924) 0x4412ca VMULPD	(%RCX,%RDI,8),%YMM3,%YMM9

  (924) 0x4412cf VMOVUPD	%YMM9,(%RCX,%RDI,8)

  (924) 0x4412d4 VMULPD	(%RSI,%RDI,8),%YMM2,%YMM9

  (924) 0x4412d9 VMOVUPD	%YMM9,(%RSI,%RDI,8)

  (924) 0x4412de VMULPD	(%R11,%RDI,8),%YMM1,%YMM9

  (924) 0x4412e4 VMOVUPD	%YMM9,(%R11,%RDI,8)

  (924) 0x4412ea VMULPD	(%RAX,%RDI,8),%YMM0,%YMM9

  (924) 0x4412ef VMOVUPD	%YMM9,(%RAX,%RDI,8)

  (924) 0x4412f4 ADD	$0x4,%RDI

  (924) 0x4412f8 CMP	%R9,%RDI

  (924) 0x4412fb JL	441290

0x4412fd MOV	%R9,%RAX

0x441300 MOV	-0x78(%RBP),%RDI

0x441304 CMP	%RDI,%R9

0x441307 JNE	440512

0x44130d JMP	440604

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 265 - 265

--------------------------------------------------------------------------------

265:   inline T* data() { return myData; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 206 - 207

--------------------------------------------------------------------------------

206:     for (int i = 0; i < nBlocks; ++i)

207:       MultiBsplineEvalRef::evaluate_vgh(einsplines[i], u[0], u[1], u[2], psi[i].data(), grad[i].data(), hess[i].data(),

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 924

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 61 - 61

--------------------------------------------------------------------------------

61:     for (size_t d = 0; d < D; ++d)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 45 - 47

--------------------------------------------------------------------------------

45:   T sf = std::floor(x);

46:   T dx2 = x - sf;

47:   int ind2 = std::min(std::max(0, static_cast<int>(sf)), nmax);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 68 - 79

--------------------------------------------------------------------------------

68:     a[0]   = ((A00 * tx + A01) * tx + A02) * tx + A03;

69:     a[1]   = ((A10 * tx + A11) * tx + A12) * tx + A13;

70:     a[2]   = ((A20 * tx + A21) * tx + A22) * tx + A23;

71:     a[3]   = ((A30 * tx + A31) * tx + A32) * tx + A33;

72:     da[0]  = (dA01 * tx + dA02) * tx + dA03;

73:     da[1]  = (dA11 * tx + dA12) * tx + dA13;

74:     da[2]  = (dA21 * tx + dA22) * tx + dA23;

75:     da[3]  = (dA31 * tx + dA32) * tx + dA33;

76:     d2a[0] = d2A02 * tx + d2A03;

77:     d2a[1] = d2A12 * tx + d2A13;

78:     d2a[2] = d2A22 * tx + d2A23;

79:     d2a[3] = d2A32 * tx + d2A33;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 187 - 286

--------------------------------------------------------------------------------

187:   x -= spline_m->x_grid.start;

188:   y -= spline_m->y_grid.start;

189:   z -= spline_m->z_grid.start;

190:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

191:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

192:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

198:   const intptr_t xs = spline_m->x_stride;

199:   const intptr_t ys = spline_m->y_stride;

200:   const intptr_t zs = spline_m->z_stride;

201:

202:   const size_t out_offset = spline_m->num_splines;

[...]

226:   for (int i = 0; i < 4; i++)

227:     for (int j = 0; j < 4; j++)

228:     {

229:       const T* restrict coefs    = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

230:       const T* restrict coefszs  = coefs + zs;

231:       const T* restrict coefs2zs = coefs + 2 * zs;

232:       const T* restrict coefs3zs = coefs + 3 * zs;

233:

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

[...]

269:   const T dxx   = dxInv * dxInv;

270:   const T dyy   = dyInv * dyInv;

271:   const T dzz   = dzInv * dzInv;

272:   const T dxy   = dxInv * dyInv;

273:   const T dxz   = dxInv * dzInv;

274:   const T dyz   = dyInv * dzInv;

275:

276:   for (int n = 0; n < num_splines; n++)

277:   {

278:     gx[n] *= dxInv;

279:     gy[n] *= dyInv;

280:     gz[n] *= dzInv;

281:     hxx[n] *= dxx;

282:     hyy[n] *= dyy;

283:     hzz[n] *= dzz;

284:     hxy[n] *= dxy;

285:     hxz[n] *= dxz;

286:     hyz[n] *= dyz;

Coverage (%)	Name	Source Location	Module
►94.11+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►3.34+	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.extracted.112	miniqmc.cpp:397	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►2.55+	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.extracted.112	miniqmc.cpp:397	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	2.21
CQA speedup if fully vectorized	7.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	micro-operation queue,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	VectorSoAContainer.h:265-265,einspline_spo_ref.hpp:206-207,stl_vector.h:1046-1046,stl_vector.h:1169-1169,stl_algobase.h:923-924,TinyVector.h:61-61,MultiBsplineEvalHelper.hpp:45-47,MultiBsplineData.hpp:68-79,MultiBsplineRef.hpp:187-192,MultiBsplineRef.hpp:198-202,MultiBsplineRef.hpp:229-229,MultiBsplineRef.hpp:244-251,MultiBsplineRef.hpp:255-258,MultiBsplineRef.hpp:269-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	74.67
CQA cycles if no scalar integer	47.50
CQA cycles if FP arith vectorized	33.71
CQA cycles if fully vectorized	9.91
Front-end cycles	74.67
P0 cycles	50.00
P1 cycles	50.17
P2 cycles	30.33
P3 cycles	30.33
P4 cycles	38.00
P5 cycles	49.83
P6 cycles	25.00
P7 cycles	38.00
P8 cycles	38.00
P9 cycles	38.00
P10 cycles	25.00
P11 cycles	30.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	432.00
Nb uops	448.00
Nb loads	92.00
Nb stores	66.00
Nb stack references	60.00
FLOP/cycle	1.94
Nb FLOP add-sub	35.00
Nb FLOP mul	72.00
Nb FLOP fma	19.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.29
Bytes prefetched	0.00
Bytes loaded	1064.00
Bytes stored	824.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.40
Vectorization ratio load	47.92
Vectorization ratio store	28.79
Vectorization ratio mul	25.00
Vectorization ratio add_sub	5.71
Vectorization ratio fma	11.76
Vectorization ratio div_sqrt	NA
Vectorization ratio other	15.69
Vector-efficiency ratio all	18.43
Vector-efficiency ratio load	23.70
Vector-efficiency ratio store	19.51
Vector-efficiency ratio mul	20.74
Vector-efficiency ratio add_sub	13.21
Vector-efficiency ratio fma	13.97
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.83

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	2.21
CQA speedup if fully vectorized	7.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	micro-operation queue,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	VectorSoAContainer.h:265-265,einspline_spo_ref.hpp:206-207,stl_vector.h:1046-1046,stl_vector.h:1169-1169,stl_algobase.h:923-924,TinyVector.h:61-61,MultiBsplineEvalHelper.hpp:45-47,MultiBsplineData.hpp:68-79,MultiBsplineRef.hpp:187-192,MultiBsplineRef.hpp:198-202,MultiBsplineRef.hpp:229-229,MultiBsplineRef.hpp:244-251,MultiBsplineRef.hpp:255-258,MultiBsplineRef.hpp:269-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	74.67
CQA cycles if no scalar integer	47.50
CQA cycles if FP arith vectorized	33.71
CQA cycles if fully vectorized	9.91
Front-end cycles	74.67
P0 cycles	50.00
P1 cycles	50.17
P2 cycles	30.33
P3 cycles	30.33
P4 cycles	38.00
P5 cycles	49.83
P6 cycles	25.00
P7 cycles	38.00
P8 cycles	38.00
P9 cycles	38.00
P10 cycles	25.00
P11 cycles	30.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	432.00
Nb uops	448.00
Nb loads	92.00
Nb stores	66.00
Nb stack references	60.00
FLOP/cycle	1.94
Nb FLOP add-sub	35.00
Nb FLOP mul	72.00
Nb FLOP fma	19.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.29
Bytes prefetched	0.00
Bytes loaded	1064.00
Bytes stored	824.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.40
Vectorization ratio load	47.92
Vectorization ratio store	28.79
Vectorization ratio mul	25.00
Vectorization ratio add_sub	5.71
Vectorization ratio fma	11.76
Vectorization ratio div_sqrt	NA
Vectorization ratio other	15.69
Vector-efficiency ratio all	18.43
Vector-efficiency ratio load	23.70
Vector-efficiency ratio store	19.51
Vector-efficiency ratio mul	20.74
Vector-efficiency ratio add_sub	13.21
Vector-efficiency ratio fma	13.97
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:187-286
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:265
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:206-207
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,198-202,226-262,269-286

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=32
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 32 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 74.67 to 47.50 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

47% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
5% of SSE/AVX addition or subtraction instructions are used in vector version.
25% of SSE/AVX multiply instructions are used in vector version.
11% of SSE/AVX fused multiply-add instructions are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 19 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_intel_fast_memset: 10 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
VRNDSCALESD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
VROUNDSD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Vector unaligned load/store instructions

Detected 18 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 18 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:278
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:278
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:279
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:279
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:280
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:280
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:281
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:281
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:282
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:282
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:283
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:283
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:284
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:284
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:285
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:285
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:286
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:286

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

81 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 9 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 145 FP arithmetical operations:

54: addition or subtraction (19 inside FMA instructions)
91: multiply (19 inside FMA instructions)

The binary loop is loading 1064 bytes (133 double precision FP elements). The binary loop is storing 824 bytes (103 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	432
nb uops	448
loop length	2258
used x86 registers	15
used mmx registers	0
used xmm registers	22
used ymm registers	12
used zmm registers	0
nb stack references	60
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	74.67 cycles
front end	74.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	50.00	50.17	30.33	30.33	38.00	49.83	25.00	38.00	38.00	38.00	25.00	30.33
cycles	50.00	50.17	30.33	30.33	38.00	49.83	25.00	38.00	38.00	38.00	25.00	30.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	74.67
Dispatch	50.17
Overall L1	74.67

Vectorization ratios

INT

all	4%
load	25%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	29%
load	50%
store	48%
mul	25%
add-sub	6%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	25%
load	47%
store	28%
mul	25%
add-sub	5%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	13%
load	21%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	19%
load	23%
store	24%
mul	20%
add-sub	13%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	18%
load	23%
store	19%
mul	20%
add-sub	13%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 74.67 cycles. At this rate:

7% of peak load performance is reached (14.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 74.67 to 50.17 cycles (1.49x speedup).

ASM code

In the binary file, the address of the loop is: 44061c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %RCX,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPNLEUQ 0xbdeb7(%RIP),%YMM9,%K1																vect (50.0%)
VMOVUPD (%RBX,%RAX,8),%YMM9{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM8,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RBX,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%RBX,%RCX,8),%YMM8{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM7,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM7,(%RBX,%RCX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%RBX,%RDX,8),%YMM7{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM6,%YMM7,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM6,(%RBX,%RDX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R13,%RAX,8),%YMM6{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM6,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM5,(%R13,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x88(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R13,%RSI,8),%YMM5{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM5,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM4,(%R13,%RSI,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x80(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R13,%RSI,8),%YMM4{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM4,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM3,(%R13,%RSI,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R13,%RCX,8),%YMM3{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM3,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM2,(%R13,%RCX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R13,%RDX,8),%YMM2{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM2,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM1,(%R13,%RDX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R13,%RCX,8),%YMM1{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%R13,%RCX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x158(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0xc8(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 441312 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1052>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x148(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RDX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x140(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x138(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x130(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD -0x210(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x28(%RSI),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVUPD -0x200(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x50(%RSI),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVUPD -0x1f0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x78(%RSI),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x48(%RSI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70(%RSI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM3,-0x240(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM0,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x38(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM15	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM15,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD %XMM4,-0x230(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM16	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
MOVSXD 0x60(%RSI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x98(%RSI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,-0x220(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x88(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM0,%XMM0,%XMM17	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMULSD %XMM28,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM29,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM3,%XMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD -0x1e0(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBLENDPD $0x1,%XMM4,%XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM4,%XMM6,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD 0xbf851(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDPD %XMM4,%XMM9,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM5,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVUPD 0xbf851(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VFMADD213PD %XMM10,%XMM7,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM6,-0x2c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM30,%XMM3,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM29,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,-0x2b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM5,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x2a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM31,%XMM6,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0xbf7b4(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM7,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0xbc900(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM2,%XMM11,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM5,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM16,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM4,%XMM4,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0xbdb15(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM3,%XMM12,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM3,%XMM31,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD -0x1d0(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDSD %XMM4,%XMM13,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM4,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM5,%XMM4,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM4,-0x280(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,-0x270(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x268(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM28,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM29,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM3,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM3,%XMM5,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPD %XMM3,%XMM9,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM4,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %XMM10,%XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM5,-0x2a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM30,%XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM29,%XMM5,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x290(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x288(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM31,%XMM5,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM7,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM2,%XMM11,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM4,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM3,%XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM1,%XMM12,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM1,%XMM31,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM13,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM3,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM4,%XMM3,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM3,-0x260(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,-0x250(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM17,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,-0x248(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM29,%XMM8,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD 0xbf619(%RIP),%XMM12,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMULSD %XMM8,%XMM8,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD 0xbf613(%RIP),%XMM14,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0xe8(%RSI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 440ad0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x810>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM8,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM12,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM13,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM14,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM15,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM16,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM17,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RBX,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R13,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD %R13,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R13,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R13,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x50(%RBP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x58(%RBP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x68(%RBP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x70(%RBP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD -0xf0(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD -0x100(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD -0xc0(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0xbc594(%RIP),%XMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbc582(%RIP),%XMM30	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbc560(%RIP),%XMM29	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbf456(%RIP),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 440afd <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x83d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA (%RCX,%RCX,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%RCX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%RCX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VCVTTSD2SI %XMM15,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM16,%ECX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM17,%EDX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
MOV -0xb0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EDX,%ESI,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RDX,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DEC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %ECX,%ESI,%ECX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RCX,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x40(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EAX,%ECX,%EAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RAX,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV -0xd0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R11,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R15,%R15,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%R15,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R10,%R15,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RCX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R9,%R11,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x3(%R8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x2(%R8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM28,%XMM8,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM29,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM8,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM8,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM30,%XMM8,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM29,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM8,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM8,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM31,%XMM2,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM8,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD 0xbf305(%RIP),%XMM8,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0xbc455(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM8,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM8,%XMM31,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD 0xbd68f(%RIP),%XMM8,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM0,%XMM14,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM13,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM7,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM12,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM8,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM9,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM10,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM11,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R10,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R8,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x30(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R11,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RBX,%RAX,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%R8,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 440d4b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xa8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV -0x48(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x128(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x120(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 440604 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x344>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD -0x230(%RBP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD -0x220(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULSD %XMM7,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVUPD -0x240(%RBP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULSD %XMM6,%XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM9,%XMM9,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM7,%XMM7,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM6,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM7,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM9,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM2,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 440510 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x5,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RSI,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RSI,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x150(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R13,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 440512 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x252>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 440604 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x344>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:187-286
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:265
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:206-207
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,198-202,226-262,269-286

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=32
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

47% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
5% of SSE/AVX addition or subtraction instructions are used in vector version.
25% of SSE/AVX multiply instructions are used in vector version.
11% of SSE/AVX fused multiply-add instructions are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 19 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

_intel_fast_memset: 10 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
VRNDSCALESD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
VROUNDSD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Vector unaligned load/store instructions

Detected 18 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 18 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:278
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:278
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:279
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:279
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:280
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:280
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:281
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:281
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:282
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:282
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:283
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:283
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:284
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:284
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:285
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:285
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:286
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:286

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 145 FP arithmetical operations:

54: addition or subtraction (19 inside FMA instructions)
91: multiply (19 inside FMA instructions)

The binary loop is loading 1064 bytes (133 double precision FP elements). The binary loop is storing 824 bytes (103 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	432
nb uops	448
loop length	2258
used x86 registers	15
used mmx registers	0
used xmm registers	22
used ymm registers	12
used zmm registers	0
nb stack references	60
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	74.67 cycles
front end	74.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	50.00	50.17	30.33	30.33	38.00	49.83	25.00	38.00	38.00	38.00	25.00	30.33
cycles	50.00	50.17	30.33	30.33	38.00	49.83	25.00	38.00	38.00	38.00	25.00	30.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	74.67
Dispatch	50.17
Overall L1	74.67

Vectorization ratios

INT

all	4%
load	25%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	29%
load	50%
store	48%
mul	25%
add-sub	6%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	25%
load	47%
store	28%
mul	25%
add-sub	5%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	13%
load	21%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	19%
load	23%
store	24%
mul	20%
add-sub	13%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	18%
load	23%
store	19%
mul	20%
add-sub	13%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 74.67 cycles. At this rate:

7% of peak load performance is reached (14.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 44061c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %RCX,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPNLEUQ 0xbdeb7(%RIP),%YMM9,%K1																vect (50.0%)
VMOVUPD (%RBX,%RAX,8),%YMM9{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM8,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RBX,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%RBX,%RCX,8),%YMM8{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM7,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM7,(%RBX,%RCX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%RBX,%RDX,8),%YMM7{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM6,%YMM7,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM6,(%RBX,%RDX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R13,%RAX,8),%YMM6{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM6,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM5,(%R13,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x88(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R13,%RSI,8),%YMM5{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM5,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM4,(%R13,%RSI,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x80(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R13,%RSI,8),%YMM4{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM4,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM3,(%R13,%RSI,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R13,%RCX,8),%YMM3{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM3,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM2,(%R13,%RCX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R13,%RDX,8),%YMM2{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM2,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM1,(%R13,%RDX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R13,%RCX,8),%YMM1{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%R13,%RCX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV -0x158(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0xc8(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 441312 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1052>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x148(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RDX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x140(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x138(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x130(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD -0x210(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x28(%RSI),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVUPD -0x200(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x50(%RSI),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVUPD -0x1f0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x78(%RSI),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x48(%RSI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70(%RSI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM3,-0x240(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM0,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x38(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM15	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM15,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD %XMM4,-0x230(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM16	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
MOVSXD 0x60(%RSI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x98(%RSI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,-0x220(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x88(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM0,%XMM0,%XMM17	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMULSD %XMM28,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM29,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM3,%XMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD -0x1e0(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBLENDPD $0x1,%XMM4,%XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM4,%XMM6,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD 0xbf851(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDPD %XMM4,%XMM9,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM5,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVUPD 0xbf851(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VFMADD213PD %XMM10,%XMM7,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM6,-0x2c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM30,%XMM3,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM29,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,-0x2b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM5,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x2a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM31,%XMM6,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0xbf7b4(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM7,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0xbc900(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM2,%XMM11,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM5,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM16,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM4,%XMM4,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0xbdb15(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM3,%XMM12,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM3,%XMM31,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD -0x1d0(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDSD %XMM4,%XMM13,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM4,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM5,%XMM4,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM4,-0x280(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,-0x270(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x268(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM28,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM29,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM3,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM3,%XMM5,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPD %XMM3,%XMM9,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM4,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %XMM10,%XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM5,-0x2a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM30,%XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM29,%XMM5,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x290(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x288(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM31,%XMM5,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM7,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM2,%XMM11,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM4,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM3,%XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM1,%XMM12,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM1,%XMM31,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM13,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM3,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM4,%XMM3,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM3,-0x260(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM2,%XMM31,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,-0x250(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM17,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,-0x248(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM29,%XMM8,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD 0xbf619(%RIP),%XMM12,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMULSD %XMM8,%XMM8,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD 0xbf613(%RIP),%XMM14,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0xe8(%RSI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 440ad0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x810>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM8,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM12,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM13,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM14,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM15,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM16,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM17,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RBX,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R13,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD %R13,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R13,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R13,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4efda0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x50(%RBP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x58(%RBP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x68(%RBP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x70(%RBP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD -0xf0(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD -0x100(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD -0xc0(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0xbc594(%RIP),%XMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbc582(%RIP),%XMM30	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbc560(%RIP),%XMM29	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbf456(%RIP),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 440afd <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x83d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA (%RCX,%RCX,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%RCX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%RCX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VCVTTSD2SI %XMM15,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM16,%ECX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM17,%EDX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
MOV -0xb0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EDX,%ESI,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RDX,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DEC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %ECX,%ESI,%ECX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RCX,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x40(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EAX,%ECX,%EAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RAX,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV -0xd0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R11,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R15,%R15,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%R15,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R10,%R15,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RCX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R9,%R11,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x3(%R8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x2(%R8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM28,%XMM8,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM29,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM8,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM8,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM30,%XMM8,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM29,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM8,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM28,%XMM8,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM31,%XMM2,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM30,%XMM8,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD 0xbf305(%RIP),%XMM8,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0xbc455(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM29,%XMM8,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM8,%XMM31,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD 0xbd68f(%RIP),%XMM8,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM31,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM0,%XMM14,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM13,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM7,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM12,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM8,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM9,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM10,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM11,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R10,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R8,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x30(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R11,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RBX,%RAX,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%R8,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 440d4b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xa8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV -0x48(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x128(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x120(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 440604 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x344>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD -0x230(%RBP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD -0x220(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULSD %XMM7,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVUPD -0x240(%RBP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULSD %XMM6,%XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM9,%XMM9,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM7,%XMM7,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM6,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM7,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM9,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM2,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 440510 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x5,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RSI,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RSI,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x150(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R13,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 440512 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x252>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 440604 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x344>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code