OV - exec - Loop 88

	Loop Id: 88	Module: exec	Source: NonLocalPP.hpp:126-135 [...]	Coverage: 0.09%

0x40ec00 INC	%R14

0x40ec03 CMP	%R14,0x260(%RAX)

0x40ec0a JBE	40eba0

0x40ec0c MOV	(%R15),%RCX

0x40ec0f VMOVSD	(%R13),%XMM0

0x40ec15 VUCOMISD	(%RCX,%R14,8),%XMM0

0x40ec1b JBE	40ec00

0x40ec1d MOV	0x13f0(%R13),%RCX

0x40ec24 SUB	0x13e8(%R13),%RCX

0x40ec2b SHR	$0x3,%RCX

0x40ec2f IMUL	$-0x55555555,%ECX,%ECX

0x40ec35 TEST	%ECX,%ECX

0x40ec37 JLE	40ecf9

0x40ec3d VPBROADCASTQ	%R14,%XMM0

0x40ec43 MOV	$0x10,%EAX

0x40ec48 XOR	%ECX,%ECX

0x40ec4a MOV	-0x30(%RBP),%R8

0x40ec4e XCHG	%AX,%AX

  (89) 0x40ec50 MOV	(%R15),%RDX

  (89) 0x40ec53 VMOVDDUP	(%RDX,%R14,8),%XMM1

  (89) 0x40ec59 MOV	(%RBX),%RDX

  (89) 0x40ec5c MOVSXD	-0x10(%RBX),%R9

  (89) 0x40ec60 VMOVSD	(%R8,%RAX,1),%XMM2

  (89) 0x40ec66 LEA	(%R14,%R9,2),%RDI

  (89) 0x40ec6a VFMADD213SD	(%RDX,%RDI,8),%XMM1,%XMM2

  (89) 0x40ec70 VMOVQ	%R9,%XMM3

  (89) 0x40ec75 VPSLLDQ	$0x8,%XMM3,%XMM3

  (89) 0x40ec7a VPADDQ	%XMM3,%XMM0,%XMM3

  (89) 0x40ec7e VPSLLQ	$0x3,%XMM3,%XMM3

  (89) 0x40ec83 VPBROADCASTQ	%RDX,%XMM4

  (89) 0x40ec89 VPADDQ	%XMM3,%XMM4,%XMM3

  (89) 0x40ec8d VMOVQ	%XMM3,%RDX

  (89) 0x40ec92 VMOVSD	(%RDX),%XMM4

  (89) 0x40ec96 VPEXTRQ	$0x1,%XMM3,%RDX

  (89) 0x40ec9c VMOVHPD	(%RDX),%XMM4,%XMM3

  (89) 0x40eca0 MOV	0x40(%RSI),%RDX

  (89) 0x40eca4 VADDSD	0x10(%RDX,%R12,8),%XMM2,%XMM2

  (89) 0x40ecab VFMADD231PD	-0x10(%R8,%RAX,1),%XMM1,%XMM3

  (89) 0x40ecb2 VADDPD	(%RDX,%R12,8),%XMM3,%XMM1

  (89) 0x40ecb8 MOV	-0x60(%RBP),%RDX

  (89) 0x40ecbc VMOVUPD	%XMM1,-0x10(%RDX,%RAX,1)

  (89) 0x40ecc2 VMOVSD	%XMM2,(%RDX,%RAX,1)

  (89) 0x40ecc7 MOV	0x13f0(%R13),%RDX

  (89) 0x40ecce SUB	0x13e8(%R13),%RDX

  (89) 0x40ecd5 INC	%RCX

  (89) 0x40ecd8 SHR	$0x3,%RDX

  (89) 0x40ecdc IMUL	$-0x55555555,%EDX,%EDX

  (89) 0x40ece2 MOVSXD	%EDX,%RDX

  (89) 0x40ece5 ADD	$0x18,%RAX

  (89) 0x40ece9 CMP	%RDX,%RCX

  (89) 0x40ecec JL	40ec50

0x40ecf2 MOV	0x1418(%R13),%RAX

0x40ecf9 MOV	0x18(%RAX),%RAX

0x40ecfd MOVSXD	(%RAX,%R14,4),%RAX

0x40ed01 MOV	0x1400(%R13),%RCX

0x40ed08 MOV	(%RCX,%RAX,8),%R13

0x40ed0c MOV	%R13,%RDI

0x40ed0f MOV	-0x38(%RBP),%RDX

0x40ed13 LEA	-0x60(%RBP),%RCX

0x40ed17 MOV	$0x1,%R8D

0x40ed1d MOV	%R14D,%R9D

0x40ed20 CALL	464e40 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>

0x40ed25 MOV	-0xa8(%RBP),%RDI

0x40ed2c MOV	%R13,%RSI

0x40ed2f LEA	-0x80(%RBP),%RDX

0x40ed33 CALL	412f30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>

0x40ed38 MOV	-0x40(%RBP),%R13

0x40ed3c MOV	0x1418(%R13),%RAX

0x40ed43 MOV	-0xa0(%RBP),%RSI

0x40ed4a JMP	40ec00

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 126 - 135

--------------------------------------------------------------------------------

126:       for (int iat = 0; iat < ions_ref.getTotalNum(); ++iat)

127:       {

128:         //due to < Rmax condition, the actually iteration iat is [0,2] in a real simulation

129:         if (dist[iat] < Rmax)

130:         {

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

133:           auto& VP = *VPs[ions_ref.GroupID[iat]];

134:           VP.makeMoves(els, jel, virtualPos, true, iat);

135:           wf.evaluateRatios(VP, ratios);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h: 173 - 173

--------------------------------------------------------------------------------

173:       pointer    _M_ptr() const { return std::get<0>(_M_t); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

Coverage (%)	Name	Source Location	Module
►100.00+	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks
Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source	stl_vector.h:919-919,stl_vector.h:1046-1046,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,TinyVector.h:145-145,unique_ptr.h:173-173,OhmmsVector.h:229-229
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.61
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	4.61
CQA cycles if fully vectorized	0.38
Front-end cycles	4.56
P0 cycles	2.17
P1 cycles	1.53
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.67
P5 cycles	1.47
P6 cycles	2.17
P7 cycles	0.67
P8 cycles	0.67
P9 cycles	0.67
P10 cycles	1.33
P11 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	27.33
Nb loads	12.00
Nb stores	0.00
Nb stack references	4.33
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.53
Bytes prefetched	0.00
Bytes loaded	93.33
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.74
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.21

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P0, P6,
Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source	stl_vector.h:919-919,stl_vector.h:1046-1046,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,TinyVector.h:145-145,unique_ptr.h:173-173,OhmmsVector.h:229-229
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.19
Front-end cycles	1.33
P0 cycles	1.50
P1 cycles	0.40
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	0.00
P5 cycles	0.40
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.20
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	8.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source	stl_vector.h:919-919,stl_vector.h:1046-1046,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,TinyVector.h:145-145,unique_ptr.h:173-173,OhmmsVector.h:229-229
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	0.51
Front-end cycles	6.67
P0 cycles	2.50
P1 cycles	2.40
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	1.00
P5 cycles	2.40
P6 cycles	2.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	2.20
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	40.00
Nb loads	17.00
Nb stores	0.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.80
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	0.00
Stride 0	3.00
Stride 1	2.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.71

Metric	Value
CQA speedup if no scalar integer	2.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.95
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source	stl_vector.h:919-919,stl_vector.h:1046-1046,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,TinyVector.h:145-145,unique_ptr.h:173-173,OhmmsVector.h:229-229
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	0.44
Front-end cycles	5.67
P0 cycles	2.50
P1 cycles	1.80
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	1.00
P5 cycles	1.60
P6 cycles	2.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.60
P11 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	34.00
Nb loads	15.00
Nb stores	0.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.47
Bytes prefetched	0.00
Bytes loaded	116.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.61 to 0.38 cycles (12.22x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 0 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 93 bytes (11 double precision FP elements).

General properties

nb instructions	25
nb uops	27.33
loop length	116.33
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	4.56 cycles
front end	4.56 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.17	1.53	4.00	4.00	0.67	1.47	2.17	0.67	0.67	0.67	1.33	4.00
cycles	2.17	1.53	4.00	4.00	0.67	1.47	2.17	0.67	0.67	0.67	1.33	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.56
Dispatch	4.06
Data deps.	1.00
Overall L1	4.61

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.61 cycles. At this rate:

10% of peak load performance is reached (20.53 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.19 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:129

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes (4 double precision FP elements).

General properties

nb instructions	7
nb uops	8
loop length	29
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.33 cycles
front end	1.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	0.40	1.33	1.33	0.00	0.40	1.50	0.00	0.00	0.00	0.20	1.33
cycles	1.50	0.40	1.33	1.33	0.00	0.40	1.50	0.00	0.00	0.00	0.20	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.33
Dispatch	1.50
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

11% of peak load performance is reached (21.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ec0c

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
INC %R14	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,0x260(%RAX)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JBE 40eba0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x770>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV (%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD (%RCX,%R14,8),%XMM0	2	1	0	0.33	0.33	0	0	0	0.33	3	1	scal (12.5%)
JBE 40ec00 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x7d0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.67 to 2.00 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:134
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:135

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:129

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 132 bytes (16 double precision FP elements).

General properties

nb instructions	37
nb uops	40
loop length	173
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.40	5.67	5.67	1.00	2.40	2.50	1.00	1.00	1.00	2.20	5.67
cycles	2.50	2.40	5.67	5.67	1.00	2.40	2.50	1.00	1.00	1.00	2.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.67
Dispatch	5.67
Data deps.	1.00
Overall L1	6.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

10% of peak load performance is reached (19.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 5.67 cycles (1.18x speedup).

ASM code

In the binary file, the address of the loop is: 40ec0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,0x260(%RAX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JBE 40eba0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x770>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD (%RCX,%R14,8),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 40ec00 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x7d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x13f0(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x13e8(%R13),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
IMUL $-0x55555555,%ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 40ecf9 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x8c9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %R14,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV $0x10,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1418(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX,%R14,4),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1400(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 464e40 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xa8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x80(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 412f30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1418(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 40ec00 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x7d0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.67 to 2.00 cycles (2.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:134
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:135

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:129

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 116 bytes (14 double precision FP elements).

General properties

nb instructions	31
nb uops	34
loop length	147
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.80	5.00	5.00	1.00	1.60	2.50	1.00	1.00	1.00	1.60	5.00
cycles	2.50	1.80	5.00	5.00	1.00	1.60	2.50	1.00	1.00	1.00	1.60	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	5.00
Data deps.	1.00
Overall L1	5.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

10% of peak load performance is reached (20.47 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40ec0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,0x260(%RAX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JBE 40eba0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x770>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD (%RCX,%R14,8),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 40ec00 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x7d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x13f0(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x13e8(%R13),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
IMUL $-0x55555555,%ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 40ecf9 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x8c9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX,%R14,4),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1400(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 464e40 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xa8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x80(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 412f30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1418(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 40ec00 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x7d0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code