OV - exec - Loop 408

	Loop Id: 408	Module: exec	Source: BsplineFunctor.h:236-241 [...]	Coverage: 1.98%

0x423ce0 VMOVUPD	(%R13,%RSI,8),%YMM4    [3]

0x423ce7 VMOVUPD	0x20(%R13,%RSI,8),%YMM5    [3]

0x423cee VMOVUPD	0x40(%R13,%RSI,8),%YMM6    [3]

0x423cf5 VMOVUPD	0x60(%R13,%RSI,8),%YMM7    [3]

0x423cfc LEA	(%R12,%RSI,1),%EDI

0x423d00 VPBROADCASTD	%EDI,%YMM8

0x423d06 VPADDD	%YMM24,%YMM8,%YMM9

0x423d0c VPADDD	%YMM31,%YMM8,%YMM8

0x423d12 VPCMPNEQD	%YMM1,%YMM8,%K0

0x423d19 VPCMPNEQD	%YMM1,%YMM9,%K2

0x423d20 VCMPPD	$0x1,%YMM3,%YMM4,%K5

0x423d27 VCMPPD	$0x1,%YMM3,%YMM5,%K1

0x423d2e KMOVW	%K1,-0x2a(%RBP)    [2]

0x423d33 KSHIFTLB	$0x4,%K1,%K3

0x423d39 KORB	%K3,%K5,%K3

0x423d3d VCMPPD	$0x1,%YMM3,%YMM6,%K6

0x423d44 VCMPPD	$0x1,%YMM3,%YMM7,%K4

0x423d4b MOVSXD	%R10D,%R10

0x423d4e LEA	(%RDX,%R10,8),%RDI

0x423d52 KANDB	%K0,%K3,%K7

0x423d56 KMOVB	%K7,%EBX

0x423d5a KANDW	%K2,%K6,%K7

0x423d5e POPCNT	%EBX,%EBX

0x423d62 VCOMPRESSPD	%YMM6,(%RDI,%RBX,8){%K7}    [4]

0x423d69 KANDW	%K0,%K5,%K5

0x423d6d VCOMPRESSPD	%YMM4,(%RDX,%R10,8){%K5}    [5]

0x423d74 KSHIFTLB	$0x4,%K4,%K1

0x423d7a KORB	%K1,%K6,%K1

0x423d7e KMOVB	%K7,-0x2d(%RBP)    [2]

0x423d83 KSHIFTRB	$0x4,%K2,%K6

0x423d89 KANDW	%K6,%K4,%K4

0x423d8d LEA	(%RDI,%RBX,8),%RBX

0x423d91 MOVZX	-0x2d(%RBP),%ECX    [2]

0x423d95 POPCNT	%ECX,%ECX

0x423d99 VCOMPRESSPD	%YMM7,(%RBX,%RCX,8){%K4}    [1]

0x423da0 KUNPCKBW	%K3,%K1,%K1

0x423da4 KMOVB	%K5,-0x2e(%RBP)    [2]

0x423da9 KUNPCKBW	%K0,%K2,%K2

0x423dad KSHIFTRB	$0x4,%K0,%K0

0x423db3 KMOVW	-0x2a(%RBP),%K3    [2]

0x423db8 KANDW	%K0,%K3,%K3

0x423dbc MOVZX	-0x2e(%RBP),%ECX    [2]

0x423dc0 POPCNT	%ECX,%ECX

0x423dc4 VCOMPRESSPD	%YMM5,(%RDI,%RCX,8){%K3}    [4]

0x423dcb KANDW	%K2,%K1,%K0

0x423dcf KMOVW	%K0,%ECX

0x423dd3 POPCNT	%ECX,%ECX

0x423dd7 ADD	%ECX,%R10D

0x423dda ADD	$0x10,%RSI

0x423dde CMP	%R11,%RSI

0x423de1 JB	423ce0

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 236 - 241

--------------------------------------------------------------------------------

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 107 - 107

--------------------------------------------------------------------------------

107:     for (int k = 0; k < ratios.size(); ++k)

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.54
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P5,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:236-241,TwoBodyJastrowRef.h:107-107
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	20.00
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	20.00
CQA cycles if fully vectorized	6.50
Front-end cycles	9.67
P0 cycles	10.00
P1 cycles	6.00
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	3.50
P5 cycles	20.00
P6 cycles	2.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.00
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	58.00
Nb loads	7.00
Nb stores	7.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.20
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	132.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	3.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	85.71
Vector-efficiency ratio all	47.43
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	43.75

Metric	Value
CQA speedup if no scalar integer	1.54
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P5,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:236-241,TwoBodyJastrowRef.h:107-107
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	20.00
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	20.00
CQA cycles if fully vectorized	6.50
Front-end cycles	9.67
P0 cycles	10.00
P1 cycles	6.00
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	3.50
P5 cycles	20.00
P6 cycles	2.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.00
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	58.00
Nb loads	7.00
Nb stores	7.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.20
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	132.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	3.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	85.71
Vector-efficiency ratio all	47.43
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	43.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:236-241
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:236-241
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 13.00 cycles (1.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
VCOMPRESSPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 132 bytes (16 double precision FP elements). The binary loop is storing 132 bytes (16 double precision FP elements).

General properties

nb instructions	51
nb uops	58
loop length	263
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	10
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	6.00	2.33	2.33	3.50	20.00	2.00	3.50	3.50	3.50	2.00	2.33
cycles	10.00	6.00	2.33	2.33	3.50	20.00	2.00	3.50	3.50	3.50	2.00	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.67
Dispatch	20.00
Data deps.	2.00
Overall L1	20.00

Vectorization ratios

INT

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Vector efficiency ratios

INT

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	47%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

3% of peak load performance is reached (6.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 423ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R13,%RSI,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R13,%RSI,8),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R13,%RSI,8),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R13,%RSI,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
LEA (%R12,%RSI,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EDI,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPADDD %YMM24,%YMM8,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM31,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPCMPNEQD %YMM1,%YMM8,%K0																vect (50.0%)
VPCMPNEQD %YMM1,%YMM9,%K2																vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM4,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVW %K1,-0x2a(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KSHIFTLB $0x4,%K1,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K3,%K5,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VCMPPD $0x1,%YMM3,%YMM6,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM7,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
MOVSXD %R10D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%RDX,%R10,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KANDB %K0,%K3,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVB %K7,%EBX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KANDW %K2,%K6,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
POPCNT %EBX,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM6,(%RDI,%RBX,8){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KANDW %K0,%K5,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VCOMPRESSPD %YMM4,(%RDX,%R10,8){%K5}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KSHIFTLB $0x4,%K4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K6,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVB %K7,-0x2d(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KSHIFTRB $0x4,%K2,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KANDW %K6,%K4,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
LEA (%RDI,%RBX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVZX -0x2d(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM7,(%RBX,%RCX,8){%K4}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KUNPCKBW %K3,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVB %K5,-0x2e(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KUNPCKBW %K0,%K2,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTRB $0x4,%K0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW -0x2a(%RBP),%K3	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
KANDW %K0,%K3,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOVZX -0x2e(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM5,(%RDI,%RCX,8){%K3}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KANDW %K2,%K1,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
POPCNT %ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 423ce0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x300>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:236-241
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:236-241
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
VCOMPRESSPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	51
nb uops	58
loop length	263
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	10
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	6.00	2.33	2.33	3.50	20.00	2.00	3.50	3.50	3.50	2.00	2.33
cycles	10.00	6.00	2.33	2.33	3.50	20.00	2.00	3.50	3.50	3.50	2.00	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.67
Dispatch	20.00
Data deps.	2.00
Overall L1	20.00

Vectorization ratios

INT

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Vector efficiency ratios

INT

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	47%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

3% of peak load performance is reached (6.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 423ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R13,%RSI,8),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R13,%RSI,8),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R13,%RSI,8),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R13,%RSI,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
LEA (%R12,%RSI,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EDI,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPADDD %YMM24,%YMM8,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM31,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPCMPNEQD %YMM1,%YMM8,%K0																vect (50.0%)
VPCMPNEQD %YMM1,%YMM9,%K2																vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM4,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVW %K1,-0x2a(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KSHIFTLB $0x4,%K1,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K3,%K5,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VCMPPD $0x1,%YMM3,%YMM6,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM7,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
MOVSXD %R10D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%RDX,%R10,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KANDB %K0,%K3,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVB %K7,%EBX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KANDW %K2,%K6,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
POPCNT %EBX,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM6,(%RDI,%RBX,8){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KANDW %K0,%K5,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VCOMPRESSPD %YMM4,(%RDX,%R10,8){%K5}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KSHIFTLB $0x4,%K4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K6,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVB %K7,-0x2d(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KSHIFTRB $0x4,%K2,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KANDW %K6,%K4,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
LEA (%RDI,%RBX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVZX -0x2d(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM7,(%RBX,%RCX,8){%K4}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KUNPCKBW %K3,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVB %K5,-0x2e(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KUNPCKBW %K0,%K2,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTRB $0x4,%K0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW -0x2a(%RBP),%K3	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
KANDW %K0,%K3,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOVZX -0x2e(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM5,(%RDI,%RCX,8){%K3}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KANDW %K2,%K1,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
POPCNT %ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 423ce0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x300>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code