OV - exec - Loop 406

	Loop Id: 406	Module: exec	Source: BsplineFunctor.h:246-260	Coverage: 0.08%

0x4240f0 VMULPD	(%RDX,%RSI,8),%YMM19,%YMM21    [2]

0x4240f7 VCVTTPD2DQ	%YMM21,%XMM22

0x4240fd VRNDSCALEPD	$0xb,%YMM21,%YMM23

0x424104 VSUBPD	%YMM23,%YMM21,%YMM21

0x42410a VMULPD	%YMM21,%YMM21,%YMM23

0x424110 VMULPD	%YMM21,%YMM23,%YMM24

0x424116 VMOVAPD	%YMM23,%YMM25

0x42411c VFMADD213PD	%YMM2,%YMM17,%YMM25

0x424122 VFMADD231PD	%YMM3,%YMM24,%YMM25

0x424128 VFMADD231PD	%YMM21,%YMM5,%YMM25

0x42412e VXORPD	%XMM26,%XMM26,%XMM26

0x424134 KXNORW	%K0,%K0,%K1

0x424138 VGATHERDPD	(%R11,%XMM22,8),%YMM26{%K1}    [1]

0x42413f VFMADD213PD	%YMM20,%YMM25,%YMM26

0x424145 VMOVAPD	%YMM24,%YMM20

0x42414b VFMADD213PD	%YMM16,%YMM10,%YMM20

0x424151 VFMADD231PD	%YMM23,%YMM14,%YMM20

0x424157 VXORPD	%XMM25,%XMM25,%XMM25

0x42415d KXNORW	%K0,%K0,%K1

0x424161 VGATHERDPD	0x8(%R11,%XMM22,8),%YMM25{%K1}    [1]

0x424169 VFMADD231PD	%YMM21,%YMM15,%YMM20

0x42416f VFMADD213PD	%YMM26,%YMM20,%YMM25

0x424175 VMOVAPD	%YMM24,%YMM20

0x42417b VFMADD213PD	%YMM9,%YMM13,%YMM20

0x424181 VXORPD	%XMM26,%XMM26,%XMM26

0x424187 KXNORW	%K0,%K0,%K1

0x42418b VGATHERDPD	0x10(%R11,%XMM22,8),%YMM26{%K1}    [1]

0x424193 VFMADD231PD	%YMM23,%YMM12,%YMM20

0x424199 VFMADD231PD	%YMM21,%YMM11,%YMM20

0x42419f VFMADD213PD	%YMM25,%YMM20,%YMM26

0x4241a5 VXORPD	%XMM20,%XMM20,%XMM20

0x4241ab KXNORW	%K0,%K0,%K1

0x4241af VGATHERDPD	0x18(%R11,%XMM22,8),%YMM20{%K1}    [1]

0x4241b7 VFMADD213PD	%YMM4,%YMM8,%YMM24

0x4241bd VFMADD231PD	%YMM23,%YMM7,%YMM24

0x4241c3 VFMADD231PD	%YMM21,%YMM6,%YMM24

0x4241c9 VFMADD213PD	%YMM26,%YMM24,%YMM20

0x4241cf ADD	$0x4,%RSI

0x4241d3 CMP	%R9,%RSI

0x4241d6 JB	4240f0

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.68
CQA speedup if fully vectorized	2.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	7.00
Front-end cycles	9.67
P0 cycles	15.00
P1 cycles	15.00
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	0.00
P5 cycles	10.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	57.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.00
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	46.97
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	42.31

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.68
CQA speedup if fully vectorized	2.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	7.00
Front-end cycles	9.67
P0 cycles	15.00
P1 cycles	15.00
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	0.00
P5 cycles	10.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	57.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.00
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	46.97
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	42.31

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 46% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259
VRNDSCALEPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:251

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

21 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

68: addition or subtraction (64 inside FMA instructions)
76: multiply (64 inside FMA instructions)

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	57
loop length	236
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	23
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.00	15.00	5.67	5.67	0.00	10.00	1.00	0.00	0.00	0.00	0.00	5.67
cycles	15.00	15.00	5.67	5.67	0.00	10.00	1.00	0.00	0.00	0.00	0.00	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	9.67
Dispatch	15.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	46%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

5% of peak load performance is reached (10.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4240f0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMULPD (%RDX,%RSI,8),%YMM19,%YMM21	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VCVTTPD2DQ %YMM21,%XMM22	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM21,%YMM23	2	1	1	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM23,%YMM21,%YMM21	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM23	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM21,%YMM23,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM23,%YMM25	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD %YMM2,%YMM17,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM24,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM5,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD (%R11,%XMM22,8),%YMM26{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD213PD %YMM20,%YMM25,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM20	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD %YMM16,%YMM10,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM14,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD 0x8(%R11,%XMM22,8),%YMM25{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD231PD %YMM21,%YMM15,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM26,%YMM20,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM20	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD %YMM9,%YMM13,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD 0x10(%R11,%XMM22,8),%YMM26{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD231PD %YMM23,%YMM12,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM11,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM25,%YMM20,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD 0x18(%R11,%XMM22,8),%YMM20{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD213PD %YMM4,%YMM8,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM7,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM6,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM26,%YMM24,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x4,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 4240f0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x710>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 46% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259
VRNDSCALEPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:251

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

21 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

68: addition or subtraction (64 inside FMA instructions)
76: multiply (64 inside FMA instructions)

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	57
loop length	236
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	23
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.00	15.00	5.67	5.67	0.00	10.00	1.00	0.00	0.00	0.00	0.00	5.67
cycles	15.00	15.00	5.67	5.67	0.00	10.00	1.00	0.00	0.00	0.00	0.00	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	9.67
Dispatch	15.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	46%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

5% of peak load performance is reached (10.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4240f0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMULPD (%RDX,%RSI,8),%YMM19,%YMM21	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VCVTTPD2DQ %YMM21,%XMM22	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM21,%YMM23	2	1	1	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM23,%YMM21,%YMM21	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM23	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM21,%YMM23,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM23,%YMM25	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD %YMM2,%YMM17,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM24,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM5,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD (%R11,%XMM22,8),%YMM26{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD213PD %YMM20,%YMM25,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM20	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD %YMM16,%YMM10,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM14,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD 0x8(%R11,%XMM22,8),%YMM25{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD231PD %YMM21,%YMM15,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM26,%YMM20,%YMM25	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM20	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD %YMM9,%YMM13,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD 0x10(%R11,%XMM22,8),%YMM26{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD231PD %YMM23,%YMM12,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM11,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM25,%YMM20,%YMM26	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPD 0x18(%R11,%XMM22,8),%YMM20{%K1}	5	1	1	1.33	1.33	1	0	0	1.33	28	2	vect (50.0%)
VFMADD213PD %YMM4,%YMM8,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM7,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM6,%YMM24	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM26,%YMM24,%YMM20	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x4,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 4240f0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x710>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code