OV - exec - Loop 2204

	Loop Id: 2204	Module: exec	Source: SoaDistanceTableABOMPTarget.h:228-228 [...]	Coverage: 7.03%

0x4cd760 VMOVSD	(%R14,%RDX,1),%XMM23    [4]

0x4cd767 VSUBSD	%XMM20,%XMM23,%XMM23

0x4cd76d VMOVSD	(%R12,%RDX,1),%XMM24    [3]

0x4cd774 VSUBSD	%XMM21,%XMM24,%XMM24

0x4cd77a VMOVSD	(%R9,%RDX,1),%XMM25    [2]

0x4cd781 VSUBSD	%XMM22,%XMM25,%XMM25

0x4cd787 VMULSD	%XMM23,%XMM2,%XMM26

0x4cd78d VFMADD231SD	%XMM24,%XMM3,%XMM26

0x4cd793 VFMADD231SD	%XMM25,%XMM4,%XMM26

0x4cd799 VMULSD	%XMM23,%XMM5,%XMM27

0x4cd79f VFMADD231SD	%XMM24,%XMM6,%XMM27

0x4cd7a5 VFMADD231SD	%XMM25,%XMM7,%XMM27

0x4cd7ab VMULSD	%XMM23,%XMM8,%XMM23

0x4cd7b1 VFMADD231SD	%XMM24,%XMM9,%XMM23

0x4cd7b7 VFMADD231SD	%XMM25,%XMM10,%XMM23

0x4cd7bd VMOVDQA64	%XMM1,%XMM24

0x4cd7c3 VPTERNLOGQ	$-0x8,%XMM0,%XMM26,%XMM24

0x4cd7ca VADDSD	%XMM24,%XMM26,%XMM24

0x4cd7d0 VRNDSCALESD	$0xb,%XMM24,%XMM24,%XMM24

0x4cd7d7 VMOVDQA64	%XMM1,%XMM25

0x4cd7dd VPTERNLOGQ	$-0x8,%XMM0,%XMM27,%XMM25

0x4cd7e4 VADDSD	%XMM25,%XMM27,%XMM25

0x4cd7ea VRNDSCALESD	$0xb,%XMM25,%XMM25,%XMM25

0x4cd7f1 VSUBSD	%XMM24,%XMM26,%XMM24

0x4cd7f7 VSUBSD	%XMM25,%XMM27,%XMM25

0x4cd7fd VMOVDQA64	%XMM1,%XMM26

0x4cd803 VPTERNLOGQ	$-0x8,%XMM0,%XMM23,%XMM26

0x4cd80a VADDSD	%XMM26,%XMM23,%XMM26

0x4cd810 VRNDSCALESD	$0xb,%XMM26,%XMM26,%XMM26

0x4cd817 VSUBSD	%XMM26,%XMM23,%XMM23

0x4cd81d VMULSD	%XMM24,%XMM11,%XMM26

0x4cd823 VFMADD231SD	%XMM25,%XMM12,%XMM26

0x4cd829 VFMADD231SD	%XMM13,%XMM23,%XMM26

0x4cd82f VMOVSD	%XMM26,(%R15,%RDX,1)    [7]

0x4cd836 VMULSD	%XMM24,%XMM14,%XMM27

0x4cd83c VFMADD231SD	%XMM25,%XMM15,%XMM27

0x4cd842 VFMADD231SD	%XMM23,%XMM16,%XMM27

0x4cd848 VMOVSD	%XMM27,(%RBX,%RDX,1)    [5]

0x4cd84f VMULSD	%XMM24,%XMM17,%XMM24

0x4cd855 VFMADD231SD	%XMM25,%XMM18,%XMM24

0x4cd85b VFMADD231SD	%XMM23,%XMM19,%XMM24

0x4cd861 VMOVSD	%XMM24,(%R8,%RDX,1)    [1]

0x4cd868 VMULSD	%XMM26,%XMM26,%XMM23

0x4cd86e VFMADD231SD	%XMM27,%XMM27,%XMM23

0x4cd874 VFMADD231SD	%XMM24,%XMM24,%XMM23

0x4cd87a VSQRTSD	%XMM23,%XMM23,%XMM23

0x4cd880 VMOVSD	%XMM23,(%RDI,%RDX,1)    [6]

0x4cd887 ADD	$0x8,%RDX

0x4cd88b CMP	%RDX,%R13

0x4cd88e JNE	4cd760

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

--------------------------------------------------------------------------------

280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 228 - 228

--------------------------------------------------------------------------------

228:           for (int iel = first; iel < last; iel++)

Coverage (%)	Name	Source Location	Module
►99.68+	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:134	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.33
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P0, P1,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298,SoaDistanceTableABOMPTarget.h:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	2.25
Front-end cycles	8.67
P0 cycles	15.00
P1 cycles	15.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	2.00
P5 cycles	10.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	1.00
DIV/SQRT cycles	4.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	52.00
Nb loads	3.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.73
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	12.77
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	14.10
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.33
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P0, P1,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298,SoaDistanceTableABOMPTarget.h:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	2.25
Front-end cycles	8.67
P0 cycles	15.00
P1 cycles	15.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	2.00
P5 cycles	10.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	1.00
DIV/SQRT cycles	4.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	52.00
Nb loads	3.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.73
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	12.77
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	14.10
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	SoaDistanceTableABOMPTarget.h:228-228
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 15.00 to 2.25 cycles (6.67x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 10.50 cycles (1.43x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:289
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:290
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:291

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 45 FP arithmetical operations:

23: addition or subtraction (14 inside FMA instructions)
21: multiply (14 inside FMA instructions)
1: square root

The binary loop is loading 24 bytes (3 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.80 FP operations per loaded or stored byte.

General properties

nb instructions	50
nb uops	52
loop length	308
used x86 registers	9
used mmx registers	0
used xmm registers	28
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.00	14.50	1.00	1.00	2.00	10.50	1.00	2.00	2.00	2.00	0.00	1.00
cycles	15.00	15.00	1.00	1.00	2.00	10.50	1.00	2.00	2.00	2.00	0.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	4.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.67
Dispatch	15.00
DIV/SQRT	4.50
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	66%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

0% of peak load performance is reached (1.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4cd760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R14,%RDX,1),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD %XMM20,%XMM23,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R12,%RDX,1),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD %XMM21,%XMM24,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R9,%RDX,1),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD %XMM22,%XMM25,%XMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM23,%XMM2,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM3,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM4,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM5,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM6,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM7,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM8,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM9,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM10,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA64 %XMM1,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM0,%XMM26,%XMM24	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM24,%XMM26,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VRNDSCALESD $0xb,%XMM24,%XMM24,%XMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVDQA64 %XMM1,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM0,%XMM27,%XMM25	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM25,%XMM27,%XMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VRNDSCALESD $0xb,%XMM25,%XMM25,%XMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM24,%XMM26,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM25,%XMM27,%XMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDQA64 %XMM1,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM0,%XMM23,%XMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM26,%XMM23,%XMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VRNDSCALESD $0xb,%XMM26,%XMM26,%XMM26	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM26,%XMM23,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM24,%XMM11,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM12,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM23,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM26,(%R15,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM24,%XMM14,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM15,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM23,%XMM16,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM27,(%RBX,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM24,%XMM17,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM18,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM23,%XMM19,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM24,(%R8,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM26,%XMM26,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM27,%XMM27,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM24,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM23,%XMM23,%XMM23	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD %XMM23,(%RDI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4cd760 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x530>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	SoaDistanceTableABOMPTarget.h:228-228
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:289
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:290
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:291

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 45 FP arithmetical operations:

23: addition or subtraction (14 inside FMA instructions)
21: multiply (14 inside FMA instructions)
1: square root

The binary loop is loading 24 bytes (3 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.80 FP operations per loaded or stored byte.

General properties

nb instructions	50
nb uops	52
loop length	308
used x86 registers	9
used mmx registers	0
used xmm registers	28
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.00	14.50	1.00	1.00	2.00	10.50	1.00	2.00	2.00	2.00	0.00	1.00
cycles	15.00	15.00	1.00	1.00	2.00	10.50	1.00	2.00	2.00	2.00	0.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	4.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.67
Dispatch	15.00
DIV/SQRT	4.50
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	66%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

0% of peak load performance is reached (1.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4cd760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R14,%RDX,1),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD %XMM20,%XMM23,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R12,%RDX,1),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD %XMM21,%XMM24,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R9,%RDX,1),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD %XMM22,%XMM25,%XMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM23,%XMM2,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM3,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM4,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM5,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM6,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM7,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM8,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM9,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM10,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA64 %XMM1,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM0,%XMM26,%XMM24	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM24,%XMM26,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VRNDSCALESD $0xb,%XMM24,%XMM24,%XMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVDQA64 %XMM1,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM0,%XMM27,%XMM25	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM25,%XMM27,%XMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VRNDSCALESD $0xb,%XMM25,%XMM25,%XMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM24,%XMM26,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM25,%XMM27,%XMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDQA64 %XMM1,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM0,%XMM23,%XMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM26,%XMM23,%XMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VRNDSCALESD $0xb,%XMM26,%XMM26,%XMM26	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM26,%XMM23,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM24,%XMM11,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM12,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM23,%XMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM26,(%R15,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM24,%XMM14,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM15,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM23,%XMM16,%XMM27	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM27,(%RBX,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM24,%XMM17,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM18,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM23,%XMM19,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM24,(%R8,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM26,%XMM26,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM27,%XMM27,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM24,%XMM23	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM23,%XMM23,%XMM23	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD %XMM23,(%RDI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4cd760 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x530>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code