OV - exec - Loop 1944

	Loop Id: 1944	Module: exec	Source: SoaDistanceTableAAOMPTarget.h:440-442 [...]	Coverage: 15.52%

0x4afb80 MOV	-0x28(%RSI,%R14,8),%RBX    [3]

0x4afb85 VMOVSD	-0x8(%R8,%R10,8),%XMM1    [1]

0x4afb8c VMOVSD	%XMM1,(%RBX,%R13,8)    [9]

0x4afb92 VMOVSD	-0x8(%RDX,%R10,8),%XMM1    [10]

0x4afb99 VXORPS	%XMM0,%XMM1,%XMM1

0x4afb9d VMOVSD	-0x8(%R12,%R10,8),%XMM2    [4]

0x4afba4 VXORPS	%XMM0,%XMM2,%XMM2

0x4afba8 VMOVSD	-0x8(%R15,%R10,8),%XMM3    [7]

0x4afbaf VXORPS	%XMM0,%XMM3,%XMM3

0x4afbb3 MOV	-0x38(%RAX,%R14,8),%RBX    [8]

0x4afbb8 MOV	-0x28(%RAX,%R14,8),%RDI    [8]

0x4afbbd VMOVLPS	%XMM1,(%RDI,%R13,8)    [6]

0x4afbc3 LEA	(%RBX,%R13,1),%RCX

0x4afbc7 VMOVLPS	%XMM2,(%RDI,%RCX,8)    [6]

0x4afbcc LEA	(%R13,%RBX,2),%RCX

0x4afbd1 VMOVLPS	%XMM3,(%RDI,%RCX,8)    [6]

0x4afbd6 MOV	(%RSI,%R14,8),%RCX    [3]

0x4afbda VMOVSD	(%R8,%R10,8),%XMM1    [1]

0x4afbe0 VMOVSD	%XMM1,(%RCX,%R13,8)    [2]

0x4afbe6 VMOVSD	(%RDX,%R10,8),%XMM1    [10]

0x4afbec VXORPS	%XMM0,%XMM1,%XMM1

0x4afbf0 VMOVSD	(%R12,%R10,8),%XMM2    [4]

0x4afbf6 VXORPS	%XMM0,%XMM2,%XMM2

0x4afbfa VMOVSD	(%R15,%R10,8),%XMM3    [7]

0x4afc00 MOV	-0x10(%RAX,%R14,8),%RCX    [8]

0x4afc05 MOV	(%RAX,%R14,8),%RDI    [8]

0x4afc09 VMOVLPS	%XMM1,(%RDI,%R13,8)    [5]

0x4afc0f LEA	(%RCX,%R13,1),%RBX

0x4afc13 VMOVLPS	%XMM2,(%RDI,%RBX,8)    [5]

0x4afc18 VXORPS	%XMM0,%XMM3,%XMM1

0x4afc1c LEA	(%R13,%RCX,2),%RCX

0x4afc21 VMOVLPS	%XMM1,(%RDI,%RCX,8)    [5]

0x4afc26 ADD	$0x2,%R10

0x4afc2a ADD	$0xa,%R14

0x4afc2e CMP	%R10,%R11

0x4afc31 JNE	4afb80

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 244 - 263

--------------------------------------------------------------------------------

244:         *(_base + M * i) = rhs[i];

[...]

263:   inline Accessor operator()(size_t i) { return Accessor(myData + i, nGhosts); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 182 - 182

--------------------------------------------------------------------------------

182:       inverse[d] = -X[d];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h: 440 - 442

--------------------------------------------------------------------------------

440:     for (size_t i = iat + 1; i < num_targets_; ++i)

441:     {

442:       distances_[i][iat]     = temp_r_[i];

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::ParticleSet::acce[...]	ParticleSet.cpp:389	exec
○	main.extracted.107	miniqmc.cpp:452	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.46
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::update(int)
Source	VectorSoAContainer.h:244-244,VectorSoAContainer.h:263-263,TinyVector.h:182-182,OhmmsVector.h:223-223,SoaDistanceTableAAOMPTarget.h:440-442
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	0.73
Front-end cycles	5.83
P0 cycles	2.17
P1 cycles	2.33
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	4.00
P5 cycles	2.00
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	14.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.17
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	4.00
Stride n	2.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	54.55
Vectorization ratio load	0.00
Vectorization ratio store	75.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	15.91
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.46
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::update(int)
Source	VectorSoAContainer.h:244-244,VectorSoAContainer.h:263-263,TinyVector.h:182-182,OhmmsVector.h:223-223,SoaDistanceTableAAOMPTarget.h:440-442
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	0.73
Front-end cycles	5.83
P0 cycles	2.17
P1 cycles	2.33
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	4.00
P5 cycles	2.00
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	14.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.17
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	4.00
Stride n	2.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	54.55
Vectorization ratio load	0.00
Vectorization ratio store	75.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	15.91
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::update(int)
Source file and lines	SoaDistanceTableAAOMPTarget.h:440-442
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:182
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:440-442

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 4.00 cycles (1.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 5.83 to 0.73 cycles (8.00x speedup).

Details

54% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
75% of SSE/AVX stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	36
nb uops	35
loop length	183
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.17	2.33	4.67	4.67	4.00	2.00	0.50	4.00	4.00	4.00	0.00	4.67
cycles	2.17	2.33	4.67	4.67	4.00	2.00	0.50	4.00	4.00	4.00	0.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.83
Dispatch	4.67
Data deps.	1.00
Overall L1	5.83

Vectorization ratios

all	54%
load	0%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.97 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.83 to 4.67 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 4afb80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x28(%RSI,%R14,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x8(%R8,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM1,(%RBX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM1,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD -0x8(%R12,%R10,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD -0x8(%R15,%R10,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM3,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
MOV -0x38(%RAX,%R14,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x28(%RAX,%R14,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVLPS %XMM1,(%RDI,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
LEA (%RBX,%R13,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM2,(%RDI,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
LEA (%R13,%RBX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM3,(%RDI,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
MOV (%RSI,%R14,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R8,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM1,(%RCX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM1,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD (%R12,%R10,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD (%R15,%R10,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x10(%RAX,%R14,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R14,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVLPS %XMM1,(%RDI,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
LEA (%RCX,%R13,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM2,(%RDI,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
VXORPS %XMM0,%XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
LEA (%R13,%RCX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM1,(%RDI,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
ADD $0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0xa,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4afb80 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::update(int)
Source file and lines	SoaDistanceTableAAOMPTarget.h:440-442
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:182
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:440-442

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 4.00 cycles (1.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

54% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
75% of SSE/AVX stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	36
nb uops	35
loop length	183
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.17	2.33	4.67	4.67	4.00	2.00	0.50	4.00	4.00	4.00	0.00	4.67
cycles	2.17	2.33	4.67	4.67	4.00	2.00	0.50	4.00	4.00	4.00	0.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.83
Dispatch	4.67
Data deps.	1.00
Overall L1	5.83

Vectorization ratios

all	54%
load	0%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.97 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4afb80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x28(%RSI,%R14,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x8(%R8,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM1,(%RBX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM1,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD -0x8(%R12,%R10,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD -0x8(%R15,%R10,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM3,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
MOV -0x38(%RAX,%R14,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x28(%RAX,%R14,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVLPS %XMM1,(%RDI,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
LEA (%RBX,%R13,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM2,(%RDI,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
LEA (%R13,%RBX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM3,(%RDI,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
MOV (%RSI,%R14,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R8,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM1,(%RCX,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM1,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD (%R12,%R10,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPS %XMM0,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD (%R15,%R10,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x10(%RAX,%R14,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R14,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVLPS %XMM1,(%RDI,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
LEA (%RCX,%R13,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM2,(%RDI,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
VXORPS %XMM0,%XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
LEA (%R13,%RCX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVLPS %XMM1,(%RDI,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	vect (12.5%)
ADD $0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0xa,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4afb80 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code