OV - exec - Loop 1399

	Loop Id: 1399	Module: exec	Source: ParticleBConds3DSoa.h:235-256	Coverage: 1.44%

0x46fc70 LEA	(%R9,%R12,1),%R15D

0x46fc74 MOVSXD	%R15D,%R15

0x46fc77 VMOVUPD	(%RDX,%R15,8),%YMM7    [8]

0x46fc7d VMOVUPD	0x20(%RDX,%R15,8),%YMM8    [8]

0x46fc84 VMOVUPD	0x40(%RDX,%R15,8),%YMM9    [8]

0x46fc8b VMOVUPD	0x60(%RDX,%R15,8),%YMM11    [8]

0x46fc92 VSUBPD	%YMM2,%YMM7,%YMM10

0x46fc96 VSUBPD	%YMM2,%YMM8,%YMM17

0x46fc9c VSUBPD	%YMM2,%YMM9,%YMM18

0x46fca2 VSUBPD	%YMM2,%YMM11,%YMM19

0x46fca8 VMOVUPD	(%R10,%R15,8),%YMM7    [3]

0x46fcae VMOVUPD	0x20(%R10,%R15,8),%YMM8    [3]

0x46fcb5 VMOVUPD	0x40(%R10,%R15,8),%YMM9    [3]

0x46fcbc VMOVUPD	0x60(%R10,%R15,8),%YMM11    [3]

0x46fcc3 VSUBPD	%YMM3,%YMM11,%YMM21

0x46fcc9 VSUBPD	%YMM3,%YMM9,%YMM22

0x46fccf VSUBPD	%YMM3,%YMM8,%YMM24

0x46fcd5 VMOVUPD	(%RSI,%R15,8),%YMM8    [5]

0x46fcdb VMOVUPD	0x20(%RSI,%R15,8),%YMM9    [5]

0x46fce2 VMOVUPD	0x40(%RSI,%R15,8),%YMM12    [5]

0x46fce9 VMOVUPD	0x60(%RSI,%R15,8),%YMM13    [5]

0x46fcf0 VSUBPD	%YMM3,%YMM7,%YMM26

0x46fcf6 VSUBPD	%YMM4,%YMM8,%YMM11

0x46fcfa VSUBPD	%YMM4,%YMM9,%YMM20

0x46fd00 VSUBPD	%YMM4,%YMM12,%YMM23

0x46fd06 VSUBPD	%YMM4,%YMM13,%YMM25

0x46fd0c VBROADCASTSD	0x48(%RDI),%YMM8    [2]

0x46fd12 VMULPD	%YMM19,%YMM8,%YMM12

0x46fd18 VMULPD	%YMM18,%YMM8,%YMM13

0x46fd1e VMULPD	%YMM17,%YMM8,%YMM7

0x46fd24 VMULPD	%YMM10,%YMM8,%YMM8

0x46fd29 VBROADCASTSD	0x50(%RDI),%YMM9    [2]

0x46fd2f VFMADD231PD	%YMM26,%YMM9,%YMM8

0x46fd35 VFMADD231PD	%YMM24,%YMM9,%YMM7

0x46fd3b VFMADD231PD	%YMM22,%YMM9,%YMM13

0x46fd41 VBROADCASTSD	0x60(%RDI),%YMM27    [2]

0x46fd48 VMULPD	%YMM10,%YMM27,%YMM15

0x46fd4e VMULPD	%YMM17,%YMM27,%YMM16

0x46fd54 VMULPD	%YMM18,%YMM27,%YMM14

0x46fd5a VFMADD231PD	%YMM9,%YMM21,%YMM12

0x46fd60 VMULPD	%YMM19,%YMM27,%YMM9

0x46fd66 VBROADCASTSD	0x68(%RDI),%YMM27    [2]

0x46fd6d VFMADD231PD	%YMM21,%YMM27,%YMM9

0x46fd73 VFMADD231PD	%YMM22,%YMM27,%YMM14

0x46fd79 VBROADCASTSD	0x78(%RDI),%YMM28    [2]

0x46fd80 VFMADD231PD	%YMM24,%YMM27,%YMM16

0x46fd86 VMULPD	%YMM19,%YMM28,%YMM19

0x46fd8c VMULPD	%YMM18,%YMM28,%YMM18

0x46fd92 VMULPD	%YMM17,%YMM28,%YMM17

0x46fd98 VMULPD	%YMM10,%YMM28,%YMM10

0x46fd9e VBROADCASTSD	0x80(%RDI),%YMM28    [2]

0x46fda5 VFMADD231PD	%YMM27,%YMM26,%YMM15

0x46fdab VFMADD231PD	%YMM26,%YMM28,%YMM10

0x46fdb1 VBROADCASTSD	0x58(%RDI),%YMM26    [2]

0x46fdb8 VFMADD231PD	%YMM25,%YMM26,%YMM12

0x46fdbe VFMADD231PD	%YMM23,%YMM26,%YMM13

0x46fdc4 VFMADD231PD	%YMM20,%YMM26,%YMM7

0x46fdca VFMADD231PD	%YMM26,%YMM11,%YMM8

0x46fdd0 VBROADCASTSD	0x70(%RDI),%YMM26    [2]

0x46fdd7 VFMADD231PD	%YMM11,%YMM26,%YMM15

0x46fddd VFMADD231PD	%YMM20,%YMM26,%YMM16

0x46fde3 VFMADD231PD	%YMM23,%YMM26,%YMM14

0x46fde9 VFMADD231PD	%YMM24,%YMM28,%YMM17

0x46fdef VFMADD231PD	%YMM26,%YMM25,%YMM9

0x46fdf5 VFMADD231PD	%YMM22,%YMM28,%YMM18

0x46fdfb VFMADD231PD	%YMM21,%YMM28,%YMM19

0x46fe01 VBROADCASTSD	0x88(%RDI),%YMM21    [2]

0x46fe08 VFMADD231PD	%YMM25,%YMM21,%YMM19

0x46fe0e VFMADD231PD	%YMM23,%YMM21,%YMM18

0x46fe14 VMOVDQA64	%YMM6,%YMM22

0x46fe1a VFMADD231PD	%YMM20,%YMM21,%YMM17

0x46fe20 VPTERNLOGQ	$-0x8,%YMM5,%YMM8,%YMM22

0x46fe27 VADDPD	%YMM22,%YMM8,%YMM20

0x46fe2d VMOVDQA64	%YMM6,%YMM22

0x46fe33 VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM22

0x46fe3a VADDPD	%YMM22,%YMM7,%YMM22

0x46fe40 VRNDSCALEPD	$0xb,%YMM20,%YMM20

0x46fe47 VRNDSCALEPD	$0xb,%YMM22,%YMM22

0x46fe4e VMOVDQA64	%YMM6,%YMM23

0x46fe54 VPTERNLOGQ	$-0x8,%YMM5,%YMM13,%YMM23

0x46fe5b VADDPD	%YMM23,%YMM13,%YMM23

0x46fe61 VMOVDQA64	%YMM6,%YMM24

0x46fe67 VRNDSCALEPD	$0xb,%YMM23,%YMM23

0x46fe6e VPTERNLOGQ	$-0x8,%YMM5,%YMM12,%YMM24

0x46fe75 VADDPD	%YMM24,%YMM12,%YMM24

0x46fe7b VRNDSCALEPD	$0xb,%YMM24,%YMM24

0x46fe82 VMOVDQA64	%YMM6,%YMM25

0x46fe88 VPTERNLOGQ	$-0x8,%YMM5,%YMM9,%YMM25

0x46fe8f VADDPD	%YMM25,%YMM9,%YMM25

0x46fe95 VRNDSCALEPD	$0xb,%YMM25,%YMM25

0x46fe9c VMOVDQA64	%YMM6,%YMM26

0x46fea2 VPTERNLOGQ	$-0x8,%YMM5,%YMM14,%YMM26

0x46fea9 VADDPD	%YMM26,%YMM14,%YMM26

0x46feaf VRNDSCALEPD	$0xb,%YMM26,%YMM26

0x46feb6 VFMADD231PD	%YMM11,%YMM21,%YMM10

0x46febc VMOVDQA	%YMM6,%YMM11

0x46fec0 VPTERNLOGQ	$-0x8,%YMM5,%YMM16,%YMM11

0x46fec7 VADDPD	%YMM11,%YMM16,%YMM11

0x46fecd VRNDSCALEPD	$0xb,%YMM11,%YMM21

0x46fed4 VSUBPD	%YMM24,%YMM12,%YMM12

0x46feda VSUBPD	%YMM23,%YMM13,%YMM11

0x46fee0 VMOVDQA	%YMM6,%YMM13

0x46fee4 VPTERNLOGQ	$-0x8,%YMM5,%YMM15,%YMM13

0x46feeb VADDPD	%YMM13,%YMM15,%YMM13

0x46fef0 VROUNDPD	$0xb,%YMM13,%YMM13

0x46fef6 VSUBPD	%YMM22,%YMM7,%YMM7

0x46fefc VSUBPD	%YMM20,%YMM8,%YMM8

0x46ff02 VMOVDQA64	%YMM6,%YMM20

0x46ff08 VPTERNLOGQ	$-0x8,%YMM5,%YMM10,%YMM20

0x46ff0f VADDPD	%YMM20,%YMM10,%YMM20

0x46ff15 VRNDSCALEPD	$0xb,%YMM20,%YMM23

0x46ff1c VSUBPD	%YMM13,%YMM15,%YMM13

0x46ff21 VSUBPD	%YMM21,%YMM16,%YMM15

0x46ff27 VMOVDQA64	%YMM6,%YMM16

0x46ff2d VPTERNLOGQ	$-0x8,%YMM5,%YMM17,%YMM16

0x46ff34 VADDPD	%YMM16,%YMM17,%YMM16

0x46ff3a VRNDSCALEPD	$0xb,%YMM16,%YMM24

0x46ff41 VMOVDQA64	%YMM6,%YMM16

0x46ff47 VSUBPD	%YMM26,%YMM14,%YMM20

0x46ff4d VPTERNLOGQ	$-0x8,%YMM5,%YMM18,%YMM16

0x46ff54 VADDPD	%YMM16,%YMM18,%YMM14

0x46ff5a VROUNDPD	$0xb,%YMM14,%YMM14

0x46ff60 VMOVDQA64	%YMM6,%YMM16

0x46ff66 VPTERNLOGQ	$-0x8,%YMM5,%YMM19,%YMM16

0x46ff6d VSUBPD	%YMM25,%YMM9,%YMM21

0x46ff73 VADDPD	%YMM16,%YMM19,%YMM9

0x46ff79 VROUNDPD	$0xb,%YMM9,%YMM9

0x46ff7f VSUBPD	%YMM9,%YMM19,%YMM22

0x46ff85 VBROADCASTSD	(%RDI),%YMM25    [2]

0x46ff8b VSUBPD	%YMM14,%YMM18,%YMM19

0x46ff91 VMULPD	%YMM8,%YMM25,%YMM9

0x46ff97 VMULPD	%YMM7,%YMM25,%YMM14

0x46ff9d VMULPD	%YMM11,%YMM25,%YMM16

0x46ffa3 VMULPD	%YMM12,%YMM25,%YMM18

0x46ffa9 VBROADCASTSD	0x8(%RDI),%YMM25    [2]

0x46ffb0 VSUBPD	%YMM24,%YMM17,%YMM17

0x46ffb6 VFMADD231PD	%YMM21,%YMM25,%YMM18

0x46ffbc VFMADD231PD	%YMM20,%YMM25,%YMM16

0x46ffc2 VFMADD231PD	%YMM15,%YMM25,%YMM14

0x46ffc8 VFMADD231PD	%YMM25,%YMM13,%YMM9

0x46ffce VBROADCASTSD	0x10(%RDI),%YMM24    [2]

0x46ffd5 VSUBPD	%YMM23,%YMM10,%YMM23

0x46ffdb VFMADD231PD	%YMM24,%YMM23,%YMM9

0x46ffe1 VFMADD231PD	%YMM24,%YMM17,%YMM14

0x46ffe7 VFMADD231PD	%YMM24,%YMM19,%YMM16

0x46ffed VFMADD231PD	%YMM24,%YMM22,%YMM18

0x46fff3 VMOVUPD	%YMM18,0x60(%R8,%R15,8)    [1]

0x46fffb VMOVUPD	%YMM16,0x40(%R8,%R15,8)    [1]

0x470003 VMOVUPD	%YMM14,0x20(%R8,%R15,8)    [1]

0x47000a VMOVUPD	%YMM9,(%R8,%R15,8)    [1]

0x470010 VBROADCASTSD	0x18(%RDI),%YMM24    [2]

0x470017 VMULPD	%YMM12,%YMM24,%YMM10

0x47001d VMULPD	%YMM8,%YMM24,%YMM25

0x470023 VMULPD	%YMM7,%YMM24,%YMM26

0x470029 VBROADCASTSD	0x20(%RDI),%YMM27    [2]

0x470030 VMULPD	%YMM11,%YMM24,%YMM24

0x470036 VFMADD231PD	%YMM20,%YMM27,%YMM24

0x47003c VFMADD231PD	%YMM15,%YMM27,%YMM26

0x470042 VFMADD231PD	%YMM13,%YMM27,%YMM25

0x470048 VFMADD231PD	%YMM27,%YMM21,%YMM10

0x47004e VBROADCASTSD	0x28(%RDI),%YMM27    [2]

0x470055 VFMADD231PD	%YMM22,%YMM27,%YMM10

0x47005b VFMADD231PD	%YMM17,%YMM27,%YMM26

0x470061 VFMADD231PD	%YMM27,%YMM19,%YMM24

0x470067 VMOVUPD	%YMM24,0x40(%RBX,%R15,8)    [6]

0x47006f VMOVUPD	%YMM26,0x20(%RBX,%R15,8)    [6]

0x470077 VFMADD231PD	%YMM23,%YMM27,%YMM25

0x47007d VMOVUPD	%YMM25,(%RBX,%R15,8)    [6]

0x470084 VMOVUPD	%YMM10,0x60(%RBX,%R15,8)    [6]

0x47008b VBROADCASTSD	0x30(%RDI),%YMM27    [2]

0x470092 VMULPD	%YMM12,%YMM27,%YMM12

0x470098 VMULPD	%YMM8,%YMM27,%YMM8

0x47009e VMULPD	%YMM7,%YMM27,%YMM7

0x4700a4 VMULPD	%YMM11,%YMM27,%YMM11

0x4700aa VBROADCASTSD	0x38(%RDI),%YMM27    [2]

0x4700b1 VFMADD231PD	%YMM20,%YMM27,%YMM11

0x4700b7 VFMADD231PD	%YMM15,%YMM27,%YMM7

0x4700bd VFMADD231PD	%YMM13,%YMM27,%YMM8

0x4700c3 VFMADD231PD	%YMM21,%YMM27,%YMM12

0x4700c9 VBROADCASTSD	0x40(%RDI),%YMM13    [2]

0x4700cf VFMADD231PD	%YMM22,%YMM13,%YMM12

0x4700d5 VFMADD231PD	%YMM23,%YMM13,%YMM8

0x4700db VFMADD231PD	%YMM17,%YMM13,%YMM7

0x4700e1 VFMADD231PD	%YMM19,%YMM13,%YMM11

0x4700e7 VMULPD	%YMM16,%YMM16,%YMM13

0x4700ed VMULPD	%YMM18,%YMM18,%YMM15

0x4700f3 VMOVUPD	%YMM11,0x40(%R11,%R15,8)    [4]

0x4700fa VMULPD	%YMM9,%YMM9,%YMM9

0x4700ff VMULPD	%YMM14,%YMM14,%YMM14

0x470104 VFMADD231PD	%YMM26,%YMM26,%YMM14

0x47010a VFMADD231PD	%YMM25,%YMM25,%YMM9

0x470110 VMOVUPD	%YMM7,0x20(%R11,%R15,8)    [4]

0x470117 VFMADD231PD	%YMM10,%YMM10,%YMM15

0x47011c VFMADD231PD	%YMM24,%YMM24,%YMM13

0x470122 VFMADD231PD	%YMM11,%YMM11,%YMM13

0x470127 VFMADD231PD	%YMM12,%YMM12,%YMM15

0x47012c VMOVUPD	%YMM8,(%R11,%R15,8)    [4]

0x470132 VFMADD231PD	%YMM8,%YMM8,%YMM9

0x470137 VFMADD231PD	%YMM7,%YMM7,%YMM14

0x47013c VSQRTPD	%YMM14,%YMM7

0x470141 VSQRTPD	%YMM9,%YMM8

0x470146 VMOVUPD	%YMM12,0x60(%R11,%R15,8)    [4]

0x47014d VSQRTPD	%YMM15,%YMM9

0x470152 VSQRTPD	%YMM13,%YMM10

0x470157 VMOVUPD	%YMM10,0x40(%RCX,%R15,8)    [7]

0x47015e VMOVUPD	%YMM9,0x60(%RCX,%R15,8)    [7]

0x470165 VMOVUPD	%YMM8,(%RCX,%R15,8)    [7]

0x47016b VMOVUPD	%YMM7,0x20(%RCX,%R15,8)    [7]

0x470172 ADD	$0x10,%R12D

0x470176 CMP	%R13D,%R12D

0x470179 JBE	46fc70

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 235 - 256

--------------------------------------------------------------------------------

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

Coverage (%)	Name	Source Location	Module
►40.32+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:283	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►37.20+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:275	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►10.51+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:366	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►9.04+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:185	exec
○	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	main.extracted.112	miniqmc.cpp:396	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►2.93+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:361	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.67
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:235-256
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	60.00
CQA cycles if no scalar integer	60.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	36.00
Front-end cycles	37.00
P0 cycles	59.00
P1 cycles	60.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	8.00
P5 cycles	42.00
P6 cycles	2.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	2.00
P11 cycles	10.00
DIV/SQRT cycles	36.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	211.00
Nb uops	222.00
Nb loads	30.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	144.00
Nb FLOP mul	112.00
Nb FLOP fma	224.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.33
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	91.26
Vectorization ratio load	40.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	46.72
Vector-efficiency ratio load	27.50
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	37.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.67
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:235-256
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	60.00
CQA cycles if no scalar integer	60.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	36.00
Front-end cycles	37.00
P0 cycles	59.00
P1 cycles	60.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	8.00
P5 cycles	42.00
P6 cycles	2.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	2.00
P11 cycles	10.00
DIV/SQRT cycles	36.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	211.00
Nb uops	222.00
Nb loads	30.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	144.00
Nb FLOP mul	112.00
Nb FLOP fma	224.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.33
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	91.26
Vectorization ratio load	40.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	46.72
Vector-efficiency ratio load	27.50
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	37.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:235-256
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:235-256.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

91% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALEPD: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
VROUNDPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 28 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 28 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

136 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary loop is loading 528 bytes (66 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.69 FP operations per loaded or stored byte.

General properties

nb instructions	211
nb uops	222
loop length	1295
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	27
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	37.00 cycles
front end	37.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.00	59.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00
cycles	59.00	60.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	36.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	37.00
Dispatch	60.00
DIV/SQRT	36.00
Data deps.	1.00
Overall L1	60.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	90%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	40%

INT+FP

all	91%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	27%

INT+FP

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.00 cycles. At this rate:

4% of peak load performance is reached (8.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46fc70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R9,%R12,1),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R15D,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVUPD (%RDX,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RDX,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM2,%YMM7,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM8,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM9,%YMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM11,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R10,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R10,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R10,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM11,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM9,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM8,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RSI,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RSI,%R15,8),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RSI,%R15,8),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM7,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM8,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM9,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM12,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM13,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x48(%RDI),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM19,%YMM8,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM8,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x50(%RDI),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM26,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM9,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM9,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x60(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM10,%YMM27,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM21,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x68(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM21,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x78(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM24,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x80(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM27,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x58(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM26,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM11,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x70(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM11,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x88(%RDI),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM21,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %YMM20,%YMM21,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM8,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM8,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM7,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM7,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM20	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM22,%YMM22	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM13,%YMM23	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM23,%YMM13,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VRNDSCALEPD $0xb,%YMM23,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM12,%YMM24	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM24,%YMM12,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM24,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM9,%YMM25	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM25,%YMM9,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM25,%YMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM14,%YMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM26,%YMM14,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM26,%YMM26	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VFMADD231PD %YMM11,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM16,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM11,%YMM16,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM11,%YMM21	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM24,%YMM12,%YMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM23,%YMM13,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM15,%YMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM13,%YMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM22,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM20,%YMM8,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM10,%YMM20	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM20,%YMM10,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM21,%YMM16,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM17,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM17,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM16,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VSUBPD %YMM26,%YMM14,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM18,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM18,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM14,%YMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM19,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VSUBPD %YMM25,%YMM9,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM16,%YMM19,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM9,%YMM9	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM9,%YMM19,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD (%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM14,%YMM18,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM8,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM12,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x8(%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM24,%YMM17,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM13,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x10(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM23,%YMM10,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM23,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM17,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM19,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM22,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM18,0x60(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM16,0x40(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x18(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM24,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM24,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM24,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x20(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM11,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM27,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x28(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM27,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM19,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM24,0x40(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM26,0x20(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM25,(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM10,0x60(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x30(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x38(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM20,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x40(%RDI),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM13,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM13,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM13,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM13,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM18,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM11,0x40(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD %YMM9,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM24,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM11,%YMM11,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM12,%YMM12,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM8,(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM14,%YMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM12,0x60(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSQRTPD %YMM15,%YMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM13,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM10,0x40(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,0x60(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x10,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R13D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JBE 46fc70 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:235-256
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

91% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALEPD: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
VROUNDPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 28 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 28 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

136 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary loop is loading 528 bytes (66 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.69 FP operations per loaded or stored byte.

General properties

nb instructions	211
nb uops	222
loop length	1295
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	27
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	37.00 cycles
front end	37.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.00	59.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00
cycles	59.00	60.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	36.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	37.00
Dispatch	60.00
DIV/SQRT	36.00
Data deps.	1.00
Overall L1	60.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	90%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	40%

INT+FP

all	91%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	27%

INT+FP

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.00 cycles. At this rate:

4% of peak load performance is reached (8.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46fc70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R9,%R12,1),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R15D,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVUPD (%RDX,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RDX,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM2,%YMM7,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM8,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM9,%YMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM11,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R10,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R10,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R10,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM11,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM9,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM8,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RSI,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RSI,%R15,8),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RSI,%R15,8),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM7,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM8,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM9,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM12,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM13,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x48(%RDI),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM19,%YMM8,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM8,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x50(%RDI),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM26,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM9,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM9,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x60(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM10,%YMM27,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM21,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x68(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM21,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x78(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM24,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x80(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM27,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x58(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM26,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM11,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x70(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM11,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x88(%RDI),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM21,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %YMM20,%YMM21,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM8,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM8,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM7,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM7,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM20	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM22,%YMM22	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM13,%YMM23	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM23,%YMM13,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VRNDSCALEPD $0xb,%YMM23,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM12,%YMM24	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM24,%YMM12,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM24,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM9,%YMM25	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM25,%YMM9,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM25,%YMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM14,%YMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM26,%YMM14,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM26,%YMM26	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VFMADD231PD %YMM11,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM16,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM11,%YMM16,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM11,%YMM21	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM24,%YMM12,%YMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM23,%YMM13,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM15,%YMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM13,%YMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM22,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM20,%YMM8,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM10,%YMM20	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM20,%YMM10,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM21,%YMM16,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM17,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM17,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM16,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VSUBPD %YMM26,%YMM14,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM18,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM18,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM14,%YMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM19,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VSUBPD %YMM25,%YMM9,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM16,%YMM19,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM9,%YMM9	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM9,%YMM19,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD (%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM14,%YMM18,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM8,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM12,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x8(%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM24,%YMM17,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM13,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x10(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM23,%YMM10,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM23,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM17,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM19,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM22,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM18,0x60(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM16,0x40(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x18(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM24,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM24,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM24,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x20(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM11,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM27,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x28(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM27,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM19,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM24,0x40(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM26,0x20(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM25,(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM10,0x60(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x30(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x38(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM20,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x40(%RDI),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM13,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM13,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM13,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM13,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM18,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM11,0x40(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD %YMM9,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM24,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM11,%YMM11,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM12,%YMM12,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM8,(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM14,%YMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM12,0x60(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSQRTPD %YMM15,%YMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM13,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM10,0x40(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,0x60(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x10,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R13D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JBE 46fc70 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code