OV - exec - Function qmcplusplus::TimerType<std::chrono::_V2::system

	Function: qmcplusplus::TimerType<std::chrono::_V2::system_clock>::stop()	Module: exec	Source: NewTimer.cpp:85-120 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 85 - 120

--------------------------------------------------------------------------------

85: {

86:   if (active)

[...]

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       std::chrono::duration<double> elapsed = CLOCK::now() - start_time;

105:       total_time += elapsed.count();

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed.count();

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono: 227 - 666

--------------------------------------------------------------------------------

227: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

666: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

0x48e150 PUSH	%RBP

0x48e151 MOV	%RSP,%RBP

0x48e154 PUSH	%R15

0x48e156 PUSH	%R14

0x48e158 PUSH	%R13

0x48e15a PUSH	%R12

0x48e15c PUSH	%RBX

0x48e15d SUB	$0x18,%RSP

0x48e161 CMPB	$0,0x38(%RDI)

0x48e165 JE	48e2d7

0x48e16b MOV	%RDI,%RBX

0x48e16e CALL	404600 <omp_get_level@plt>

0x48e173 TEST	%EAX,%EAX

0x48e175 JLE	48e261

0x48e17b MOV	%RBX,-0x40(%RBP)

0x48e17f MOV	$0x1,%R14B

0x48e182 MOV	%EAX,-0x2c(%RBP)

0x48e185 CMP	$0x8,%EAX

0x48e188 JB	48e22d

0x48e18e MOV	-0x2c(%RBP),%EAX

0x48e191 MOV	%EAX,%ECX

0x48e193 SHR	$0x3,%ECX

0x48e196 MOV	$0x1,%R14B

0x48e199 MOV	%EAX,%R15D

0x48e19c NOPL	(%RAX)

(1633) 0x48e1a0 MOV	%ECX,-0x38(%RBP)

(1633) 0x48e1a3 MOV	%R15D,%EDI

(1633) 0x48e1a6 CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e1ab MOV	%EAX,%R12D

(1633) 0x48e1ae LEA	-0x1(%R15),%EDI

(1633) 0x48e1b2 CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e1b7 MOV	%EAX,%R13D

(1633) 0x48e1ba OR	%R12D,%R13D

(1633) 0x48e1bd LEA	-0x2(%R15),%EDI

(1633) 0x48e1c1 CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e1c6 MOV	%EAX,%R12D

(1633) 0x48e1c9 LEA	-0x3(%R15),%EDI

(1633) 0x48e1cd CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e1d2 MOV	%EAX,%EBX

(1633) 0x48e1d4 OR	%R12D,%EBX

(1633) 0x48e1d7 OR	%R13D,%EBX

(1633) 0x48e1da LEA	-0x4(%R15),%EDI

(1633) 0x48e1de CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e1e3 MOV	%EAX,%R12D

(1633) 0x48e1e6 LEA	-0x5(%R15),%EDI

(1633) 0x48e1ea CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e1ef MOV	%EAX,%R13D

(1633) 0x48e1f2 OR	%R12D,%R13D

(1633) 0x48e1f5 OR	%EBX,%R13D

(1633) 0x48e1f8 LEA	-0x6(%R15),%EDI

(1633) 0x48e1fc CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e201 MOV	%EAX,%EBX

(1633) 0x48e203 LEA	-0x7(%R15),%EDI

(1633) 0x48e207 CALL	404240 <omp_get_ancestor_thread_num@plt>

(1633) 0x48e20c MOV	-0x38(%RBP),%ECX

(1633) 0x48e20f OR	%EBX,%EAX

(1633) 0x48e211 MOVZX	%R14B,%R14D

(1633) 0x48e215 OR	%R13D,%EAX

(1633) 0x48e218 MOV	$0,%EAX

(1633) 0x48e21d CMOVNE	%EAX,%R14D

(1633) 0x48e221 ADD	$-0x8,%R15D

(1633) 0x48e225 DEC	%ECX

(1633) 0x48e227 JNE	48e1a0

0x48e22d MOV	-0x2c(%RBP),%R15D

0x48e231 MOV	%R15D,%EAX

0x48e234 AND	$0x7ffffff8,%EAX

0x48e239 SUB	%EAX,%R15D

0x48e23c JE	48e257

0x48e23e XOR	%EBX,%EBX

(1632) 0x48e240 MOV	%R15D,%EDI

(1632) 0x48e243 CALL	404240 <omp_get_ancestor_thread_num@plt>

(1632) 0x48e248 TEST	%EAX,%EAX

(1632) 0x48e24a MOVZX	%R14B,%R14D

(1632) 0x48e24e CMOVNE	%EBX,%R14D

(1632) 0x48e252 DEC	%R15D

(1632) 0x48e255 JNE	48e240

0x48e257 TEST	$0x1,%R14B

0x48e25b MOV	-0x40(%RBP),%RBX

0x48e25f JE	48e2d7

0x48e261 CALL	4046c0 <_ZNSt6chrono3_V212system_clock3nowEv@plt>

0x48e266 SUB	(%RBX),%RAX

0x48e269 VCVTSI2SD	%RAX,%XMM0,%XMM0

0x48e26e VMULSD	0x70092(%RIP),%XMM0,%XMM0

0x48e276 VMOVSD	%XMM0,-0x38(%RBP)

0x48e27b VADDSD	0x8(%RBX),%XMM0,%XMM0

0x48e280 VMOVSD	%XMM0,0x8(%RBX)

0x48e285 INCQ	0x10(%RBX)

0x48e289 LEA	0x68(%RBX),%RDI

0x48e28d LEA	0x50(%RBX),%R14

0x48e291 MOV	%R14,%RSI

0x48e294 CALL	48e2f0 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_>

0x48e299 VMOVSD	-0x38(%RBP),%XMM0

0x48e29e VADDSD	(%RAX),%XMM0,%XMM0

0x48e2a2 VMOVSD	%XMM0,(%RAX)

0x48e2a6 LEA	0x98(%RBX),%RDI

0x48e2ad MOV	%R14,%RSI

0x48e2b0 CALL	48e480 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_>

0x48e2b5 INCQ	(%RAX)

0x48e2b8 MOV	0x48(%RBX),%RDI

0x48e2bc TEST	%RDI,%RDI

0x48e2bf JE	48e2d7

0x48e2c1 MOV	%RBX,%RSI

0x48e2c4 ADD	$0x18,%RSP

0x48e2c8 POP	%RBX

0x48e2c9 POP	%R12

0x48e2cb POP	%R13

0x48e2cd POP	%R14

0x48e2cf POP	%R15

0x48e2d1 POP	%RBP

0x48e2d2 JMP	494150

0x48e2d7 ADD	$0x18,%RSP

0x48e2db POP	%RBX

0x48e2dc POP	%R12

0x48e2de POP	%R13

0x48e2e0 POP	%R14

0x48e2e2 POP	%R15

0x48e2e4 POP	%RBP

0x48e2e5 RET

0x48e2e6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►24.97+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:445	exec
○	qmcplusplus::ParticleSet::acce[...]	ParticleSet.cpp:389	exec
○	main.extracted.107	miniqmc.cpp:452	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►23.62+	qmcplusplus::ParticleSet::acce[...]	ParticleSet.cpp:389	exec
○	main.extracted.107	miniqmc.cpp:452	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►5.41+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:101	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►5.41+	qmcplusplus::SoaDistanceTableA[...]	NewTimer.h:249	exec
○	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:134	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►4.16+	miniqmcreference::einspline_sp[...]	NewTimer.h:249	exec
○	qmcplusplus::SPOSet::evaluateD[...]	OhmmsVector.h:178	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►3.85+	qmcplusplus::ParticleSet::acce[...]	ParticleSet.cpp:395	exec
○	main.extracted.107	miniqmc.cpp:452	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►3.85+	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:345	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►3.75+	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:245	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:134	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►2.81+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:368	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►2.71+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►2.71+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:233	exec
○	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:134	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►1.98+	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►1.98+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►1.14+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:287	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►1.04+	qmcplusplus::WaveFunction::acc[...]	WaveFunction.cpp:225	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227,666

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.83 to 3.00 cycles (4.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.83 to 0.51 cycles (26.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_level@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:99
std::chrono::_V2::system_clock::now(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:104
std::map
, double, std::less
>, std::allocator
const, double> > >::operator[](qmcplusplus::StackKeyParam<2> const&): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:108
std::map
, long, std::less
>, std::allocator
const, long> > >::operator[](qmcplusplus::StackKeyParam<2> const&): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:109

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:106
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:109
VCVTSI2SD: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: multiply

The binary function is loading 81 bytes (10 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	74
nb uops	83
loop length	252
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.83 cycles
front end	13.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	5.10	8.33	8.33	8.50	4.90	5.00	8.50	8.50	8.50	5.00	8.33
cycles	5.00	5.10	8.33	8.33	8.50	4.90	5.00	8.50	8.50	8.50	5.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.83
Dispatch	8.50
Overall L1	13.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	10%
store	11%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.83 cycles. At this rate:

3% of peak load performance is reached (5.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.83 to 8.50 cycles (1.63x speedup).

ASM code

In the binary file, the address of the function is: 48e150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPB $0,0x38(%RDI)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (1.6%)
JE 48e2d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404600 <omp_get_level@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 48e261 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x111>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x8,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 48e22d <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0xdd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOV $0x1,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x2c(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffff8,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %EAX,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 48e257 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x107>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST $0x1,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 48e2d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CALL 4046c0 <_ZNSt6chrono3_V212system_clock3nowEv@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
SUB (%RBX),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VCVTSI2SD %RAX,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	scal (12.5%)
VMULSD 0x70092(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%RBX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INCQ 0x10(%RBX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
LEA 0x68(%RBX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x50(%RBX),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 48e2f0 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x98(%RBX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 48e480 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
INCQ (%RAX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 48e2d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 494150 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227,666

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.83 to 3.00 cycles (4.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

omp_get_level@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:99
std::chrono::_V2::system_clock::now(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:104
std::map
, double, std::less
>, std::allocator
const, double> > >::operator[](qmcplusplus::StackKeyParam<2> const&): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:108
std::map
, long, std::less
>, std::allocator
const, long> > >::operator[](qmcplusplus::StackKeyParam<2> const&): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:109

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:106
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:109
VCVTSI2SD: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: multiply

The binary function is loading 81 bytes (10 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	74
nb uops	83
loop length	252
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.83 cycles
front end	13.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	5.10	8.33	8.33	8.50	4.90	5.00	8.50	8.50	8.50	5.00	8.33
cycles	5.00	5.10	8.33	8.33	8.50	4.90	5.00	8.50	8.50	8.50	5.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.83
Dispatch	8.50
Overall L1	13.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	10%
store	11%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.83 cycles. At this rate:

3% of peak load performance is reached (5.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 48e150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPB $0,0x38(%RDI)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (1.6%)
JE 48e2d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404600 <omp_get_level@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 48e261 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x111>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x8,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 48e22d <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0xdd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOV $0x1,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x2c(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffff8,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %EAX,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 48e257 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x107>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST $0x1,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 48e2d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CALL 4046c0 <_ZNSt6chrono3_V212system_clock3nowEv@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
SUB (%RBX),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VCVTSI2SD %RAX,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	scal (12.5%)
VMULSD 0x70092(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%RBX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INCQ 0x10(%RBX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
LEA 0x68(%RBX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x50(%RBX),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 48e2f0 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x98(%RBX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 48e480 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
INCQ (%RAX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 48e2d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 494150 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::stop()–	0.02	0.02
○Loop 1632 - NewTimer.cpp:99-100 - exec	0.00	0.01
○Loop 1633 - NewTimer.cpp:86-100 - exec	0.00	0.00

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