OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds3DSoa.h:221-257 [...]	Coverage (incl. loops): 1.45% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 271 - 273

--------------------------------------------------------------------------------

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

272:   ///return the const pointer of the i-th components

273:   inline const T* restrict data(size_t i) const { return myData + i * nGhosts; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 221 - 257

--------------------------------------------------------------------------------

221:   {

222:     const T x0 = pos[0];

223:     const T y0 = pos[1];

224:     const T z0 = pos[2];

[...]

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

257:   }

0x46fbd0 PUSH	%RBP

0x46fbd1 MOV	%RSP,%RBP

0x46fbd4 PUSH	%R15

0x46fbd6 PUSH	%R14

0x46fbd8 PUSH	%R13

0x46fbda PUSH	%R12

0x46fbdc PUSH	%RBX

0x46fbdd MOV	0x10(%RBP),%EAX

0x46fbe0 MOV	%EAX,%R13D

0x46fbe3 SUB	%R9D,%R13D

0x46fbe6 JLE	470454

0x46fbec VMOVUPD	(%RSI),%XMM0

0x46fbf0 VMOVSD	0x10(%RSI),%XMM1

0x46fbf5 MOV	0x8(%RDX),%RSI

0x46fbf9 MOV	0x18(%RDX),%RDX

0x46fbfd LEA	(%RDX,%RSI,8),%R10

0x46fc01 SAL	$0x4,%RSI

0x46fc05 ADD	%RDX,%RSI

0x46fc08 MOV	0x8(%R8),%R11

0x46fc0c MOV	0x18(%R8),%R8

0x46fc10 LEA	(%R8,%R11,8),%RBX

0x46fc14 SAL	$0x4,%R11

0x46fc18 ADD	%R8,%R11

0x46fc1b MOV	%R13D,%R15D

0x46fc1e AND	$-0x4,%R15D

0x46fc22 JE	47019a

0x46fc28 MOV	%R13D,%R14D

0x46fc2b VBROADCASTSD	%XMM0,%YMM2

0x46fc30 AND	$-0x10,%R14D

0x46fc34 MOV	%R15,-0x38(%RBP)

0x46fc38 JE	4701a2

0x46fc3e MOV	%R13D,-0x2c(%RBP)

0x46fc42 LEA	-0x1(%R14),%R13D

0x46fc46 VPERMPD	$0x55,%YMM0,%YMM3

0x46fc4c VBROADCASTSD	%XMM1,%YMM4

0x46fc51 XOR	%R12D,%R12D

0x46fc54 VPBROADCASTQ	0x8d3eb(%RIP),%YMM5

0x46fc5d VPBROADCASTQ	0x939ea(%RIP),%YMM6

0x46fc66 NOPW	%CS:(%RAX,%RAX,1)

(1399) 0x46fc70 LEA	(%R9,%R12,1),%R15D

(1399) 0x46fc74 MOVSXD	%R15D,%R15

(1399) 0x46fc77 VMOVUPD	(%RDX,%R15,8),%YMM7

(1399) 0x46fc7d VMOVUPD	0x20(%RDX,%R15,8),%YMM8

(1399) 0x46fc84 VMOVUPD	0x40(%RDX,%R15,8),%YMM9

(1399) 0x46fc8b VMOVUPD	0x60(%RDX,%R15,8),%YMM11

(1399) 0x46fc92 VSUBPD	%YMM2,%YMM7,%YMM10

(1399) 0x46fc96 VSUBPD	%YMM2,%YMM8,%YMM17

(1399) 0x46fc9c VSUBPD	%YMM2,%YMM9,%YMM18

(1399) 0x46fca2 VSUBPD	%YMM2,%YMM11,%YMM19

(1399) 0x46fca8 VMOVUPD	(%R10,%R15,8),%YMM7

(1399) 0x46fcae VMOVUPD	0x20(%R10,%R15,8),%YMM8

(1399) 0x46fcb5 VMOVUPD	0x40(%R10,%R15,8),%YMM9

(1399) 0x46fcbc VMOVUPD	0x60(%R10,%R15,8),%YMM11

(1399) 0x46fcc3 VSUBPD	%YMM3,%YMM11,%YMM21

(1399) 0x46fcc9 VSUBPD	%YMM3,%YMM9,%YMM22

(1399) 0x46fccf VSUBPD	%YMM3,%YMM8,%YMM24

(1399) 0x46fcd5 VMOVUPD	(%RSI,%R15,8),%YMM8

(1399) 0x46fcdb VMOVUPD	0x20(%RSI,%R15,8),%YMM9

(1399) 0x46fce2 VMOVUPD	0x40(%RSI,%R15,8),%YMM12

(1399) 0x46fce9 VMOVUPD	0x60(%RSI,%R15,8),%YMM13

(1399) 0x46fcf0 VSUBPD	%YMM3,%YMM7,%YMM26

(1399) 0x46fcf6 VSUBPD	%YMM4,%YMM8,%YMM11

(1399) 0x46fcfa VSUBPD	%YMM4,%YMM9,%YMM20

(1399) 0x46fd00 VSUBPD	%YMM4,%YMM12,%YMM23

(1399) 0x46fd06 VSUBPD	%YMM4,%YMM13,%YMM25

(1399) 0x46fd0c VBROADCASTSD	0x48(%RDI),%YMM8

(1399) 0x46fd12 VMULPD	%YMM19,%YMM8,%YMM12

(1399) 0x46fd18 VMULPD	%YMM18,%YMM8,%YMM13

(1399) 0x46fd1e VMULPD	%YMM17,%YMM8,%YMM7

(1399) 0x46fd24 VMULPD	%YMM10,%YMM8,%YMM8

(1399) 0x46fd29 VBROADCASTSD	0x50(%RDI),%YMM9

(1399) 0x46fd2f VFMADD231PD	%YMM26,%YMM9,%YMM8

(1399) 0x46fd35 VFMADD231PD	%YMM24,%YMM9,%YMM7

(1399) 0x46fd3b VFMADD231PD	%YMM22,%YMM9,%YMM13

(1399) 0x46fd41 VBROADCASTSD	0x60(%RDI),%YMM27

(1399) 0x46fd48 VMULPD	%YMM10,%YMM27,%YMM15

(1399) 0x46fd4e VMULPD	%YMM17,%YMM27,%YMM16

(1399) 0x46fd54 VMULPD	%YMM18,%YMM27,%YMM14

(1399) 0x46fd5a VFMADD231PD	%YMM9,%YMM21,%YMM12

(1399) 0x46fd60 VMULPD	%YMM19,%YMM27,%YMM9

(1399) 0x46fd66 VBROADCASTSD	0x68(%RDI),%YMM27

(1399) 0x46fd6d VFMADD231PD	%YMM21,%YMM27,%YMM9

(1399) 0x46fd73 VFMADD231PD	%YMM22,%YMM27,%YMM14

(1399) 0x46fd79 VBROADCASTSD	0x78(%RDI),%YMM28

(1399) 0x46fd80 VFMADD231PD	%YMM24,%YMM27,%YMM16

(1399) 0x46fd86 VMULPD	%YMM19,%YMM28,%YMM19

(1399) 0x46fd8c VMULPD	%YMM18,%YMM28,%YMM18

(1399) 0x46fd92 VMULPD	%YMM17,%YMM28,%YMM17

(1399) 0x46fd98 VMULPD	%YMM10,%YMM28,%YMM10

(1399) 0x46fd9e VBROADCASTSD	0x80(%RDI),%YMM28

(1399) 0x46fda5 VFMADD231PD	%YMM27,%YMM26,%YMM15

(1399) 0x46fdab VFMADD231PD	%YMM26,%YMM28,%YMM10

(1399) 0x46fdb1 VBROADCASTSD	0x58(%RDI),%YMM26

(1399) 0x46fdb8 VFMADD231PD	%YMM25,%YMM26,%YMM12

(1399) 0x46fdbe VFMADD231PD	%YMM23,%YMM26,%YMM13

(1399) 0x46fdc4 VFMADD231PD	%YMM20,%YMM26,%YMM7

(1399) 0x46fdca VFMADD231PD	%YMM26,%YMM11,%YMM8

(1399) 0x46fdd0 VBROADCASTSD	0x70(%RDI),%YMM26

(1399) 0x46fdd7 VFMADD231PD	%YMM11,%YMM26,%YMM15

(1399) 0x46fddd VFMADD231PD	%YMM20,%YMM26,%YMM16

(1399) 0x46fde3 VFMADD231PD	%YMM23,%YMM26,%YMM14

(1399) 0x46fde9 VFMADD231PD	%YMM24,%YMM28,%YMM17

(1399) 0x46fdef VFMADD231PD	%YMM26,%YMM25,%YMM9

(1399) 0x46fdf5 VFMADD231PD	%YMM22,%YMM28,%YMM18

(1399) 0x46fdfb VFMADD231PD	%YMM21,%YMM28,%YMM19

(1399) 0x46fe01 VBROADCASTSD	0x88(%RDI),%YMM21

(1399) 0x46fe08 VFMADD231PD	%YMM25,%YMM21,%YMM19

(1399) 0x46fe0e VFMADD231PD	%YMM23,%YMM21,%YMM18

(1399) 0x46fe14 VMOVDQA64	%YMM6,%YMM22

(1399) 0x46fe1a VFMADD231PD	%YMM20,%YMM21,%YMM17

(1399) 0x46fe20 VPTERNLOGQ	$-0x8,%YMM5,%YMM8,%YMM22

(1399) 0x46fe27 VADDPD	%YMM22,%YMM8,%YMM20

(1399) 0x46fe2d VMOVDQA64	%YMM6,%YMM22

(1399) 0x46fe33 VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM22

(1399) 0x46fe3a VADDPD	%YMM22,%YMM7,%YMM22

(1399) 0x46fe40 VRNDSCALEPD	$0xb,%YMM20,%YMM20

(1399) 0x46fe47 VRNDSCALEPD	$0xb,%YMM22,%YMM22

(1399) 0x46fe4e VMOVDQA64	%YMM6,%YMM23

(1399) 0x46fe54 VPTERNLOGQ	$-0x8,%YMM5,%YMM13,%YMM23

(1399) 0x46fe5b VADDPD	%YMM23,%YMM13,%YMM23

(1399) 0x46fe61 VMOVDQA64	%YMM6,%YMM24

(1399) 0x46fe67 VRNDSCALEPD	$0xb,%YMM23,%YMM23

(1399) 0x46fe6e VPTERNLOGQ	$-0x8,%YMM5,%YMM12,%YMM24

(1399) 0x46fe75 VADDPD	%YMM24,%YMM12,%YMM24

(1399) 0x46fe7b VRNDSCALEPD	$0xb,%YMM24,%YMM24

(1399) 0x46fe82 VMOVDQA64	%YMM6,%YMM25

(1399) 0x46fe88 VPTERNLOGQ	$-0x8,%YMM5,%YMM9,%YMM25

(1399) 0x46fe8f VADDPD	%YMM25,%YMM9,%YMM25

(1399) 0x46fe95 VRNDSCALEPD	$0xb,%YMM25,%YMM25

(1399) 0x46fe9c VMOVDQA64	%YMM6,%YMM26

(1399) 0x46fea2 VPTERNLOGQ	$-0x8,%YMM5,%YMM14,%YMM26

(1399) 0x46fea9 VADDPD	%YMM26,%YMM14,%YMM26

(1399) 0x46feaf VRNDSCALEPD	$0xb,%YMM26,%YMM26

(1399) 0x46feb6 VFMADD231PD	%YMM11,%YMM21,%YMM10

(1399) 0x46febc VMOVDQA	%YMM6,%YMM11

(1399) 0x46fec0 VPTERNLOGQ	$-0x8,%YMM5,%YMM16,%YMM11

(1399) 0x46fec7 VADDPD	%YMM11,%YMM16,%YMM11

(1399) 0x46fecd VRNDSCALEPD	$0xb,%YMM11,%YMM21

(1399) 0x46fed4 VSUBPD	%YMM24,%YMM12,%YMM12

(1399) 0x46feda VSUBPD	%YMM23,%YMM13,%YMM11

(1399) 0x46fee0 VMOVDQA	%YMM6,%YMM13

(1399) 0x46fee4 VPTERNLOGQ	$-0x8,%YMM5,%YMM15,%YMM13

(1399) 0x46feeb VADDPD	%YMM13,%YMM15,%YMM13

(1399) 0x46fef0 VROUNDPD	$0xb,%YMM13,%YMM13

(1399) 0x46fef6 VSUBPD	%YMM22,%YMM7,%YMM7

(1399) 0x46fefc VSUBPD	%YMM20,%YMM8,%YMM8

(1399) 0x46ff02 VMOVDQA64	%YMM6,%YMM20

(1399) 0x46ff08 VPTERNLOGQ	$-0x8,%YMM5,%YMM10,%YMM20

(1399) 0x46ff0f VADDPD	%YMM20,%YMM10,%YMM20

(1399) 0x46ff15 VRNDSCALEPD	$0xb,%YMM20,%YMM23

(1399) 0x46ff1c VSUBPD	%YMM13,%YMM15,%YMM13

(1399) 0x46ff21 VSUBPD	%YMM21,%YMM16,%YMM15

(1399) 0x46ff27 VMOVDQA64	%YMM6,%YMM16

(1399) 0x46ff2d VPTERNLOGQ	$-0x8,%YMM5,%YMM17,%YMM16

(1399) 0x46ff34 VADDPD	%YMM16,%YMM17,%YMM16

(1399) 0x46ff3a VRNDSCALEPD	$0xb,%YMM16,%YMM24

(1399) 0x46ff41 VMOVDQA64	%YMM6,%YMM16

(1399) 0x46ff47 VSUBPD	%YMM26,%YMM14,%YMM20

(1399) 0x46ff4d VPTERNLOGQ	$-0x8,%YMM5,%YMM18,%YMM16

(1399) 0x46ff54 VADDPD	%YMM16,%YMM18,%YMM14

(1399) 0x46ff5a VROUNDPD	$0xb,%YMM14,%YMM14

(1399) 0x46ff60 VMOVDQA64	%YMM6,%YMM16

(1399) 0x46ff66 VPTERNLOGQ	$-0x8,%YMM5,%YMM19,%YMM16

(1399) 0x46ff6d VSUBPD	%YMM25,%YMM9,%YMM21

(1399) 0x46ff73 VADDPD	%YMM16,%YMM19,%YMM9

(1399) 0x46ff79 VROUNDPD	$0xb,%YMM9,%YMM9

(1399) 0x46ff7f VSUBPD	%YMM9,%YMM19,%YMM22

(1399) 0x46ff85 VBROADCASTSD	(%RDI),%YMM25

(1399) 0x46ff8b VSUBPD	%YMM14,%YMM18,%YMM19

(1399) 0x46ff91 VMULPD	%YMM8,%YMM25,%YMM9

(1399) 0x46ff97 VMULPD	%YMM7,%YMM25,%YMM14

(1399) 0x46ff9d VMULPD	%YMM11,%YMM25,%YMM16

(1399) 0x46ffa3 VMULPD	%YMM12,%YMM25,%YMM18

(1399) 0x46ffa9 VBROADCASTSD	0x8(%RDI),%YMM25

(1399) 0x46ffb0 VSUBPD	%YMM24,%YMM17,%YMM17

(1399) 0x46ffb6 VFMADD231PD	%YMM21,%YMM25,%YMM18

(1399) 0x46ffbc VFMADD231PD	%YMM20,%YMM25,%YMM16

(1399) 0x46ffc2 VFMADD231PD	%YMM15,%YMM25,%YMM14

(1399) 0x46ffc8 VFMADD231PD	%YMM25,%YMM13,%YMM9

(1399) 0x46ffce VBROADCASTSD	0x10(%RDI),%YMM24

(1399) 0x46ffd5 VSUBPD	%YMM23,%YMM10,%YMM23

(1399) 0x46ffdb VFMADD231PD	%YMM24,%YMM23,%YMM9

(1399) 0x46ffe1 VFMADD231PD	%YMM24,%YMM17,%YMM14

(1399) 0x46ffe7 VFMADD231PD	%YMM24,%YMM19,%YMM16

(1399) 0x46ffed VFMADD231PD	%YMM24,%YMM22,%YMM18

(1399) 0x46fff3 VMOVUPD	%YMM18,0x60(%R8,%R15,8)

(1399) 0x46fffb VMOVUPD	%YMM16,0x40(%R8,%R15,8)

(1399) 0x470003 VMOVUPD	%YMM14,0x20(%R8,%R15,8)

(1399) 0x47000a VMOVUPD	%YMM9,(%R8,%R15,8)

(1399) 0x470010 VBROADCASTSD	0x18(%RDI),%YMM24

(1399) 0x470017 VMULPD	%YMM12,%YMM24,%YMM10

(1399) 0x47001d VMULPD	%YMM8,%YMM24,%YMM25

(1399) 0x470023 VMULPD	%YMM7,%YMM24,%YMM26

(1399) 0x470029 VBROADCASTSD	0x20(%RDI),%YMM27

(1399) 0x470030 VMULPD	%YMM11,%YMM24,%YMM24

(1399) 0x470036 VFMADD231PD	%YMM20,%YMM27,%YMM24

(1399) 0x47003c VFMADD231PD	%YMM15,%YMM27,%YMM26

(1399) 0x470042 VFMADD231PD	%YMM13,%YMM27,%YMM25

(1399) 0x470048 VFMADD231PD	%YMM27,%YMM21,%YMM10

(1399) 0x47004e VBROADCASTSD	0x28(%RDI),%YMM27

(1399) 0x470055 VFMADD231PD	%YMM22,%YMM27,%YMM10

(1399) 0x47005b VFMADD231PD	%YMM17,%YMM27,%YMM26

(1399) 0x470061 VFMADD231PD	%YMM27,%YMM19,%YMM24

(1399) 0x470067 VMOVUPD	%YMM24,0x40(%RBX,%R15,8)

(1399) 0x47006f VMOVUPD	%YMM26,0x20(%RBX,%R15,8)

(1399) 0x470077 VFMADD231PD	%YMM23,%YMM27,%YMM25

(1399) 0x47007d VMOVUPD	%YMM25,(%RBX,%R15,8)

(1399) 0x470084 VMOVUPD	%YMM10,0x60(%RBX,%R15,8)

(1399) 0x47008b VBROADCASTSD	0x30(%RDI),%YMM27

(1399) 0x470092 VMULPD	%YMM12,%YMM27,%YMM12

(1399) 0x470098 VMULPD	%YMM8,%YMM27,%YMM8

(1399) 0x47009e VMULPD	%YMM7,%YMM27,%YMM7

(1399) 0x4700a4 VMULPD	%YMM11,%YMM27,%YMM11

(1399) 0x4700aa VBROADCASTSD	0x38(%RDI),%YMM27

(1399) 0x4700b1 VFMADD231PD	%YMM20,%YMM27,%YMM11

(1399) 0x4700b7 VFMADD231PD	%YMM15,%YMM27,%YMM7

(1399) 0x4700bd VFMADD231PD	%YMM13,%YMM27,%YMM8

(1399) 0x4700c3 VFMADD231PD	%YMM21,%YMM27,%YMM12

(1399) 0x4700c9 VBROADCASTSD	0x40(%RDI),%YMM13

(1399) 0x4700cf VFMADD231PD	%YMM22,%YMM13,%YMM12

(1399) 0x4700d5 VFMADD231PD	%YMM23,%YMM13,%YMM8

(1399) 0x4700db VFMADD231PD	%YMM17,%YMM13,%YMM7

(1399) 0x4700e1 VFMADD231PD	%YMM19,%YMM13,%YMM11

(1399) 0x4700e7 VMULPD	%YMM16,%YMM16,%YMM13

(1399) 0x4700ed VMULPD	%YMM18,%YMM18,%YMM15

(1399) 0x4700f3 VMOVUPD	%YMM11,0x40(%R11,%R15,8)

(1399) 0x4700fa VMULPD	%YMM9,%YMM9,%YMM9

(1399) 0x4700ff VMULPD	%YMM14,%YMM14,%YMM14

(1399) 0x470104 VFMADD231PD	%YMM26,%YMM26,%YMM14

(1399) 0x47010a VFMADD231PD	%YMM25,%YMM25,%YMM9

(1399) 0x470110 VMOVUPD	%YMM7,0x20(%R11,%R15,8)

(1399) 0x470117 VFMADD231PD	%YMM10,%YMM10,%YMM15

(1399) 0x47011c VFMADD231PD	%YMM24,%YMM24,%YMM13

(1399) 0x470122 VFMADD231PD	%YMM11,%YMM11,%YMM13

(1399) 0x470127 VFMADD231PD	%YMM12,%YMM12,%YMM15

(1399) 0x47012c VMOVUPD	%YMM8,(%R11,%R15,8)

(1399) 0x470132 VFMADD231PD	%YMM8,%YMM8,%YMM9

(1399) 0x470137 VFMADD231PD	%YMM7,%YMM7,%YMM14

(1399) 0x47013c VSQRTPD	%YMM14,%YMM7

(1399) 0x470141 VSQRTPD	%YMM9,%YMM8

(1399) 0x470146 VMOVUPD	%YMM12,0x60(%R11,%R15,8)

(1399) 0x47014d VSQRTPD	%YMM15,%YMM9

(1399) 0x470152 VSQRTPD	%YMM13,%YMM10

(1399) 0x470157 VMOVUPD	%YMM10,0x40(%RCX,%R15,8)

(1399) 0x47015e VMOVUPD	%YMM9,0x60(%RCX,%R15,8)

(1399) 0x470165 VMOVUPD	%YMM8,(%RCX,%R15,8)

(1399) 0x47016b VMOVUPD	%YMM7,0x20(%RCX,%R15,8)

(1399) 0x470172 ADD	$0x10,%R12D

(1399) 0x470176 CMP	%R13D,%R12D

(1399) 0x470179 JBE	46fc70

0x47017f MOV	-0x38(%RBP),%R15

0x470183 CMP	%R14D,%R15D

0x470186 MOV	-0x2c(%RBP),%R13D

0x47018a JNE	4701a5

0x47018c CMP	%R15D,%R13D

0x47018f JNE	47030a

0x470195 JMP	470454

0x47019a XOR	%R14D,%R14D

0x47019d JMP	47030a

0x4701a2 XOR	%R14D,%R14D

0x4701a5 DEC	%R15D

0x4701a8 VPERMPD	$0x55,%YMM0,%YMM3

0x4701ae VBROADCASTSD	%XMM1,%YMM4

0x4701b3 VPBROADCASTQ	0x8ce8c(%RIP),%YMM5

0x4701bc VPBROADCASTQ	0x9348b(%RIP),%YMM6

0x4701c5 NOPW	%CS:(%RAX,%RAX,1)

(1398) 0x4701d0 LEA	(%R9,%R14,1),%R12D

(1398) 0x4701d4 MOVSXD	%R12D,%R12

(1398) 0x4701d7 VMOVUPD	(%RDX,%R12,8),%YMM7

(1398) 0x4701dd VSUBPD	%YMM2,%YMM7,%YMM7

(1398) 0x4701e1 VMOVUPD	(%R10,%R12,8),%YMM8

(1398) 0x4701e7 VSUBPD	%YMM3,%YMM8,%YMM8

(1398) 0x4701eb VMOVUPD	(%RSI,%R12,8),%YMM9

(1398) 0x4701f1 VSUBPD	%YMM4,%YMM9,%YMM9

(1398) 0x4701f5 VMULPD	0x48(%RDI){1to4},%YMM7,%YMM10

(1398) 0x4701fc VFMADD231PD	0x50(%RDI){1to4},%YMM8,%YMM10

(1398) 0x470203 VFMADD231PD	0x58(%RDI){1to4},%YMM9,%YMM10

(1398) 0x47020a VMULPD	0x60(%RDI){1to4},%YMM7,%YMM11

(1398) 0x470211 VFMADD231PD	0x68(%RDI){1to4},%YMM8,%YMM11

(1398) 0x470218 VFMADD231PD	0x70(%RDI){1to4},%YMM9,%YMM11

(1398) 0x47021f VMULPD	0x78(%RDI){1to4},%YMM7,%YMM7

(1398) 0x470226 VFMADD231PD	0x80(%RDI){1to4},%YMM8,%YMM7

(1398) 0x47022d VFMADD231PD	0x88(%RDI){1to4},%YMM9,%YMM7

(1398) 0x470234 VMOVDQA	%YMM6,%YMM8

(1398) 0x470238 VPTERNLOGQ	$-0x8,%YMM5,%YMM10,%YMM8

(1398) 0x47023f VADDPD	%YMM8,%YMM10,%YMM8

(1398) 0x470244 VROUNDPD	$0xb,%YMM8,%YMM8

(1398) 0x47024a VMOVDQA	%YMM6,%YMM9

(1398) 0x47024e VSUBPD	%YMM8,%YMM10,%YMM8

(1398) 0x470253 VPTERNLOGQ	$-0x8,%YMM5,%YMM11,%YMM9

(1398) 0x47025a VADDPD	%YMM9,%YMM11,%YMM9

(1398) 0x47025f VROUNDPD	$0xb,%YMM9,%YMM9

(1398) 0x470265 VMOVDQA	%YMM6,%YMM10

(1398) 0x470269 VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM10

(1398) 0x470270 VSUBPD	%YMM9,%YMM11,%YMM9

(1398) 0x470275 VADDPD	%YMM7,%YMM10,%YMM10

(1398) 0x470279 VROUNDPD	$0xb,%YMM10,%YMM10

(1398) 0x47027f VMULPD	(%RDI){1to4},%YMM8,%YMM11

(1398) 0x470285 VSUBPD	%YMM10,%YMM7,%YMM7

(1398) 0x47028a VFMADD231PD	0x8(%RDI){1to4},%YMM9,%YMM11

(1398) 0x470291 VFMADD231PD	0x10(%RDI){1to4},%YMM7,%YMM11

(1398) 0x470298 VMOVUPD	%YMM11,(%R8,%R12,8)

(1398) 0x47029e VMULPD	0x18(%RDI){1to4},%YMM8,%YMM10

(1398) 0x4702a5 VFMADD231PD	0x20(%RDI){1to4},%YMM9,%YMM10

(1398) 0x4702ac VFMADD231PD	0x28(%RDI){1to4},%YMM7,%YMM10

(1398) 0x4702b3 VMOVUPD	%YMM10,(%RBX,%R12,8)

(1398) 0x4702b9 VMULPD	0x30(%RDI){1to4},%YMM8,%YMM8

(1398) 0x4702c0 VFMADD231PD	0x38(%RDI){1to4},%YMM9,%YMM8

(1398) 0x4702c7 VFMADD231PD	0x40(%RDI){1to4},%YMM7,%YMM8

(1398) 0x4702ce VMULPD	%YMM11,%YMM11,%YMM7

(1398) 0x4702d3 VFMADD231PD	%YMM10,%YMM10,%YMM7

(1398) 0x4702d8 VMOVUPD	%YMM8,(%R11,%R12,8)

(1398) 0x4702de VFMADD231PD	%YMM8,%YMM8,%YMM7

(1398) 0x4702e3 VSQRTPD	%YMM7,%YMM7

(1398) 0x4702e7 VMOVUPD	%YMM7,(%RCX,%R12,8)

(1398) 0x4702ed ADD	$0x4,%R14D

(1398) 0x4702f1 CMP	%R15D,%R14D

(1398) 0x4702f4 JBE	4701d0

0x4702fa MOV	-0x38(%RBP),%R15

0x4702fe MOV	%R15D,%R14D

0x470301 CMP	%R15D,%R13D

0x470304 JE	470454

0x47030a ADD	%R9D,%R14D

0x47030d VMOVQ	0x9333b(%RIP),%XMM2

0x470315 VPBROADCASTQ	0x8dfda(%RIP),%XMM3

0x47031e VPBROADCASTQ	0x93329(%RIP),%XMM4

0x470327 VPBROADCASTQ	0x8cd18(%RIP),%XMM5

(1397) 0x470330 MOVSXD	%R14D,%R14

(1397) 0x470333 VMOVSD	(%RSI,%R14,8),%XMM6

(1397) 0x470339 VSUBSD	%XMM1,%XMM6,%XMM6

(1397) 0x47033d VMOVUPD	0x60(%RDI),%XMM7

(1397) 0x470342 VMOVUPD	0x70(%RDI),%XMM8

(1397) 0x470347 VMOVSD	(%RDX,%R14,8),%XMM9

(1397) 0x47034d VMOVHPD	(%R10,%R14,8),%XMM9,%XMM9

(1397) 0x470353 VSUBPD	%XMM0,%XMM9,%XMM9

(1397) 0x470357 VMULPD	0x48(%RDI),%XMM9,%XMM10

(1397) 0x47035c VSHUFPD	$0x1,%XMM10,%XMM10,%XMM11

(1397) 0x470362 VADDSD	%XMM10,%XMM11,%XMM10

(1397) 0x470367 VFMADD231SD	0x58(%RDI),%XMM6,%XMM10

(1397) 0x47036d VMOVSD	0x68(%RDI),%XMM11

(1397) 0x470372 VPUNPCKLQDQ	0x78(%RDI),%XMM11,%XMM11

(1397) 0x470377 VSHUFPD	$0x1,%XMM9,%XMM9,%XMM12

(1397) 0x47037d VMULPD	%XMM12,%XMM11,%XMM11

(1397) 0x470382 VMOVHPD	0x80(%RDI),%XMM7,%XMM7

(1397) 0x47038a VMOVHPD	0x88(%RDI),%XMM8,%XMM8

(1397) 0x470392 VFMADD213PD	%XMM11,%XMM9,%XMM7

(1397) 0x470397 VMOVDDUP	%XMM6,%XMM6

(1397) 0x47039b VMOVAPD	%XMM10,%XMM9

(1397) 0x4703a0 VPTERNLOGQ	$-0x28,%XMM3,%XMM2,%XMM9

(1397) 0x4703a7 VADDSD	%XMM9,%XMM10,%XMM9

(1397) 0x4703ac VROUNDSD	$0xb,%XMM9,%XMM9,%XMM9

(1397) 0x4703b2 VFMADD213PD	%XMM7,%XMM8,%XMM6

(1397) 0x4703b7 VSUBSD	%XMM9,%XMM10,%XMM7

(1397) 0x4703bc VMOVDQA	%XMM4,%XMM8

(1397) 0x4703c0 VPTERNLOGQ	$-0x8,%XMM5,%XMM6,%XMM8

(1397) 0x4703c7 VADDPD	%XMM6,%XMM8,%XMM8

(1397) 0x4703cb VROUNDPD	$0xb,%XMM8,%XMM8

(1397) 0x4703d1 VSUBPD	%XMM8,%XMM6,%XMM6

(1397) 0x4703d6 VMULSD	(%RDI),%XMM7,%XMM8

(1397) 0x4703da VFMADD231SD	0x8(%RDI),%XMM6,%XMM8

(1397) 0x4703e0 VSHUFPD	$0x1,%XMM6,%XMM6,%XMM9

(1397) 0x4703e5 VFMADD231SD	0x10(%RDI),%XMM9,%XMM8

(1397) 0x4703eb VMOVSD	%XMM8,(%R8,%R14,8)

(1397) 0x4703f1 VMULSD	0x18(%RDI),%XMM7,%XMM10

(1397) 0x4703f6 VFMADD231SD	0x20(%RDI),%XMM6,%XMM10

(1397) 0x4703fc VFMADD231SD	0x28(%RDI),%XMM9,%XMM10

(1397) 0x470402 VMOVSD	%XMM10,(%RBX,%R14,8)

(1397) 0x470408 VMOVUPD	0x38(%RDI),%XMM9

(1397) 0x47040d VMOVHPD	0x40(%RDI),%XMM9,%XMM9

(1397) 0x470412 VMULPD	%XMM6,%XMM9,%XMM6

(1397) 0x470416 VMOVAPD	%XMM6,%XMM9

(1397) 0x47041a VFMADD231SD	0x30(%RDI),%XMM7,%XMM9

(1397) 0x470420 VSHUFPD	$0x1,%XMM6,%XMM6,%XMM6

(1397) 0x470425 VADDSD	%XMM6,%XMM9,%XMM6

(1397) 0x470429 VMOVSD	%XMM6,(%R11,%R14,8)

(1397) 0x47042f VMULSD	%XMM8,%XMM8,%XMM7

(1397) 0x470434 VFMADD231SD	%XMM10,%XMM10,%XMM7

(1397) 0x470439 VFMADD231SD	%XMM6,%XMM6,%XMM7

(1397) 0x47043e VSQRTSD	%XMM7,%XMM7,%XMM6

(1397) 0x470442 VMOVSD	%XMM6,(%RCX,%R14,8)

(1397) 0x470448 INC	%R14D

(1397) 0x47044b CMP	%R14D,%EAX

(1397) 0x47044e JNE	470330

0x470454 POP	%RBX

0x470455 POP	%R12

0x470457 POP	%R13

0x470459 POP	%R14

0x47045b POP	%R15

0x47045d POP	%RBP

0x47045e VZEROUPPER

0x470461 RET

0x470462 NOPW	%CS:(%RAX,%RAX,1)

0x47046c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►40.15+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:283	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►37.15+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:275	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►10.68+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:366	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►9.05+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:185	exec
○	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	main.extracted.112	miniqmc.cpp:396	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►2.95+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:361	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271-273
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221-224,234-257

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 5.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:257

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 144 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	74
nb uops	75
loop length	323
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	6
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33
cycles	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Dispatch	8.33
Overall L1	12.50

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	13%
load	7%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	10%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	13%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

6% of peak load performance is reached (11.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.50 to 8.33 cycles (1.50x speedup).

ASM code

In the binary file, the address of the function is: 46fbd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 470454 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x884>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%R8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x4,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 47019a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x5ca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $-0x10,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4701a2 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x5d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x1(%R14),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPBROADCASTQ 0x8d3eb(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x939ea(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R14D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JNE 4701a5 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x5d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 47030a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x73a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 470454 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x884>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 47030a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x73a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DEC %R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ 0x8ce8c(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9348b(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 470454 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x884>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVQ 0x9333b(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ 0x8dfda(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x93329(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8cd18(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271-273
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221-224,234-257

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 5.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:257

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 144 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	74
nb uops	75
loop length	323
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	6
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33
cycles	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Dispatch	8.33
Overall L1	12.50

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	13%
load	7%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	10%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	13%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

6% of peak load performance is reached (11.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 46fbd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 470454 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x884>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%R8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x4,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 47019a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x5ca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $-0x10,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4701a2 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x5d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x1(%R14),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPBROADCASTQ 0x8d3eb(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x939ea(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R14D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JNE 4701a5 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x5d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 47030a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x73a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 470454 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x884>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 47030a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x73a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DEC %R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ 0x8ce8c(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9348b(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 470454 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x884>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVQ 0x9333b(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ 0x8dfda(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x93329(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8cd18(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	1.45	1.24
○Loop 1399 - ParticleBConds3DSoa.h:235-256 - exec	1.44	1.23
○Loop 1398 - ParticleBConds3DSoa.h:235-256 - exec	0.00	0.00
○Loop 1397 - ParticleBConds3DSoa.h:235-255 - exec	0.00	0.00

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512-bits vectorization

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