OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:172-189 [...]	Coverage (incl. loops): 20.54% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 172 - 189

--------------------------------------------------------------------------------

172:     ScopedTimer local_timer(timer);

173:

174:     auto u = Lattice.toUnit_floor(P.activeR(iat));

175:     for (int i = 0; i < nBlocks; ++i)

176:       MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock);

177:   }

178:

179:   inline void evaluate(const ParticleSet& P, int iat, ValueVector_t& psi_v)

180:   {

181:     evaluate_v(P, iat);

182:

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

188:     }

189:   }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 170 - 170

--------------------------------------------------------------------------------

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 235 - 924

--------------------------------------------------------------------------------

235:       if (__b < __a)

[...]

429: 	  const ptrdiff_t _Num = __last - __first;

430: 	  if (_Num)

431: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

[...]

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 61 - 61

--------------------------------------------------------------------------------

61:     for (size_t d = 0; d < D; ++d)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h: 725 - 751

--------------------------------------------------------------------------------

725:     { return std::copy(__first, __first + __n, __result); }

[...]

751:       if (__n2 <= 0)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 45 - 47

--------------------------------------------------------------------------------

45:   T sf = std::floor(x);

46:   T dx2 = x - sf;

47:   int ind2 = std::min(std::max(0, static_cast<int>(sf)), nmax);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57

--------------------------------------------------------------------------------

54:     a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03;

55:     a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13;

56:     a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23;

57:     a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 42 - 71

--------------------------------------------------------------------------------

42:   x -= spline_m->x_grid.start;

43:   y -= spline_m->y_grid.start;

44:   z -= spline_m->z_grid.start;

45:   T tx, ty, tz;

46:   int ix, iy, iz;

47:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

48:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

49:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

56:   const intptr_t xs = spline_m->x_stride;

57:   const intptr_t ys = spline_m->y_stride;

58:   const intptr_t zs = spline_m->z_stride;

59:

60:   constexpr T zero(0);

61:   std::fill(vals, vals + num_splines, zero);

62:

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

0x43f580 PUSH	%RBP

0x43f581 MOV	%RSP,%RBP

0x43f584 PUSH	%R15

0x43f586 PUSH	%R14

0x43f588 PUSH	%R13

0x43f58a PUSH	%R12

0x43f58c PUSH	%RBX

0x43f58d SUB	$0x168,%RSP

0x43f594 MOV	%RCX,-0x108(%RBP)

0x43f59b MOV	%EDX,%R12D

0x43f59e MOV	%RSI,%R13

0x43f5a1 MOV	%RDI,%RBX

0x43f5a4 MOV	0x358(%RDI),%RDI

0x43f5ab MOV	%RDI,-0x110(%RBP)

0x43f5b2 CALL	48dfa0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x43f5b7 MOVSXD	%R12D,%RCX

0x43f5ba LEA	(%RCX,%RCX,2),%RDX

0x43f5be SAL	$0x3,%RDX

0x43f5c2 ADD	0x40(%R13),%RDX

0x43f5c6 LEA	0x128(%R13),%RAX

0x43f5cd CMP	%ECX,0x124(%R13)

0x43f5d4 CMOVNE	%RDX,%RAX

0x43f5d8 MOV	%RBX,-0xa8(%RBP)

0x43f5df MOVSXD	0x30(%RBX),%RDX

0x43f5e3 TEST	%RDX,%RDX

0x43f5e6 JLE	440225

0x43f5ec VMOVSD	(%RAX),%XMM0

0x43f5f0 VMOVSD	0x8(%RAX),%XMM1

0x43f5f5 MOV	-0xa8(%RBP),%RCX

0x43f5fc VMULSD	0xd8(%RCX),%XMM0,%XMM2

0x43f604 VFMADD231SD	0xf0(%RCX),%XMM1,%XMM2

0x43f60d VMOVSD	0x10(%RAX),%XMM3

0x43f612 VFMADD231SD	0x108(%RCX),%XMM3,%XMM2

0x43f61b VMULSD	0xe0(%RCX),%XMM0,%XMM4

0x43f623 VFMADD231SD	0xf8(%RCX),%XMM1,%XMM4

0x43f62c VFMADD231SD	0x110(%RCX),%XMM3,%XMM4

0x43f635 VMULSD	0xe8(%RCX),%XMM0,%XMM0

0x43f63d VFMADD231SD	0x100(%RCX),%XMM1,%XMM0

0x43f646 VFMADD231SD	0x118(%RCX),%XMM3,%XMM0

0x43f64f VROUNDSD	$0x9,%XMM2,%XMM2,%XMM1

0x43f655 VSUBSD	%XMM1,%XMM2,%XMM6

0x43f659 VXORPD	%XMM1,%XMM1,%XMM1

0x43f65d VCMPSD	$0x1,%XMM1,%XMM2,%K1

0x43f664 VMOVAPD	%XMM6,%XMM3

0x43f668 VMOVSD	%XMM1,%XMM3,%XMM3{%K1}

0x43f66e VMOVSD	0xc08a2(%RIP),%XMM5

0x43f676 VCMPSD	$0x1,%XMM2,%XMM5,%K1

0x43f67d VROUNDSD	$0x9,%XMM4,%XMM4,%XMM2

0x43f683 VMOVSD	%XMM3,%XMM6,%XMM6{%K1}

0x43f689 VMOVUPD	%XMM6,-0x150(%RBP)

0x43f691 VSUBSD	%XMM2,%XMM4,%XMM3

0x43f695 VCMPSD	$0x1,%XMM1,%XMM4,%K1

0x43f69c VMOVAPD	%XMM3,%XMM2

0x43f6a0 VMOVSD	%XMM1,%XMM2,%XMM2{%K1}

0x43f6a6 VCMPSD	$0x1,%XMM4,%XMM5,%K1

0x43f6ad VMOVSD	%XMM2,%XMM3,%XMM3{%K1}

0x43f6b3 VMOVUPD	%XMM3,-0x140(%RBP)

0x43f6bb VROUNDSD	$0x9,%XMM0,%XMM0,%XMM2

0x43f6c1 VSUBSD	%XMM2,%XMM0,%XMM3

0x43f6c5 VCMPSD	$0x1,%XMM1,%XMM0,%K1

0x43f6cc VMOVAPD	%XMM3,%XMM2

0x43f6d0 VMOVSD	%XMM1,%XMM2,%XMM2{%K1}

0x43f6d6 VCMPSD	$0x1,%XMM0,%XMM5,%K1

0x43f6dd VMOVSD	%XMM2,%XMM3,%XMM3{%K1}

0x43f6e3 VMOVUPD	%XMM3,-0x130(%RBP)

0x43f6eb MOV	0x2f8(%RCX),%RAX

0x43f6f2 MOV	%RAX,-0xb8(%RBP)

0x43f6f9 MOV	0x310(%RCX),%RAX

0x43f700 MOV	%RAX,-0xb0(%RBP)

0x43f707 MOVSXD	0x40(%RCX),%RBX

0x43f70b LEA	(,%RBX,8),%RAX

0x43f713 MOV	%RAX,-0x118(%RBP)

0x43f71a TEST	%RAX,%RAX

0x43f71d MOV	%RBX,-0x78(%RBP)

0x43f721 JE	43fbf8

0x43f727 TEST	%EBX,%EBX

0x43f729 JE	4401f8

0x43f72f DEC	%RDX

0x43f732 MOV	%RBX,%RAX

0x43f735 SHR	$0x1,%RAX

0x43f738 MOV	%RAX,-0x58(%RBP)

0x43f73c AND	$-0x2,%RBX

0x43f740 XOR	%ECX,%ECX

0x43f742 VMOVDDUP	0xbd8d6(%RIP),%XMM0

0x43f74a VMOVUPD	%XMM0,-0x160(%RBP)

0x43f752 MOV	%RDX,-0x90(%RBP)

0x43f759 JMP	43f77e

0x43f75b NOPL	(%RAX,%RAX,1)

(917) 0x43f760 MOV	-0xa0(%RBP),%RCX

(917) 0x43f767 LEA	0x1(%RCX),%RAX

(917) 0x43f76b MOV	-0x90(%RBP),%RDX

(917) 0x43f772 CMP	%RDX,%RCX

(917) 0x43f775 MOV	%RAX,%RCX

(917) 0x43f778 JE	440225

(917) 0x43f77e MOV	-0xb8(%RBP),%RAX

(917) 0x43f785 MOV	(%RAX,%RCX,8),%R15

(917) 0x43f789 MOV	%RCX,-0xa0(%RBP)

(917) 0x43f790 LEA	(%RCX,%RCX,2),%RAX

(917) 0x43f794 VMOVUPD	-0x150(%RBP),%XMM0

(917) 0x43f79c VSUBSD	0x28(%R15),%XMM0,%XMM0

(917) 0x43f7a2 VMOVUPD	-0x140(%RBP),%XMM1

(917) 0x43f7aa VSUBSD	0x50(%R15),%XMM1,%XMM1

(917) 0x43f7b0 VMOVUPD	-0x130(%RBP),%XMM2

(917) 0x43f7b8 VSUBSD	0x78(%R15),%XMM2,%XMM2

(917) 0x43f7be VMULSD	0x48(%R15),%XMM0,%XMM0

(917) 0x43f7c4 MOV	-0xb0(%RBP),%RCX

(917) 0x43f7cb MOV	(%RCX,%RAX,8),%R13

(917) 0x43f7cf MOVSXD	0x38(%R15),%RAX

(917) 0x43f7d3 MOV	%RAX,-0x70(%RBP)

(917) 0x43f7d7 VROUNDSD	$0x9,%XMM0,%XMM0,%XMM3

(917) 0x43f7dd VCVTTSD2SI	%XMM3,%EAX

(917) 0x43f7e1 MOV	%EAX,-0x68(%RBP)

(917) 0x43f7e4 VSUBSD	%XMM3,%XMM0,%XMM0

(917) 0x43f7e8 VMULSD	0x70(%R15),%XMM1,%XMM1

(917) 0x43f7ee VMOVSD	0xc072a(%RIP),%XMM8

(917) 0x43f7f6 VMULSD	%XMM0,%XMM8,%XMM3

(917) 0x43f7fa VMOVSD	0xbd81e(%RIP),%XMM9

(917) 0x43f802 VSUBSD	%XMM3,%XMM9,%XMM4

(917) 0x43f806 VMULSD	%XMM0,%XMM0,%XMM5

(917) 0x43f80a VMOVDDUP	%XMM0,%XMM6

(917) 0x43f80e VMOVUPD	-0x160(%RBP),%XMM10

(917) 0x43f816 VBLENDPD	$0x1,%XMM4,%XMM10,%XMM4

(917) 0x43f81c VMULPD	%XMM4,%XMM6,%XMM4

(917) 0x43f820 VMOVUPD	0xc0748(%RIP),%XMM11

(917) 0x43f828 VADDPD	%XMM4,%XMM11,%XMM7

(917) 0x43f82c VPUNPCKLQDQ	%XMM5,%XMM6,%XMM6

(917) 0x43f830 VMOVUPD	0xc0748(%RIP),%XMM12

(917) 0x43f838 VFMADD213PD	%XMM12,%XMM7,%XMM6

(917) 0x43f83d VROUNDSD	$0x9,%XMM1,%XMM1,%XMM7

(917) 0x43f843 VCVTTSD2SI	%XMM7,%EAX

(917) 0x43f847 MOV	%EAX,-0x60(%RBP)

(917) 0x43f84a VMULSD	0x98(%R15),%XMM2,%XMM2

(917) 0x43f853 MOVSXD	0x60(%R15),%RAX

(917) 0x43f857 MOV	%RAX,-0x38(%RBP)

(917) 0x43f85b MOVSXD	0x88(%R15),%RAX

(917) 0x43f862 MOV	%RAX,-0x30(%RBP)

(917) 0x43f866 VMOVUPD	%XMM6,-0x100(%RBP)

(917) 0x43f86e VROUNDSD	$0x9,%XMM2,%XMM2,%XMM6

(917) 0x43f874 VCVTTSD2SI	%XMM6,%EAX

(917) 0x43f878 MOV	%EAX,-0x50(%RBP)

(917) 0x43f87b VSHUFPD	$0x1,%XMM4,%XMM4,%XMM4

(917) 0x43f880 VSUBSD	%XMM4,%XMM9,%XMM4

(917) 0x43f884 VFMADD213SD	%XMM9,%XMM0,%XMM4

(917) 0x43f889 VFMADD213SD	%XMM8,%XMM0,%XMM4

(917) 0x43f88e VMOVSD	%XMM4,-0xf0(%RBP)

(917) 0x43f896 VMULSD	%XMM5,%XMM3,%XMM0

(917) 0x43f89a VMOVSD	%XMM0,-0xe8(%RBP)

(917) 0x43f8a2 VSUBSD	%XMM7,%XMM1,%XMM0

(917) 0x43f8a6 VMULSD	%XMM0,%XMM8,%XMM1

(917) 0x43f8aa VSUBSD	%XMM1,%XMM9,%XMM3

(917) 0x43f8ae VMULSD	%XMM0,%XMM0,%XMM4

(917) 0x43f8b2 VMOVDDUP	%XMM0,%XMM5

(917) 0x43f8b6 VBLENDPD	$0x1,%XMM3,%XMM10,%XMM3

(917) 0x43f8bc VMULPD	%XMM3,%XMM5,%XMM3

(917) 0x43f8c0 VADDPD	%XMM3,%XMM11,%XMM7

(917) 0x43f8c4 VPUNPCKLQDQ	%XMM4,%XMM5,%XMM5

(917) 0x43f8c8 VFMADD213PD	%XMM12,%XMM7,%XMM5

(917) 0x43f8cd VMOVUPD	%XMM5,-0xe0(%RBP)

(917) 0x43f8d5 VSHUFPD	$0x1,%XMM3,%XMM3,%XMM3

(917) 0x43f8da VSUBSD	%XMM3,%XMM9,%XMM3

(917) 0x43f8de VFMADD213SD	%XMM9,%XMM0,%XMM3

(917) 0x43f8e3 VFMADD213SD	%XMM8,%XMM0,%XMM3

(917) 0x43f8e8 VMOVSD	%XMM3,-0xd0(%RBP)

(917) 0x43f8f0 VSUBSD	%XMM6,%XMM2,%XMM0

(917) 0x43f8f4 VMULSD	%XMM4,%XMM1,%XMM1

(917) 0x43f8f8 VMOVSD	%XMM1,-0xc8(%RBP)

(917) 0x43f900 VMULSD	%XMM0,%XMM8,%XMM1

(917) 0x43f904 VMOVSD	%XMM1,-0x48(%RBP)

(917) 0x43f909 VSUBSD	%XMM1,%XMM9,%XMM1

(917) 0x43f90d VFMADD213SD	0xbd722(%RIP),%XMM0,%XMM1

(917) 0x43f916 VFMADD213SD	%XMM8,%XMM0,%XMM1

(917) 0x43f91b VMOVUPD	%XMM1,-0x190(%RBP)

(917) 0x43f923 VMULSD	%XMM0,%XMM9,%XMM1

(917) 0x43f927 VADDSD	0xc05f9(%RIP),%XMM1,%XMM3

(917) 0x43f92f VMULSD	%XMM0,%XMM0,%XMM2

(917) 0x43f933 VMOVSD	%XMM2,-0x40(%RBP)

(917) 0x43f938 VFMADD213SD	0xc05ef(%RIP),%XMM2,%XMM3

(917) 0x43f941 VMOVUPD	%XMM3,-0x180(%RBP)

(917) 0x43f949 VSUBSD	%XMM1,%XMM9,%XMM1

(917) 0x43f94d VFMADD213SD	%XMM9,%XMM0,%XMM1

(917) 0x43f952 VFMADD213SD	%XMM8,%XMM0,%XMM1

(917) 0x43f957 VMOVUPD	%XMM1,-0x170(%RBP)

(917) 0x43f95f MOV	0x10(%R15),%R14

(917) 0x43f963 MOV	0x18(%R15),%RAX

(917) 0x43f967 MOV	%RAX,-0x98(%RBP)

(917) 0x43f96e MOV	0x20(%R15),%R12

(917) 0x43f972 MOV	%R13,%RDI

(917) 0x43f975 XOR	%ESI,%ESI

(917) 0x43f977 MOV	-0x118(%RBP),%RDX

(917) 0x43f97e CALL	4efda0 <_intel_fast_memset>

(917) 0x43f983 VMOVUPD	-0x170(%RBP),%XMM11

(917) 0x43f98b VMOVUPD	-0x180(%RBP),%XMM10

(917) 0x43f993 VMOVUPD	-0x190(%RBP),%XMM9

(917) 0x43f99b MOV	0x8(%R15),%RAX

(917) 0x43f99f VMOVSD	-0x40(%RBP),%XMM0

(917) 0x43f9a4 VMULSD	-0x48(%RBP),%XMM0,%XMM0

(917) 0x43f9a9 MOV	-0x30(%RBP),%R11

(917) 0x43f9ad DEC	%R11

(917) 0x43f9b0 MOV	-0x50(%RBP),%EDX

(917) 0x43f9b3 MOV	%EDX,%ECX

(917) 0x43f9b5 SAR	$0x1f,%ECX

(917) 0x43f9b8 ANDN	%EDX,%ECX,%ECX

(917) 0x43f9bd CMP	%RCX,%R11

(917) 0x43f9c0 CMOVGE	%RCX,%R11

(917) 0x43f9c4 MOV	%R12,%R8

(917) 0x43f9c7 IMUL	%R11,%R8

(917) 0x43f9cb MOV	-0x38(%RBP),%RDX

(917) 0x43f9cf DEC	%RDX

(917) 0x43f9d2 MOV	-0x60(%RBP),%ESI

(917) 0x43f9d5 MOV	%ESI,%ECX

(917) 0x43f9d7 SAR	$0x1f,%ECX

(917) 0x43f9da ANDN	%ESI,%ECX,%ECX

(917) 0x43f9df CMP	%RCX,%RDX

(917) 0x43f9e2 CMOVGE	%RCX,%RDX

(917) 0x43f9e6 MOV	-0x98(%RBP),%R10

(917) 0x43f9ed IMUL	%R10,%RDX

(917) 0x43f9f1 MOV	%RDX,%RDI

(917) 0x43f9f4 MOV	-0x70(%RBP),%RDX

(917) 0x43f9f8 DEC	%RDX

(917) 0x43f9fb MOV	-0x68(%RBP),%ESI

(917) 0x43f9fe MOV	%ESI,%ECX

(917) 0x43fa00 SAR	$0x1f,%ECX

(917) 0x43fa03 ANDN	%ESI,%ECX,%ECX

(917) 0x43fa08 CMP	%RCX,%RDX

(917) 0x43fa0b CMOVGE	%RCX,%RDX

(917) 0x43fa0f IMUL	%R14,%RDX

(917) 0x43fa13 ADD	%RDI,%RDX

(917) 0x43fa16 LEA	(%R12,%R12,2),%RDI

(917) 0x43fa1a VMOVDDUP	%XMM10,%XMM1

(917) 0x43fa1f VMOVDDUP	%XMM9,%XMM2

(917) 0x43fa24 VMOVDDUP	%XMM11,%XMM3

(917) 0x43fa29 VMOVDDUP	%XMM0,%XMM4

(917) 0x43fa2d LEA	(%RDX,%R8,1),%R9

(917) 0x43fa31 LEA	(%R9,%RBX,1),%RCX

(917) 0x43fa35 MOV	%RCX,-0x70(%RBP)

(917) 0x43fa39 LEA	(%R12,%R8,1),%RCX

(917) 0x43fa3d ADD	%RDX,%RCX

(917) 0x43fa40 ADD	%RBX,%RCX

(917) 0x43fa43 MOV	%RCX,-0x68(%RBP)

(917) 0x43fa47 LEA	(%R8,%R12,2),%RCX

(917) 0x43fa4b ADD	%RDX,%RCX

(917) 0x43fa4e ADD	%RBX,%RCX

(917) 0x43fa51 MOV	%RCX,-0x60(%RBP)

(917) 0x43fa55 ADD	%R8,%RDI

(917) 0x43fa58 ADD	%RDX,%RDI

(917) 0x43fa5b ADD	%RBX,%RDI

(917) 0x43fa5e LEA	0x3(%R11),%RCX

(917) 0x43fa62 IMUL	%R12,%RCX

(917) 0x43fa66 ADD	%RDX,%RCX

(917) 0x43fa69 LEA	(%RAX,%RCX,8),%RCX

(917) 0x43fa6d MOV	%R14,-0x88(%RBP)

(917) 0x43fa74 LEA	(,%R14,8),%RSI

(917) 0x43fa7c MOV	%RSI,-0x80(%RBP)

(917) 0x43fa80 MOV	%RCX,%R14

(917) 0x43fa83 LEA	0x2(%R11),%RCX

(917) 0x43fa87 IMUL	%R12,%RCX

(917) 0x43fa8b INC	%R11

(917) 0x43fa8e IMUL	%R12,%R11

(917) 0x43fa92 MOV	%R10,%RSI

(917) 0x43fa95 LEA	(,%R10,8),%R10

(917) 0x43fa9d ADD	%RDX,%RCX

(917) 0x43faa0 LEA	(%RAX,%RCX,8),%R15

(917) 0x43faa4 ADD	%RDX,%R11

(917) 0x43faa7 LEA	(%RAX,%R11,8),%R12

(917) 0x43faab LEA	(%RAX,%R9,8),%R8

(917) 0x43faaf XOR	%ECX,%ECX

(917) 0x43fab1 MOV	-0x78(%RBP),%RDX

(917) 0x43fab5 JMP	43faf5

0x43fab7 NOPW	(%RAX,%RAX,1)

  (918) 0x43fac0 MOV	-0x40(%RBP),%R11

  (918) 0x43fac4 LEA	0x1(%R11),%RCX

  (918) 0x43fac8 MOV	-0x38(%RBP),%R14

  (918) 0x43facc MOV	-0x80(%RBP),%R8

  (918) 0x43fad0 ADD	%R8,%R14

  (918) 0x43fad3 MOV	-0x30(%RBP),%R15

  (918) 0x43fad7 ADD	%R8,%R15

  (918) 0x43fada MOV	-0x50(%RBP),%R12

  (918) 0x43fade ADD	%R8,%R12

  (918) 0x43fae1 MOV	-0x48(%RBP),%R9

  (918) 0x43fae5 ADD	%R8,%R9

  (918) 0x43fae8 MOV	%R9,%R8

  (918) 0x43faeb CMP	$0x3,%R11

  (918) 0x43faef JE	43f760

  (918) 0x43faf5 VMOVSD	-0x100(%RBP,%RCX,8),%XMM5

  (918) 0x43fafe MOV	-0x88(%RBP),%R11

  (918) 0x43fb05 MOV	%RCX,-0x40(%RBP)

  (918) 0x43fb09 IMUL	%RCX,%R11

  (918) 0x43fb0d MOV	%R8,-0x48(%RBP)

  (918) 0x43fb11 MOV	%R12,-0x50(%RBP)

  (918) 0x43fb15 MOV	%R12,%R9

  (918) 0x43fb18 MOV	%R15,-0x30(%RBP)

  (918) 0x43fb1c MOV	%R14,-0x38(%RBP)

  (918) 0x43fb20 XOR	%R12D,%R12D

  (918) 0x43fb23 JMP	43fb4e

0x43fb25 NOPW	%CS:(%RAX,%RAX,1)

    (919) 0x43fb30 LEA	0x1(%R12),%RCX

    (919) 0x43fb35 ADD	%R10,%R14

    (919) 0x43fb38 ADD	%R10,%R15

    (919) 0x43fb3b ADD	%R10,%R9

    (919) 0x43fb3e ADD	%R10,%R8

    (919) 0x43fb41 CMP	$0x3,%R12

    (919) 0x43fb45 MOV	%RCX,%R12

    (919) 0x43fb48 JE	43fac0

    (919) 0x43fb4e VMULSD	-0xe0(%RBP,%R12,8),%XMM5,%XMM6

    (919) 0x43fb58 CMP	$0x1,%EDX

    (919) 0x43fb5b JE	43fb9f

    (919) 0x43fb5d VMOVDDUP	%XMM6,%XMM7

    (919) 0x43fb61 MOV	-0x58(%RBP),%RCX

    (919) 0x43fb65 XOR	%EDX,%EDX

    (919) 0x43fb67 NOPW	(%RAX,%RAX,1)

      (920) 0x43fb70 VMULPD	(%R8,%RDX,1),%XMM2,%XMM8

      (920) 0x43fb76 VFMADD231PD	(%R9,%RDX,1),%XMM1,%XMM8

      (920) 0x43fb7c VFMADD231PD	(%R15,%RDX,1),%XMM3,%XMM8

      (920) 0x43fb82 VFMADD231PD	(%R14,%RDX,1),%XMM4,%XMM8

      (920) 0x43fb88 VFMADD213PD	(%R13,%RDX,1),%XMM7,%XMM8

      (920) 0x43fb8f VMOVUPD	%XMM8,(%R13,%RDX,1)

      (920) 0x43fb96 ADD	$0x10,%RDX

      (920) 0x43fb9a DEC	%RCX

      (920) 0x43fb9d JNE	43fb70

    (919) 0x43fb9f MOV	-0x78(%RBP),%RDX

    (919) 0x43fba3 CMP	%RDX,%RBX

    (919) 0x43fba6 JE	43fb30

    (919) 0x43fba8 MOV	%RSI,%RCX

    (919) 0x43fbab IMUL	%R12,%RCX

    (919) 0x43fbaf ADD	%R11,%RCX

    (919) 0x43fbb2 MOV	-0x70(%RBP),%RDX

    (919) 0x43fbb6 ADD	%RCX,%RDX

    (919) 0x43fbb9 VMULSD	(%RAX,%RDX,8),%XMM9,%XMM7

    (919) 0x43fbbe MOV	-0x68(%RBP),%RDX

    (919) 0x43fbc2 ADD	%RCX,%RDX

    (919) 0x43fbc5 VFMADD231SD	(%RAX,%RDX,8),%XMM10,%XMM7

    (919) 0x43fbcb MOV	-0x60(%RBP),%RDX

    (919) 0x43fbcf ADD	%RCX,%RDX

    (919) 0x43fbd2 VFMADD231SD	(%RAX,%RDX,8),%XMM11,%XMM7

    (919) 0x43fbd8 MOV	-0x78(%RBP),%RDX

    (919) 0x43fbdc ADD	%RDI,%RCX

    (919) 0x43fbdf VFMADD231SD	(%RAX,%RCX,8),%XMM0,%XMM7

    (919) 0x43fbe5 VFMADD213SD	(%R13,%RBX,8),%XMM6,%XMM7

    (919) 0x43fbec VMOVSD	%XMM7,(%R13,%RBX,8)

    (919) 0x43fbf3 JMP	43fb30

0x43fbf8 TEST	%EBX,%EBX

0x43fbfa JE	440225

0x43fc00 DEC	%RDX

0x43fc03 MOV	-0x78(%RBP),%RAX

0x43fc07 SHR	$0x1,%RAX

0x43fc0a MOV	%RAX,-0x40(%RBP)

0x43fc0e XOR	%ECX,%ECX

0x43fc10 VMOVSD	0xc0308(%RIP),%XMM0

0x43fc18 VMOVSD	0xbd400(%RIP),%XMM1

0x43fc20 VMOVDDUP	0xbd3f8(%RIP),%XMM2

0x43fc28 VMOVUPD	0xc0340(%RIP),%XMM3

0x43fc30 VMOVUPD	0xc0348(%RIP),%XMM4

0x43fc38 VMOVSD	0xbd3f8(%RIP),%XMM5

0x43fc40 VMOVSD	0xc02e0(%RIP),%XMM6

0x43fc48 VMOVSD	0xc02e0(%RIP),%XMM7

0x43fc50 MOV	%RDX,-0x90(%RBP)

0x43fc57 JMP	43fc7e

0x43fc59 NOPL	(%RAX)

(909) 0x43fc60 MOV	-0xa0(%RBP),%RCX

(909) 0x43fc67 LEA	0x1(%RCX),%RAX

(909) 0x43fc6b MOV	-0x90(%RBP),%RDX

(909) 0x43fc72 CMP	%RDX,%RCX

(909) 0x43fc75 MOV	%RAX,%RCX

(909) 0x43fc78 JE	440225

(909) 0x43fc7e MOV	-0xb8(%RBP),%RAX

(909) 0x43fc85 MOV	(%RAX,%RCX,8),%RSI

(909) 0x43fc89 MOV	%RCX,-0xa0(%RBP)

(909) 0x43fc90 LEA	(%RCX,%RCX,2),%RCX

(909) 0x43fc94 VMOVUPD	-0x150(%RBP),%XMM8

(909) 0x43fc9c VSUBSD	0x28(%RSI),%XMM8,%XMM8

(909) 0x43fca1 VMOVUPD	-0x140(%RBP),%XMM9

(909) 0x43fca9 VSUBSD	0x50(%RSI),%XMM9,%XMM9

(909) 0x43fcae MOV	-0xb0(%RBP),%RAX

(909) 0x43fcb5 MOV	(%RAX,%RCX,8),%RDX

(909) 0x43fcb9 VMOVUPD	-0x130(%RBP),%XMM10

(909) 0x43fcc1 VSUBSD	0x78(%RSI),%XMM10,%XMM10

(909) 0x43fcc6 VMULSD	0x48(%RSI),%XMM8,%XMM8

(909) 0x43fccb MOVSXD	0x38(%RSI),%RAX

(909) 0x43fccf VROUNDSD	$0x9,%XMM8,%XMM8,%XMM11

(909) 0x43fcd5 VCVTTSD2SI	%XMM11,%R8D

(909) 0x43fcda VMULSD	0x70(%RSI),%XMM9,%XMM9

(909) 0x43fcdf VSUBSD	%XMM11,%XMM8,%XMM8

(909) 0x43fce4 VMULSD	%XMM0,%XMM8,%XMM12

(909) 0x43fce8 VSUBSD	%XMM12,%XMM1,%XMM11

(909) 0x43fced VMULSD	%XMM8,%XMM8,%XMM13

(909) 0x43fcf2 VMOVDDUP	%XMM8,%XMM14

(909) 0x43fcf7 VBLENDPD	$0x1,%XMM11,%XMM2,%XMM11

(909) 0x43fcfd VMULPD	%XMM11,%XMM14,%XMM15

(909) 0x43fd02 VADDPD	%XMM3,%XMM15,%XMM11

(909) 0x43fd06 VPUNPCKLQDQ	%XMM13,%XMM14,%XMM14

(909) 0x43fd0b VFMADD213PD	%XMM4,%XMM11,%XMM14

(909) 0x43fd10 VRNDSCALESD	$0x9,%XMM9,%XMM9,%XMM16

(909) 0x43fd17 MOVSXD	0x60(%RSI),%R14

(909) 0x43fd1b VCVTTSD2SI	%XMM16,%R10D

(909) 0x43fd21 VMULSD	0x98(%RSI),%XMM10,%XMM10

(909) 0x43fd29 MOVSXD	0x88(%RSI),%R15

(909) 0x43fd30 VMOVUPD	%XMM14,-0x100(%RBP)

(909) 0x43fd38 VROUNDSD	$0x9,%XMM10,%XMM10,%XMM11

(909) 0x43fd3e VCVTTSD2SI	%XMM11,%EDI

(909) 0x43fd43 VSHUFPD	$0x1,%XMM15,%XMM15,%XMM14

(909) 0x43fd49 VSUBSD	%XMM14,%XMM1,%XMM14

(909) 0x43fd4e VFMADD213SD	%XMM1,%XMM8,%XMM14

(909) 0x43fd53 VFMADD213SD	%XMM0,%XMM8,%XMM14

(909) 0x43fd58 VMOVSD	%XMM14,-0xf0(%RBP)

(909) 0x43fd60 VSUBSD	%XMM16,%XMM9,%XMM9

(909) 0x43fd66 VMULSD	%XMM13,%XMM12,%XMM8

(909) 0x43fd6b VMOVSD	%XMM8,-0xe8(%RBP)

(909) 0x43fd73 VMULSD	%XMM0,%XMM9,%XMM12

(909) 0x43fd77 VSUBSD	%XMM12,%XMM1,%XMM8

(909) 0x43fd7c VMULSD	%XMM9,%XMM9,%XMM13

(909) 0x43fd81 VMOVDDUP	%XMM9,%XMM14

(909) 0x43fd86 VBLENDPD	$0x1,%XMM8,%XMM2,%XMM8

(909) 0x43fd8c VMULPD	%XMM8,%XMM14,%XMM8

(909) 0x43fd91 VADDPD	%XMM3,%XMM8,%XMM15

(909) 0x43fd95 VPUNPCKLQDQ	%XMM13,%XMM14,%XMM14

(909) 0x43fd9a VFMADD213PD	%XMM4,%XMM15,%XMM14

(909) 0x43fd9f VMOVUPD	%XMM14,-0xe0(%RBP)

(909) 0x43fda7 VSHUFPD	$0x1,%XMM8,%XMM8,%XMM8

(909) 0x43fdad VSUBSD	%XMM8,%XMM1,%XMM8

(909) 0x43fdb2 VFMADD213SD	%XMM1,%XMM9,%XMM8

(909) 0x43fdb7 VFMADD213SD	%XMM0,%XMM9,%XMM8

(909) 0x43fdbc VMOVSD	%XMM8,-0xd0(%RBP)

(909) 0x43fdc4 VMULSD	%XMM13,%XMM12,%XMM9

(909) 0x43fdc9 VMOVSD	%XMM9,-0xc8(%RBP)

(909) 0x43fdd1 MOV	%RSI,%R11

(909) 0x43fdd4 MOV	%RSI,-0x70(%RBP)

(909) 0x43fdd8 MOV	0x10(%RSI),%RSI

(909) 0x43fddc MOV	0x18(%R11),%R9

(909) 0x43fde0 MOV	0x20(%R11),%R11

(909) 0x43fde4 DEC	%R15

(909) 0x43fde7 MOV	%EDI,%EBX

(909) 0x43fde9 SAR	$0x1f,%EBX

(909) 0x43fdec ANDN	%EDI,%EBX,%EDI

(909) 0x43fdf1 CMP	%RDI,%R15

(909) 0x43fdf4 CMOVGE	%RDI,%R15

(909) 0x43fdf8 MOV	%R11,%RDI

(909) 0x43fdfb IMUL	%R15,%RDI

(909) 0x43fdff MOV	%RDI,%R13

(909) 0x43fe02 DEC	%R14

(909) 0x43fe05 MOV	%R10D,%EBX

(909) 0x43fe08 SAR	$0x1f,%EBX

(909) 0x43fe0b ANDN	%R10D,%EBX,%R10D

(909) 0x43fe10 CMP	%R10,%R14

(909) 0x43fe13 CMOVGE	%R10,%R14

(909) 0x43fe17 MOV	%R9,%RCX

(909) 0x43fe1a IMUL	%R14,%RCX

(909) 0x43fe1e DEC	%RAX

(909) 0x43fe21 MOV	%R8D,%EBX

(909) 0x43fe24 SAR	$0x1f,%EBX

(909) 0x43fe27 ANDN	%R8D,%EBX,%R8D

(909) 0x43fe2c CMP	%R8,%RAX

(909) 0x43fe2f CMOVGE	%R8,%RAX

(909) 0x43fe33 IMUL	%RSI,%RAX

(909) 0x43fe37 MOV	%RAX,%RDI

(909) 0x43fe3a LEA	0x2(%R15),%RAX

(909) 0x43fe3e IMUL	%R11,%RAX

(909) 0x43fe42 LEA	0x3(%R15),%R8

(909) 0x43fe46 IMUL	%R11,%R8

(909) 0x43fe4a INC	%R15

(909) 0x43fe4d IMUL	%R11,%R15

(909) 0x43fe51 LEA	0x1(%R14),%R10

(909) 0x43fe55 IMUL	%R9,%R10

(909) 0x43fe59 MOV	%R10,%R12

(909) 0x43fe5c MOV	%R10,-0x48(%RBP)

(909) 0x43fe60 LEA	0x2(%R14),%RBX

(909) 0x43fe64 IMUL	%R9,%RBX

(909) 0x43fe68 ADD	$0x3,%R14

(909) 0x43fe6c IMUL	%R9,%R14

(909) 0x43fe70 MOV	%R14,%R10

(909) 0x43fe73 MOV	%R14,-0x58(%RBP)

(909) 0x43fe77 MOV	%RDI,%R11

(909) 0x43fe7a MOV	%RCX,%RDI

(909) 0x43fe7d LEA	(%RCX,%R11,1),%R9

(909) 0x43fe81 LEA	(%R9,%R8,1),%RCX

(909) 0x43fe85 MOV	%RCX,-0x60(%RBP)

(909) 0x43fe89 LEA	(%R9,%RAX,1),%RCX

(909) 0x43fe8d MOV	%RCX,-0x38(%RBP)

(909) 0x43fe91 ADD	%R15,%R9

(909) 0x43fe94 MOV	%R13,%RCX

(909) 0x43fe97 ADD	%R11,%RCX

(909) 0x43fe9a LEA	(%R11,%R12,1),%R14

(909) 0x43fe9e LEA	(%R14,%RAX,1),%R12

(909) 0x43fea2 MOV	%R12,-0x30(%RBP)

(909) 0x43fea6 ADD	%R15,%R14

(909) 0x43fea9 LEA	(%R11,%RBX,1),%R13

(909) 0x43fead LEA	(%R13,%RAX,1),%R12

(909) 0x43feb2 MOV	%R12,-0x68(%RBP)

(909) 0x43feb6 ADD	%R15,%R13

(909) 0x43feb9 LEA	(%R11,%R8,1),%R12

(909) 0x43febd ADD	%R10,%R11

(909) 0x43fec0 ADD	%R11,%R8

(909) 0x43fec3 MOV	%R8,-0x50(%RBP)

(909) 0x43fec7 ADD	%R11,%RAX

(909) 0x43feca MOV	%RAX,-0x88(%RBP)

(909) 0x43fed1 ADD	%R15,%R11

(909) 0x43fed4 MOV	%R11,-0x80(%RBP)

(909) 0x43fed8 ADD	%RCX,%RDI

(909) 0x43fedb MOV	%RDI,%R11

(909) 0x43fede MOV	-0x48(%RBP),%R10

(909) 0x43fee2 LEA	(%R12,%R10,1),%RAX

(909) 0x43fee6 ADD	%RCX,%R10

(909) 0x43fee9 MOV	%R10,%R15

(909) 0x43feec ADD	%RBX,%R12

(909) 0x43feef ADD	%RCX,%RBX

(909) 0x43fef2 MOV	%RBX,-0x98(%RBP)

(909) 0x43fef9 MOV	-0x58(%RBP),%RDI

(909) 0x43fefd ADD	%RCX,%RDI

(909) 0x43ff00 MOV	%RDI,-0x58(%RBP)

(909) 0x43ff04 MOV	-0x70(%RBP),%RCX

(909) 0x43ff08 MOV	0x8(%RCX),%RCX

(909) 0x43ff0c MOV	-0x60(%RBP),%RDI

(909) 0x43ff10 LEA	(%RCX,%RDI,8),%RDI

(909) 0x43ff14 MOV	-0x38(%RBP),%R8

(909) 0x43ff18 LEA	(%RCX,%R8,8),%R8

(909) 0x43ff1c LEA	(%RCX,%R9,8),%R9

(909) 0x43ff20 LEA	(%RCX,%R11,8),%R10

(909) 0x43ff24 LEA	(%RCX,%RAX,8),%R11

(909) 0x43ff28 MOV	-0x30(%RBP),%RAX

(909) 0x43ff2c LEA	(%RCX,%RAX,8),%RBX

(909) 0x43ff30 LEA	(%RCX,%R14,8),%R14

(909) 0x43ff34 LEA	(%RCX,%R15,8),%R15

(909) 0x43ff38 LEA	(%RCX,%R12,8),%RAX

(909) 0x43ff3c MOV	%RAX,-0x48(%RBP)

(909) 0x43ff40 MOV	-0x68(%RBP),%RAX

(909) 0x43ff44 LEA	(%RCX,%RAX,8),%RAX

(909) 0x43ff48 MOV	%RAX,-0x30(%RBP)

(909) 0x43ff4c LEA	(%RCX,%R13,8),%R13

(909) 0x43ff50 MOV	-0x98(%RBP),%RAX

(909) 0x43ff57 LEA	(%RCX,%RAX,8),%R12

(909) 0x43ff5b MOV	-0x50(%RBP),%RAX

(909) 0x43ff5f LEA	(%RCX,%RAX,8),%RAX

(909) 0x43ff63 MOV	%RAX,-0x70(%RBP)

(909) 0x43ff67 MOV	-0x88(%RBP),%RAX

(909) 0x43ff6e LEA	(%RCX,%RAX,8),%RAX

(909) 0x43ff72 MOV	%RAX,-0x68(%RBP)

(909) 0x43ff76 MOV	-0x80(%RBP),%RAX

(909) 0x43ff7a LEA	(%RCX,%RAX,8),%RAX

(909) 0x43ff7e MOV	%RAX,-0x60(%RBP)

(909) 0x43ff82 MOV	-0x58(%RBP),%RAX

(909) 0x43ff86 LEA	(%RCX,%RAX,8),%RAX

(909) 0x43ff8a MOV	%RAX,-0x58(%RBP)

(909) 0x43ff8e VSUBSD	%XMM11,%XMM10,%XMM10

(909) 0x43ff93 VMULSD	%XMM0,%XMM10,%XMM11

(909) 0x43ff97 VSUBSD	%XMM11,%XMM1,%XMM13

(909) 0x43ff9c VFMADD213SD	%XMM5,%XMM10,%XMM13

(909) 0x43ffa1 VFMADD213SD	%XMM0,%XMM10,%XMM13

(909) 0x43ffa6 VMULSD	%XMM1,%XMM10,%XMM12

(909) 0x43ffaa VADDSD	%XMM6,%XMM12,%XMM14

(909) 0x43ffae VMULSD	%XMM10,%XMM10,%XMM15

(909) 0x43ffb3 VFMADD213SD	%XMM7,%XMM15,%XMM14

(909) 0x43ffb8 VSUBSD	%XMM12,%XMM1,%XMM16

(909) 0x43ffbe VFMADD213SD	%XMM1,%XMM10,%XMM16

(909) 0x43ffc4 VFMADD213SD	%XMM0,%XMM10,%XMM16

(909) 0x43ffca VMULSD	%XMM15,%XMM11,%XMM15

(909) 0x43ffcf VMOVSD	-0xe0(%RBP),%XMM10

(909) 0x43ffd7 VMOVSD	-0xd8(%RBP),%XMM11

(909) 0x43ffdf VMOVDDUP	%XMM14,%XMM12

(909) 0x43ffe4 VMOVDDUP	%XMM13,%XMM13

(909) 0x43ffe9 VMOVDDUP	%XMM16,%XMM14

(909) 0x43ffef VMOVDDUP	%XMM15,%XMM15

(909) 0x43fff4 SAL	$0x3,%RSI

(909) 0x43fff8 MOVQ	$0,-0x38(%RBP)

(909) 0x440000 MOV	%RSI,-0x80(%RBP)

(909) 0x440004 JMP	440067

0x440006 NOPW	%CS:(%RAX,%RAX,1)

  (910) 0x440010 ADD	%RSI,%RDI

  (910) 0x440013 ADD	%RSI,%R8

  (910) 0x440016 ADD	%RSI,%R9

  (910) 0x440019 ADD	%RSI,%R10

  (910) 0x44001c ADD	%RSI,%R11

  (910) 0x44001f ADD	%RSI,%RBX

  (910) 0x440022 ADD	%RSI,%R14

  (910) 0x440025 ADD	%RSI,%R15

  (910) 0x440028 ADD	%RSI,-0x48(%RBP)

  (910) 0x44002c MOV	-0x30(%RBP),%RAX

  (910) 0x440030 ADD	%RSI,%RAX

  (910) 0x440033 MOV	%RAX,-0x30(%RBP)

  (910) 0x440037 ADD	%RSI,%R13

  (910) 0x44003a MOV	-0x50(%RBP),%R12

  (910) 0x44003e ADD	%RSI,%R12

  (910) 0x440041 ADD	%RSI,-0x70(%RBP)

  (910) 0x440045 ADD	%RSI,-0x68(%RBP)

  (910) 0x440049 ADD	%RSI,-0x60(%RBP)

  (910) 0x44004d ADD	%RSI,-0x58(%RBP)

  (910) 0x440051 MOV	-0x38(%RBP),%RAX

  (910) 0x440055 CMP	$0x3,%RAX

  (910) 0x440059 LEA	0x1(%RAX),%RCX

  (910) 0x44005d MOV	%RCX,-0x38(%RBP)

  (910) 0x440061 JE	43fc60

  (910) 0x440067 MOV	%R12,-0x50(%RBP)

  (910) 0x44006b CMPL	$0x1,-0x78(%RBP)

  (910) 0x44006f JE	440010

  (910) 0x440071 MOV	-0x38(%RBP),%RAX

  (910) 0x440075 VMOVSD	-0x100(%RBP,%RAX,8),%XMM16

  (910) 0x44007d VMULSD	%XMM16,%XMM10,%XMM17

  (910) 0x440083 VMOVDDUP	%XMM17,%XMM17

  (910) 0x440089 MOV	-0x40(%RBP),%R12

  (910) 0x44008d XOR	%ECX,%ECX

  (910) 0x44008f NOP

    (911) 0x440090 VMULPD	(%R10,%RCX,1),%XMM13,%XMM18

    (911) 0x440097 VFMADD231PD	(%R9,%RCX,1),%XMM12,%XMM18

    (911) 0x44009e VFMADD231PD	(%R8,%RCX,1),%XMM14,%XMM18

    (911) 0x4400a5 VFMADD231PD	(%RDI,%RCX,1),%XMM15,%XMM18

    (911) 0x4400ac VFMADD213PD	(%RDX,%RCX,1),%XMM17,%XMM18

    (911) 0x4400b3 VMOVUPD	%XMM18,(%RDX,%RCX,1)

    (911) 0x4400ba ADD	$0x10,%RCX

    (911) 0x4400be DEC	%R12

    (911) 0x4400c1 JNE	440090

  (910) 0x4400c3 CMPL	$0x1,-0x78(%RBP)

  (910) 0x4400c7 JE	440010

  (910) 0x4400cd VMULSD	%XMM16,%XMM11,%XMM17

  (910) 0x4400d3 VMOVDDUP	%XMM17,%XMM17

  (910) 0x4400d9 XOR	%R12D,%R12D

  (910) 0x4400dc MOV	-0x40(%RBP),%RCX

    (912) 0x4400e0 VMULPD	(%R15,%R12,1),%XMM13,%XMM18

    (912) 0x4400e7 VFMADD231PD	(%R14,%R12,1),%XMM12,%XMM18

    (912) 0x4400ee VFMADD231PD	(%RBX,%R12,1),%XMM14,%XMM18

    (912) 0x4400f5 VFMADD231PD	(%R11,%R12,1),%XMM15,%XMM18

    (912) 0x4400fc VFMADD213PD	(%RDX,%R12,1),%XMM17,%XMM18

    (912) 0x440103 VMOVUPD	%XMM18,(%RDX,%R12,1)

    (912) 0x44010a ADD	$0x10,%R12

    (912) 0x44010e DEC	%RCX

    (912) 0x440111 JNE	4400e0

  (910) 0x440113 CMPL	$0x1,-0x78(%RBP)

  (910) 0x440117 JE	440010

  (910) 0x44011d MOV	%R11,-0x88(%RBP)

  (910) 0x440124 VMULSD	%XMM16,%XMM8,%XMM17

  (910) 0x44012a VMOVDDUP	%XMM17,%XMM17

  (910) 0x440130 XOR	%R12D,%R12D

  (910) 0x440133 MOV	-0x40(%RBP),%RCX

  (910) 0x440137 MOV	%R13,%RSI

  (910) 0x44013a MOV	-0x30(%RBP),%R13

  (910) 0x44013e MOV	-0x48(%RBP),%RAX

  (910) 0x440142 MOV	-0x50(%RBP),%R11

  (910) 0x440146 NOPW	%CS:(%RAX,%RAX,1)

    (913) 0x440150 VMULPD	(%R11,%R12,1),%XMM13,%XMM18

    (913) 0x440157 VFMADD231PD	(%RSI,%R12,1),%XMM12,%XMM18

    (913) 0x44015e VFMADD231PD	(%R13,%R12,1),%XMM14,%XMM18

    (913) 0x440166 VFMADD231PD	(%RAX,%R12,1),%XMM15,%XMM18

    (913) 0x44016d VFMADD213PD	(%RDX,%R12,1),%XMM17,%XMM18

    (913) 0x440174 VMOVUPD	%XMM18,(%RDX,%R12,1)

    (913) 0x44017b ADD	$0x10,%R12

    (913) 0x44017f DEC	%RCX

    (913) 0x440182 JNE	440150

  (910) 0x440184 CMPL	$0x1,-0x78(%RBP)

  (910) 0x440188 MOV	%RSI,%R13

  (910) 0x44018b MOV	-0x80(%RBP),%RSI

  (910) 0x44018f MOV	-0x88(%RBP),%R11

  (910) 0x440196 JE	440010

  (910) 0x44019c VMULSD	%XMM16,%XMM9,%XMM16

  (910) 0x4401a2 VMOVDDUP	%XMM16,%XMM16

  (910) 0x4401a8 XOR	%R12D,%R12D

  (910) 0x4401ab MOV	-0x40(%RBP),%RCX

  (910) 0x4401af NOP

    (914) 0x4401b0 MOV	-0x58(%RBP),%RAX

    (914) 0x4401b4 VMULPD	(%RAX,%R12,1),%XMM13,%XMM17

    (914) 0x4401bb MOV	-0x60(%RBP),%RAX

    (914) 0x4401bf VFMADD231PD	(%RAX,%R12,1),%XMM12,%XMM17

    (914) 0x4401c6 MOV	-0x68(%RBP),%RAX

    (914) 0x4401ca VFMADD231PD	(%RAX,%R12,1),%XMM14,%XMM17

    (914) 0x4401d1 MOV	-0x70(%RBP),%RAX

    (914) 0x4401d5 VFMADD231PD	(%RAX,%R12,1),%XMM15,%XMM17

    (914) 0x4401dc VFMADD213PD	(%RDX,%R12,1),%XMM16,%XMM17

    (914) 0x4401e3 VMOVUPD	%XMM17,(%RDX,%R12,1)

    (914) 0x4401ea ADD	$0x10,%R12

    (914) 0x4401ee DEC	%RCX

    (914) 0x4401f1 JNE	4401b0

  (910) 0x4401f3 JMP	440010

0x4401f8 MOV	%EDX,%EAX

0x4401fa AND	$0x7,%EAX

0x4401fd CMP	$0x8,%EDX

0x440200 JB	440216

0x440202 AND	$0x7ffffff8,%EDX

0x440208 NOPL	(%RAX,%RAX,1)

(916) 0x440210 ADD	$-0x8,%RDX

(916) 0x440214 JNE	440210

0x440216 TEST	%RAX,%RAX

0x440219 JE	440225

0x44021b NOPL	(%RAX,%RAX,1)

(915) 0x440220 DEC	%RAX

(915) 0x440223 JNE	440220

0x440225 MOV	-0x110(%RBP),%RDI

0x44022c CALL	48e150 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x440231 MOV	-0xa8(%RBP),%R12

0x440238 MOV	0x30(%R12),%EAX

0x44023d TEST	%EAX,%EAX

0x44023f MOV	-0x108(%RBP),%R15

0x440246 JLE	4402a5

0x440248 XOR	%EBX,%EBX

0x44024a XOR	%R14D,%R14D

0x44024d JMP	44025c

0x44024f NOP

(908) 0x440250 MOVSXD	%EAX,%RCX

(908) 0x440253 ADD	$0x18,%RBX

(908) 0x440257 CMP	%RCX,%R14

(908) 0x44025a JGE	4402a5

(908) 0x44025c MOV	%R14D,%ECX

(908) 0x44025f IMUL	%EAX,%ECX

(908) 0x440262 INC	%R14

(908) 0x440265 MOV	0x40(%R12),%EDX

(908) 0x44026a IMUL	%R14D,%EDX

(908) 0x44026e MOV	0x8(%R12),%ESI

(908) 0x440273 CMP	%EDX,%ESI

(908) 0x440275 CMOVL	%ESI,%EDX

(908) 0x440278 SUB	%ECX,%EDX

(908) 0x44027a JLE	440250

(908) 0x44027c MOV	0x310(%R12),%RAX

(908) 0x440284 MOV	(%RAX,%RBX,1),%RSI

(908) 0x440288 MOVSXD	%ECX,%RDI

(908) 0x44028b SAL	$0x3,%RDI

(908) 0x44028f ADD	0x18(%R15),%RDI

(908) 0x440293 MOV	%EDX,%EDX

(908) 0x440295 SAL	$0x3,%RDX

(908) 0x440299 CALL	4040b0 <memmove@plt>

(908) 0x44029e MOV	0x30(%R12),%EAX

(908) 0x4402a3 JMP	440250

0x4402a5 ADD	$0x168,%RSP

0x4402ac POP	%RBX

0x4402ad POP	%R12

0x4402af POP	%R13

0x4402b1 POP	%R14

0x4402b3 POP	%R15

0x4402b5 POP	%RBP

0x4402b6 RET

0x4402b7 MOV	%RAX,%RDI

0x4402ba CALL	40e360 <__clang_call_terminate>

0x4402bf NOP

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::SPOSet::evaluateD[...]	OhmmsVector.h:178	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,429-431,923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:725,751
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,56-71

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.33 to 10.50 cycles (2.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 24.33 to 2.27 cycles (10.72x speedup).

Details

13% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__clang_call_terminate: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VROUNDSD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 280 bytes (35 double precision FP elements). The binary function is storing 152 bytes (19 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	140
nb uops	146
loop length	718
used x86 registers	12
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.33 cycles
front end	24.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.43	11.43	14.00	14.00	12.00	11.43	11.30	12.00	12.00	12.00	11.40	14.00
cycles	11.43	11.43	14.00	14.00	12.00	11.43	11.30	12.00	12.00	12.00	11.40	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.33
Dispatch	14.00
Overall L1	24.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	9%
store	100%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	13%
load	7%
store	26%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	10%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	15%
load	13%
store	25%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	12%
store	15%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 24.33 cycles. At this rate:

5% of peak load performance is reached (11.51 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.33 to 14.00 cycles (1.74x speedup).

ASM code

In the binary file, the address of the function is: 43f580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 48dfa0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %R12D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%RCX,%RCX,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
ADD 0x40(%R13),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x128(%R13),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %ECX,0x124(%R13)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
CMOVNE %RDX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RBX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 440225 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xca5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD 0xd8(%RCX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf0(%RCX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0x108(%RCX),%XMM3,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe0(%RCX),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf8(%RCX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x110(%RCX),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe8(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x100(%RCX),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x118(%RCX),%XMM3,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM2,%XMM2,%XMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM1,%XMM2,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPSD $0x1,%XMM1,%XMM2,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVSD 0xc08a2(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VROUNDSD $0x9,%XMM4,%XMM4,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD %XMM3,%XMM6,%XMM6{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM6,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM2,%XMM4,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM4,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM3,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM2,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM0,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM3,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x2f8(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x310(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x40(%RCX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RBX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 43fbf8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x678>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 4401f8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xc78>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDDUP 0xbd8d6(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 43f77e <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x1fe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 440225 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xca5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0xc0308(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbd400(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xbd3f8(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0xc0340(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0xc0348(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0xbd3f8(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc02e0(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc02e0(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 43fc7e <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6fe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 440216 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xc96>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $0x7ffffff8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 440225 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xca5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x110(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 48e150 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xa8(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV -0x108(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 4402a5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xd25>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 44025c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xcdc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 40e360 <__clang_call_terminate>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,429-431,923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:725,751
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,56-71

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

13% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

__clang_call_terminate: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VROUNDSD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 280 bytes (35 double precision FP elements). The binary function is storing 152 bytes (19 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	140
nb uops	146
loop length	718
used x86 registers	12
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.33 cycles
front end	24.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.43	11.43	14.00	14.00	12.00	11.43	11.30	12.00	12.00	12.00	11.40	14.00
cycles	11.43	11.43	14.00	14.00	12.00	11.43	11.30	12.00	12.00	12.00	11.40	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.33
Dispatch	14.00
Overall L1	24.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	9%
store	100%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	13%
load	7%
store	26%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	10%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	15%
load	13%
store	25%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	12%
store	15%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 24.33 cycles. At this rate:

5% of peak load performance is reached (11.51 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 43f580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 48dfa0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %R12D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%RCX,%RCX,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
ADD 0x40(%R13),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x128(%R13),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %ECX,0x124(%R13)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
CMOVNE %RDX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RBX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 440225 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xca5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD 0xd8(%RCX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf0(%RCX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0x108(%RCX),%XMM3,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe0(%RCX),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf8(%RCX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x110(%RCX),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe8(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x100(%RCX),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x118(%RCX),%XMM3,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM2,%XMM2,%XMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM1,%XMM2,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPSD $0x1,%XMM1,%XMM2,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVSD 0xc08a2(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VROUNDSD $0x9,%XMM4,%XMM4,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD %XMM3,%XMM6,%XMM6{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM6,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM2,%XMM4,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM4,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM3,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM2,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM0,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM3,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x2f8(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x310(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x40(%RCX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RBX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 43fbf8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x678>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 4401f8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xc78>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDDUP 0xbd8d6(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 43f77e <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x1fe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 440225 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xca5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0xc0308(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xbd400(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xbd3f8(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0xc0340(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0xc0348(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0xbd3f8(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc02e0(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc02e0(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 43fc7e <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6fe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 440216 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xc96>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $0x7ffffff8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 440225 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xca5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x110(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 48e150 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xa8(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV -0x108(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 4402a5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xd25>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 44025c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xcdc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 40e360 <__clang_call_terminate>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)–	20.54	17.65
▼Loop 917 - MultiBsplineRef.hpp:42-71 - exec–	0.00	0.01
▼Loop 918 - MultiBsplineRef.hpp:63-71 - exec–	0.00	0.01
▼Loop 919 - MultiBsplineRef.hpp:64-71 - exec–	0.00	0.01
○Loop 920 - MultiBsplineRef.hpp:68-70 - exec	20.52	17.48
○Loop 908 - einspline_spo_ref.hpp:183-187 - exec	0.00	0.01
○Loop 916 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00
▼Loop 909 - MultiBsplineRef.hpp:42-71 - exec–	0.00	0.00
▼Loop 910 - MultiBsplineRef.hpp:63-70 - exec–	0.00	0.00
○Loop 912 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 913 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 911 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 914 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 915 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00

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