OV - exec - Function qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const*, double*, double*, double*, double*, int*) const

	Function: qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const, double, do ...	Module: exec	Source: BsplineFunctor.h:275-339 [...]	Coverage (incl. loops): 0.52% \| (excl. loops): 0.00%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1064 - 1064

--------------------------------------------------------------------------------

1064: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 275 - 339

--------------------------------------------------------------------------------

275: {

276:   real_type dSquareDeltaRinv = DeltaRInv * DeltaRInv;

[...]

284:   int iLimit                 = iEnd - iStart;

285:   const real_type* distArray = _distArray + iStart;

[...]

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

298:       iCount++;

299:     }

300:   }

301:

302:   #pragma omp simd

303:   for (int j = 0; j < iCount; j++)

304:   {

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

337:     // clang-format on

338:   }

339: }

0x41fba0 PUSH	%RBP

0x41fba1 MOV	%RSP,%RBP

0x41fba4 PUSH	%R15

0x41fba6 PUSH	%R14

0x41fba8 PUSH	%R13

0x41fbaa PUSH	%R12

0x41fbac PUSH	%RBX

0x41fbad AND	$-0x20,%RSP

0x41fbb1 SUB	$0x3e0,%RSP

0x41fbb8 SUB	%EDX,%ECX

0x41fbba TEST	%ECX,%ECX

0x41fbbc JLE	420989

0x41fbc2 MOV	0x28(%RBP),%R11

0x41fbc6 MOV	0x20(%RBP),%R10

0x41fbca VMOVQ	0x238(%RDI),%XMM0

0x41fbd2 MOVSXD	%EDX,%R12

0x41fbd5 VMOVSD	0x8(%RDI),%XMM1

0x41fbda MOV	%ECX,%R15D

0x41fbdd MOV	%R15,%R14

0x41fbe0 AND	$0x7ffffff0,%R14

0x41fbe7 JE	41fbf8

0x41fbe9 CMP	$0x7,%ECX

0x41fbec JA	41fc02

0x41fbee XOR	%R14D,%R14D

0x41fbf1 XOR	%EBX,%EBX

0x41fbf3 JMP	41fdc5

0x41fbf8 XOR	%R14D,%R14D

0x41fbfb XOR	%EBX,%EBX

0x41fbfd JMP	41fdac

0x41fc02 MOV	%R9,0x120(%RSP)

0x41fc0a VPBROADCASTD	%ESI,%YMM2

0x41fc10 VBROADCASTSD	%XMM1,%YMM3

0x41fc15 MOV	%EDX,0xc0(%RSP)

0x41fc1c MOV	%EDX,%EDX

0x41fc1e MOV	%R12,0x100(%RSP)

0x41fc26 MOV	%R8,0xe0(%RSP)

0x41fc2e LEA	(%R8,%R12,8),%R12

0x41fc32 XOR	%EBX,%EBX

0x41fc34 VPMOVSXBD	0xde693(%RIP),%YMM4

0x41fc3d VPMOVSXBD	0xde692(%RIP),%YMM5

0x41fc46 XOR	%R13D,%R13D

0x41fc49 MOV	%R10,%RCX

0x41fc4c MOV	%R11,%R10

0x41fc4f NOP

(348) 0x41fc50 VMOVUPD	(%R12,%R13,8),%YMM7

(348) 0x41fc56 VMOVUPD	0x20(%R12,%R13,8),%YMM6

(348) 0x41fc5d VMOVUPD	0x40(%R12,%R13,8),%YMM8

(348) 0x41fc64 VMOVUPD	0x60(%R12,%R13,8),%YMM9

(348) 0x41fc6b LEA	(%RDX,%R13,1),%R11D

(348) 0x41fc6f VPBROADCASTD	%R11D,%YMM10

(348) 0x41fc75 VPADDD	%YMM4,%YMM10,%YMM11

(348) 0x41fc79 VPADDD	%YMM5,%YMM10,%YMM10

(348) 0x41fc7d VPCMPNEQD	%YMM2,%YMM10,%K0

(348) 0x41fc84 VPCMPNEQD	%YMM2,%YMM11,%K2

(348) 0x41fc8b VCMPPD	$0x1,%YMM3,%YMM7,%K4

(348) 0x41fc92 VCMPPD	$0x1,%YMM3,%YMM6,%K1

(348) 0x41fc99 KMOVW	%K1,0x20(%RSP)

(348) 0x41fc9f KSHIFTLB	$0x4,%K1,%K3

(348) 0x41fca5 KORB	%K3,%K4,%K3

(348) 0x41fca9 VCMPPD	$0x1,%YMM3,%YMM8,%K6

(348) 0x41fcb0 VPBROADCASTD	%R13D,%YMM10

(348) 0x41fcb6 VPADDD	%YMM5,%YMM10,%YMM11

(348) 0x41fcba MOVSXD	%EBX,%RBX

(348) 0x41fcbd KANDB	%K0,%K3,%K5

(348) 0x41fcc1 VPCOMPRESSD	%YMM11,(%R10,%RBX,4){%K5}

(348) 0x41fcc8 VCMPPD	$0x1,%YMM3,%YMM9,%K7

(348) 0x41fccf KMOVB	%K5,%R11D

(348) 0x41fcd3 KSHIFTLB	$0x4,%K7,%K5

(348) 0x41fcd9 KORB	%K5,%K6,%K5

(348) 0x41fcdd VPADDD	%YMM4,%YMM10,%YMM10

(348) 0x41fce1 LEA	(%R10,%RBX,4),%RAX

(348) 0x41fce5 POPCNT	%R11D,%R9D

(348) 0x41fcea KANDB	%K2,%K5,%K1

(348) 0x41fcee VPCOMPRESSD	%YMM10,(%RAX,%R9,4){%K1}

(348) 0x41fcf5 LEA	(%RCX,%RBX,8),%R11

(348) 0x41fcf9 KANDW	%K2,%K6,%K1

(348) 0x41fcfd VCOMPRESSPD	%YMM8,(%R11,%R9,8){%K1}

(348) 0x41fd04 KANDW	%K0,%K4,%K4

(348) 0x41fd08 VCOMPRESSPD	%YMM7,(%RCX,%RBX,8){%K4}

(348) 0x41fd0f KMOVB	%K1,0x1f(%RSP)

(348) 0x41fd15 KSHIFTRB	$0x4,%K2,%K1

(348) 0x41fd1b KANDW	%K1,%K7,%K1

(348) 0x41fd1f LEA	(%R11,%R9,8),%RAX

(348) 0x41fd23 MOVZX	0x1f(%RSP),%R9D

(348) 0x41fd29 POPCNT	%R9D,%R9D

(348) 0x41fd2e VCOMPRESSPD	%YMM9,(%RAX,%R9,8){%K1}

(348) 0x41fd35 KUNPCKBW	%K3,%K5,%K1

(348) 0x41fd39 KMOVB	%K4,0x1e(%RSP)

(348) 0x41fd3f KUNPCKBW	%K0,%K2,%K2

(348) 0x41fd43 KSHIFTRB	$0x4,%K0,%K0

(348) 0x41fd49 KMOVW	0x20(%RSP),%K3

(348) 0x41fd4f KANDW	%K0,%K3,%K3

(348) 0x41fd53 MOVZX	0x1e(%RSP),%EAX

(348) 0x41fd58 POPCNT	%EAX,%EAX

(348) 0x41fd5c VCOMPRESSPD	%YMM6,(%R11,%RAX,8){%K3}

(348) 0x41fd63 KANDW	%K2,%K1,%K0

(348) 0x41fd67 KMOVW	%K0,%EAX

(348) 0x41fd6b POPCNT	%EAX,%EAX

(348) 0x41fd6f ADD	%EAX,%EBX

(348) 0x41fd71 ADD	$0x10,%R13

(348) 0x41fd75 CMP	%R14,%R13

(348) 0x41fd78 JB	41fc50

0x41fd7e CMP	%R15D,%R14D

0x41fd81 MOV	0x120(%RSP),%R9

0x41fd89 MOV	%R10,%R11

0x41fd8c MOV	%RCX,%R10

0x41fd8f MOV	0x100(%RSP),%R12

0x41fd97 MOV	0xe0(%RSP),%R8

0x41fd9f MOV	0xc0(%RSP),%EDX

0x41fda6 JE	41ffab

0x41fdac VMOVQ	%R15,%XMM3

0x41fdb1 VMOVD	%R14D,%XMM2

0x41fdb6 VPSUBQ	%YMM2,%YMM3,%YMM3

0x41fdba VMOVQ	%XMM3,%RCX

0x41fdbf CMP	$0x8,%RCX

0x41fdc3 JAE	41fdfe

0x41fdc5 SUB	%EDX,%ESI

0x41fdc7 LEA	(%R8,%R12,8),%RCX

0x41fdcb JMP	41fddc

0x41fdcd NOPL	(%RAX)

(347) 0x41fdd0 INC	%R14

(347) 0x41fdd3 CMP	%R14,%R15

(347) 0x41fdd6 JE	41ffab

(347) 0x41fddc VMOVSD	(%RCX,%R14,8),%XMM2

(347) 0x41fde2 VUCOMISD	%XMM2,%XMM1

(347) 0x41fde6 JBE	41fdd0

(347) 0x41fde8 CMP	%R14D,%ESI

(347) 0x41fdeb JE	41fdd0

(347) 0x41fded MOVSXD	%EBX,%RBX

(347) 0x41fdf0 MOV	%R14D,(%R11,%RBX,4)

(347) 0x41fdf4 VMOVSD	%XMM2,(%R10,%RBX,8)

(347) 0x41fdfa INC	%EBX

(347) 0x41fdfc JMP	41fdd0

0x41fdfe VPBROADCASTQ	%XMM3,%YMM3

0x41fe03 VPCMPNLEUQ	0xde5d2(%RIP),%YMM3,%K2

0x41fe0e VPCMPNLEUQ	0xde5e7(%RIP),%YMM3,%K3

0x41fe19 KSHIFTLB	$0x4,%K3,%K0

0x41fe1f KORB	%K0,%K2,%K1

0x41fe23 VPCMPNLEUQ	0xde5f2(%RIP),%YMM3,%K4

0x41fe2e VPCMPNLEUQ	0xde607(%RIP),%YMM3,%K5

0x41fe39 KSHIFTLB	$0x4,%K5,%K0

0x41fe3f ADD	%R12,%R14

0x41fe42 VMOVUPD	0x60(%R8,%R14,8),%YMM3{%K5}{z}

0x41fe4a VMOVUPD	0x40(%R8,%R14,8),%YMM4{%K4}{z}

0x41fe52 KORB	%K0,%K4,%K0

0x41fe56 KMOVW	%K0,0x20(%RSP)

0x41fe5c VMOVUPD	0x20(%R8,%R14,8),%YMM5{%K3}{z}

0x41fe64 VMOVUPD	(%R8,%R14,8),%YMM6{%K2}{z}

0x41fe6b VPBROADCASTD	%EDX,%YMM7

0x41fe71 VPMOVQD	%YMM2,%XMM2

0x41fe77 VPBROADCASTD	%XMM2,%YMM2

0x41fe7c VPOR	0xde61c(%RIP),%YMM2,%YMM8

0x41fe84 VPOR	0xde634(%RIP),%YMM2,%YMM2

0x41fe8c VPADDD	%YMM2,%YMM7,%YMM9

0x41fe90 VPADDD	%YMM7,%YMM8,%YMM7

0x41fe94 VPBROADCASTD	%ESI,%YMM10

0x41fe9a VPCMPNEQD	%YMM10,%YMM7,%K3

0x41fea1 VPCMPNEQD	%YMM10,%YMM9,%K4

0x41fea8 VBROADCASTSD	%XMM1,%YMM1

0x41fead VCMPPD	$0x1,%YMM1,%YMM6,%K2

0x41feb4 VCMPPD	$0x1,%YMM1,%YMM5,%K5

0x41febb KSHIFTLB	$0x4,%K5,%K5

0x41fec1 KORB	%K5,%K2,%K2

0x41fec5 VCMPPD	$0x1,%YMM1,%YMM4,%K5

0x41fecc VCMPPD	$0x1,%YMM1,%YMM3,%K6

0x41fed3 KSHIFTLB	$0x4,%K6,%K6

0x41fed9 KORB	%K6,%K5,%K5

0x41fedd MOVSXD	%EBX,%RCX

0x41fee0 LEA	(%R11,%RCX,4),%RAX

0x41fee4 KANDB	%K3,%K1,%K6

0x41fee8 KANDB	%K2,%K6,%K6

0x41feec VPCOMPRESSD	%YMM8,(%R11,%RCX,4){%K6}

0x41fef3 KANDB	%K4,%K0,%K7

0x41fef7 KANDB	%K5,%K7,%K7

0x41fefb KMOVB	%K6,%EDX

0x41feff POPCNT	%EDX,%EDX

0x41ff03 VPCOMPRESSD	%YMM2,(%RAX,%RDX,4){%K7}

0x41ff0a LEA	(%R10,%RCX,8),%RAX

0x41ff0e VCOMPRESSPD	%YMM4,(%RAX,%RDX,8){%K7}

0x41ff15 VCOMPRESSPD	%YMM6,(%R10,%RCX,8){%K6}

0x41ff1c KSHIFTLB	$0x4,%K7,%K0

0x41ff22 KSHIFTRB	$0x4,%K0,%K0

0x41ff28 KMOVB	%K0,0x1d(%RSP)

0x41ff2e LEA	(%RAX,%RDX,8),%RDX

0x41ff32 KSHIFTRB	$0x4,%K7,%K7

0x41ff38 MOVZX	0x1d(%RSP),%ESI

0x41ff3d POPCNT	%ESI,%ESI

0x41ff41 VCOMPRESSPD	%YMM3,(%RDX,%RSI,8){%K7}

0x41ff48 KUNPCKBW	%K3,%K4,%K0

0x41ff4c KSHIFTLB	$0x4,%K6,%K3

0x41ff52 KSHIFTRB	$0x4,%K3,%K3

0x41ff58 KMOVB	%K3,0x1c(%RSP)

0x41ff5e KSHIFTRB	$0x4,%K6,%K3

0x41ff64 MOVZX	0x1c(%RSP),%EDX

0x41ff69 POPCNT	%EDX,%EDX

0x41ff6d VCOMPRESSPD	%YMM5,(%RAX,%RDX,8){%K3}

0x41ff74 KUNPCKBW	%K2,%K5,%K2

0x41ff78 KMOVW	0x20(%RSP),%K3

0x41ff7e KUNPCKBW	%K1,%K3,%K3

0x41ff82 KANDW	%K0,%K3,%K0

0x41ff86 KANDW	%K0,%K3,%K0

0x41ff8a KANDW	%K2,%K0,%K0

0x41ff8e KMOVW	%K0,%EAX

0x41ff92 VMOVD	%EBX,%XMM1

0x41ff96 POPCNT	%EAX,%EAX

0x41ff9a ADD	%EAX,%ECX

0x41ff9c VMOVD	%ECX,%XMM2

0x41ffa0 VINSERTI32X4	$0,%XMM2,%YMM0,%YMM1{%K1}

0x41ffa7 VMOVD	%XMM1,%EBX

0x41ffab TEST	%EBX,%EBX

0x41ffad JLE	420989

0x41ffb3 MOV	0x18(%RBP),%RDX

0x41ffb7 MOV	0x10(%RBP),%RCX

0x41ffbb MOV	0x218(%RDI),%RSI

0x41ffc2 VMOVSD	0x128(%RDI),%XMM13

0x41ffca VMOVQ	0x130(%RDI),%XMM7

0x41ffd2 VMOVSD	0x148(%RDI),%XMM14

0x41ffda VMOVSD	0x150(%RDI),%XMM16

0x41ffe1 VMOVSD	0x168(%RDI),%XMM15

0x41ffe9 VMOVSD	0x170(%RDI),%XMM12

0x41fff1 VMOVSD	0x188(%RDI),%XMM2

0x41fff9 VMOVSD	0x190(%RDI),%XMM31

0x420000 VMOVSD	0xa0(%RDI),%XMM22

0x420007 VMOVSD	0xa8(%RDI),%XMM21

0x42000e VMOVSD	0xb0(%RDI),%XMM10

0x420016 VMOVSD	0xc0(%RDI),%XMM9

0x42001e VMOVSD	0xc8(%RDI),%XMM6

0x420026 VMOVSD	0xd0(%RDI),%XMM11

0x42002e VMOVSD	0xe0(%RDI),%XMM30

0x420035 VMOVSD	0xe8(%RDI),%XMM1

0x42003d VMOVSD	0xf0(%RDI),%XMM5

0x420045 VMOVSD	0x100(%RDI),%XMM20

0x42004c VMOVSD	0x108(%RDI),%XMM19

0x420053 VMOVSD	0x110(%RDI),%XMM23

0x42005a VMOVSD	0x18(%RDI),%XMM18

0x420061 VMOVSD	0x20(%RDI),%XMM25

0x420068 VMOVSD	0x28(%RDI),%XMM24

0x42006f VMOVSD	0x30(%RDI),%XMM28

0x420076 VMOVSD	0x38(%RDI),%XMM3

0x42007b VMOVUPS	%XMM3,0x40(%RSP)

0x420081 VMOVSD	0x40(%RDI),%XMM3

0x420086 VMOVUPS	%XMM3,0x60(%RSP)

0x42008c VMOVSD	0x48(%RDI),%XMM3

0x420091 VMOVUPS	%XMM3,0x80(%RSP)

0x42009a VMOVSD	0x50(%RDI),%XMM3

0x42009f VMOVUPS	%XMM3,0xa0(%RSP)

0x4200a8 VMOVSD	0x58(%RDI),%XMM26

0x4200af VMOVSD	0x60(%RDI),%XMM3

0x4200b4 VMOVUPS	%XMM3,0x190(%RSP)

0x4200bd VMOVSD	0x68(%RDI),%XMM8

0x4200c2 VMOVSD	0x70(%RDI),%XMM3

0x4200c7 MOV	%EBX,%EBX

0x4200c9 MOV	%RBX,%R8

0x4200cc VMOVSD	0x78(%RDI),%XMM4

0x4200d1 VMOVUPS	%XMM4,0x150(%RSP)

0x4200da VMOVSD	0x80(%RDI),%XMM4

0x4200e2 VMOVUPS	%XMM4,0x160(%RSP)

0x4200eb VMOVSD	0x88(%RDI),%XMM4

0x4200f3 VMOVUPS	%XMM4,0x170(%RSP)

0x4200fc VMOVSD	0x90(%RDI),%XMM4

0x420104 VMOVUPS	%XMM4,0x180(%RSP)

0x42010d VMULSD	%XMM0,%XMM0,%XMM17

0x420113 AND	$0x7ffffffc,%R8

0x42011a JE	42063c

0x420120 VBROADCASTSD	%XMM0,%YMM4

0x420125 VBROADCASTSD	%XMM13,%YMM0

0x42012a VMOVUPD	%YMM0,0x260(%RSP)

0x420133 VPBROADCASTQ	%XMM7,%YMM0

0x420138 VMOVDQU	%YMM0,0x300(%RSP)

0x420141 VBROADCASTSD	%XMM14,%YMM0

0x420146 VMOVUPD	%YMM0,0x240(%RSP)

0x42014f VBROADCASTSD	%XMM16,%YMM0

0x420155 VMOVUPD	%YMM0,0x3a0(%RSP)

0x42015e VBROADCASTSD	%XMM15,%YMM0

0x420163 VMOVUPS	%YMM0,0xc0(%RSP)

0x42016c VBROADCASTSD	%XMM12,%YMM0

0x420171 VMOVUPS	%YMM0,0x120(%RSP)

0x42017a VBROADCASTSD	%XMM2,%YMM0

0x42017f VMOVUPD	%YMM0,0x100(%RSP)

0x420188 VBROADCASTSD	%XMM31,%YMM0

0x42018e VMOVUPD	%YMM0,0x380(%RSP)

0x420197 VBROADCASTSD	%XMM17,%YMM0

0x42019d VMOVUPD	%YMM0,0x20(%RSP)

0x4201a3 VBROADCASTSD	%XMM22,%YMM0

0x4201a9 VMOVUPD	%YMM0,0x2c0(%RSP)

0x4201b2 VBROADCASTSD	%XMM21,%YMM0

0x4201b8 VMOVUPD	%YMM0,0x2e0(%RSP)

0x4201c1 VBROADCASTSD	%XMM10,%YMM0

0x4201c6 VMOVUPD	%YMM0,0x340(%RSP)

0x4201cf VBROADCASTSD	%XMM9,%YMM0

0x4201d4 VMOVUPD	%YMM0,0x280(%RSP)

0x4201dd VBROADCASTSD	%XMM6,%YMM0

0x4201e2 VMOVUPD	%YMM0,0x2a0(%RSP)

0x4201eb VBROADCASTSD	%XMM11,%YMM0

0x4201f0 VMOVUPD	%YMM0,0x360(%RSP)

0x4201f9 VBROADCASTSD	%XMM30,%YMM0

0x4201ff VMOVUPS	%YMM0,0x1c0(%RSP)

0x420208 VBROADCASTSD	%XMM1,%YMM0

0x42020d VMOVUPD	%YMM0,0x1a0(%RSP)

0x420216 VBROADCASTSD	%XMM5,%YMM0

0x42021b VMOVUPD	%YMM0,0x320(%RSP)

0x420224 VBROADCASTSD	%XMM20,%YMM0

0x42022a VMOVUPD	%YMM0,0xe0(%RSP)

0x420233 VBROADCASTSD	%XMM19,%YMM9

0x420239 VBROADCASTSD	%XMM23,%YMM16

0x42023f VBROADCASTSD	%XMM18,%YMM10

0x420245 VBROADCASTSD	%XMM25,%YMM29

0x42024b VBROADCASTSD	%XMM24,%YMM27

0x420251 VBROADCASTSD	%XMM28,%YMM28

0x420257 VBROADCASTSD	0x40(%RSP),%YMM14

0x42025e VBROADCASTSD	0x60(%RSP),%YMM13

0x420265 VBROADCASTSD	0x80(%RSP),%YMM31

0x42026d VBROADCASTSD	0xa0(%RSP),%YMM0

0x420277 VBROADCASTSD	%XMM26,%YMM26

0x42027d VBROADCASTSD	0x190(%RSP),%YMM19

0x420285 VBROADCASTSD	%XMM8,%YMM30

0x42028b VBROADCASTSD	%XMM3,%YMM12

0x420290 VBROADCASTSD	0x150(%RSP),%YMM11

0x42029a VBROADCASTSD	0x160(%RSP),%YMM25

0x4202a2 VBROADCASTSD	0x170(%RSP),%YMM23

0x4202aa VBROADCASTSD	0x180(%RSP),%YMM15

0x4202b4 XOR	%EDI,%EDI

0x4202b6 VPBROADCASTQ	%R12,%YMM22

0x4202bc NOPL	(%RAX)

(346) 0x4202c0 VMOVUPD	(%R10,%RDI,8),%YMM17

(346) 0x4202c7 VMULPD	%YMM4,%YMM17,%YMM1

(346) 0x4202cd VCVTTPD2DQ	%YMM1,%XMM21

(346) 0x4202d3 VMOVAPD	%YMM23,%YMM5

(346) 0x4202d9 VXORPD	%XMM23,%XMM23,%XMM23

(346) 0x4202df KXNORW	%K0,%K0,%K1

(346) 0x4202e3 VGATHERDPD	(%RSI,%XMM21,8),%YMM23{%K1}

(346) 0x4202ea VMOVDQA64	%YMM22,%YMM7

(346) 0x4202f0 VPXORD	%XMM22,%XMM22,%XMM22

(346) 0x4202f6 KXNORW	%K0,%K0,%K1

(346) 0x4202fa VGATHERDPD	0x8(%RSI,%XMM21,8),%YMM22{%K1}

(346) 0x420302 VROUNDPD	$0xb,%YMM1,%YMM2

(346) 0x420308 VXORPD	%XMM20,%XMM20,%XMM20

(346) 0x42030e KXNORW	%K0,%K0,%K1

(346) 0x420312 VGATHERDPD	0x10(%RSI,%XMM21,8),%YMM20{%K1}

(346) 0x42031a VSUBPD	%YMM2,%YMM1,%YMM6

(346) 0x42031e VMULPD	%YMM6,%YMM6,%YMM24

(346) 0x420324 VMULPD	%YMM6,%YMM24,%YMM18

(346) 0x42032a VMOVAPD	%YMM19,%YMM3

(346) 0x420330 VMOVAPD	%YMM30,%YMM19

(346) 0x420336 VMOVAPD	%YMM15,%YMM30

(346) 0x42033c VMOVAPD	%YMM12,%YMM15

(346) 0x420341 VMOVAPD	%YMM11,%YMM12

(346) 0x420346 VMOVAPD	%YMM25,%YMM11

(346) 0x42034c VMOVAPD	%YMM6,%YMM25

(346) 0x420352 VMOVAPD	%YMM24,%YMM2

(346) 0x420358 VMOVUPD	0x340(%RSP),%YMM1

(346) 0x420361 VFMADD132PD	0x2c0(%RSP),%YMM1,%YMM2

(346) 0x42036b VFMADD231PD	0x2e0(%RSP),%YMM6,%YMM2

(346) 0x420375 VMOVAPD	%YMM6,%YMM1

(346) 0x420379 VMOVUPD	0x300(%RSP),%YMM8

(346) 0x420382 VFMADD132PD	0x260(%RSP),%YMM8,%YMM1

(346) 0x42038c VMULPD	%YMM23,%YMM1,%YMM1

(346) 0x420392 VMOVUPD	0x240(%RSP),%YMM8

(346) 0x42039b VFMADD213PD	0x3a0(%RSP),%YMM8,%YMM25

(346) 0x4203a3 VFMADD213PD	%YMM1,%YMM22,%YMM25

(346) 0x4203a9 VMOVAPD	%YMM24,%YMM1

(346) 0x4203af VMOVUPD	0x280(%RSP),%YMM8

(346) 0x4203b8 VFMADD213PD	0x360(%RSP),%YMM8,%YMM1

(346) 0x4203c2 VFMADD231PD	0x2a0(%RSP),%YMM6,%YMM1

(346) 0x4203cc VMULPD	%YMM23,%YMM2,%YMM2

(346) 0x4203d2 VFMADD213PD	%YMM2,%YMM22,%YMM1

(346) 0x4203d8 VMOVAPD	%YMM18,%YMM2

(346) 0x4203de VFMADD213PD	%YMM28,%YMM10,%YMM2

(346) 0x4203e4 VFMADD231PD	%YMM24,%YMM29,%YMM2

(346) 0x4203ea VFMADD231PD	%YMM6,%YMM27,%YMM2

(346) 0x4203f0 VMULPD	%YMM23,%YMM2,%YMM2

(346) 0x4203f6 VMOVAPD	%YMM18,%YMM23

(346) 0x4203fc VFMADD213PD	%YMM0,%YMM14,%YMM23

(346) 0x420402 VFMADD231PD	%YMM24,%YMM13,%YMM23

(346) 0x420408 VFMADD231PD	%YMM6,%YMM31,%YMM23

(346) 0x42040e VFMADD213PD	%YMM2,%YMM22,%YMM23

(346) 0x420414 VXORPD	%XMM2,%XMM2,%XMM2

(346) 0x420418 KXNORW	%K0,%K0,%K1

(346) 0x42041c VGATHERDPD	0x18(%RSI,%XMM21,8),%YMM2{%K1}

(346) 0x420424 VMOVAPD	%YMM6,%YMM21

(346) 0x42042a VMOVUPD	0xc0(%RSP),%YMM22

(346) 0x420432 VFMADD213PD	0x120(%RSP),%YMM22,%YMM21

(346) 0x42043a VFMADD213PD	%YMM25,%YMM20,%YMM21

(346) 0x420440 VMOVAPD	%YMM11,%YMM25

(346) 0x420446 VMOVAPD	%YMM12,%YMM11

(346) 0x42044b VMOVAPD	%YMM15,%YMM12

(346) 0x420450 VMOVAPD	%YMM30,%YMM15

(346) 0x420456 VMOVAPD	%YMM19,%YMM30

(346) 0x42045c VMOVAPD	%YMM3,%YMM19

(346) 0x420462 VMOVAPD	%YMM24,%YMM22

(346) 0x420468 VMOVUPD	0x320(%RSP),%YMM3

(346) 0x420471 VFMADD132PD	0x1c0(%RSP),%YMM3,%YMM22

(346) 0x420479 VFMADD231PD	0x1a0(%RSP),%YMM6,%YMM22

(346) 0x420481 VFMADD213PD	%YMM1,%YMM20,%YMM22

(346) 0x420487 VMOVAPD	%YMM18,%YMM1

(346) 0x42048d VFMADD213PD	%YMM12,%YMM26,%YMM1

(346) 0x420493 VFMADD231PD	%YMM24,%YMM19,%YMM1

(346) 0x420499 VFMADD231PD	%YMM6,%YMM30,%YMM1

(346) 0x42049f VFMADD213PD	%YMM23,%YMM20,%YMM1

(346) 0x4204a5 VMOVAPD	%YMM5,%YMM23

(346) 0x4204ab VFMADD213PD	%YMM15,%YMM11,%YMM18

(346) 0x4204b1 VFMADD231PD	%YMM24,%YMM25,%YMM18

(346) 0x4204b7 VFMADD132PD	0xe0(%RSP),%YMM16,%YMM24

(346) 0x4204bf VFMADD231PD	%YMM6,%YMM9,%YMM24

(346) 0x4204c5 VFMADD231PD	%YMM6,%YMM5,%YMM18

(346) 0x4204cb VMOVUPD	0x380(%RSP),%YMM3

(346) 0x4204d4 VFMADD132PD	0x100(%RSP),%YMM3,%YMM6

(346) 0x4204de VFMADD213PD	%YMM21,%YMM2,%YMM6

(346) 0x4204e4 VFMADD213PD	%YMM22,%YMM2,%YMM24

(346) 0x4204ea VMOVDQA64	%YMM7,%YMM22

(346) 0x4204f0 VFMADD213PD	%YMM1,%YMM2,%YMM18

(346) 0x4204f6 VMULPD	%YMM4,%YMM24,%YMM1

(346) 0x4204fc VDIVPD	%YMM17,%YMM1,%YMM1

(346) 0x420502 VPMOVSXDQ	(%R11,%RDI,4),%YMM2

(346) 0x420508 VMULPD	0x20(%RSP),%YMM6,%YMM6

(346) 0x42050e VPADDQ	%YMM2,%YMM7,%YMM2

(346) 0x420512 KXNORW	%K0,%K0,%K1

(346) 0x420516 VSCATTERQPD	%YMM6,(%RDX,%YMM2,8){%K1}

(346) 0x42051d KXNORW	%K0,%K0,%K1

(346) 0x420521 VSCATTERQPD	%YMM1,(%RCX,%YMM2,8){%K1}

(346) 0x420528 KXNORW	%K0,%K0,%K1

(346) 0x42052c VSCATTERQPD	%YMM18,(%R9,%YMM2,8){%K1}

(346) 0x420533 ADD	$0x4,%RDI

(346) 0x420537 CMP	%R8,%RDI

(346) 0x42053a JB	4202c0

0x420540 VMOVUPD	%YMM14,0x40(%RSP)

0x420546 VMOVUPD	%YMM13,0x60(%RSP)

0x42054c VMOVAPD	%YMM31,%YMM21

0x420552 VMOVAPD	%YMM27,%YMM24

0x420558 VMOVUPD	0x340(%RSP),%YMM17

0x420560 VMOVUPD	0x360(%RSP),%YMM31

0x420568 VMOVUPD	0x320(%RSP),%YMM8

0x420571 VMOVUPD	0x3a0(%RSP),%YMM3

0x42057a VMOVUPD	0x380(%RSP),%YMM27

0x420582 CMP	%EBX,%R8D

0x420585 JE	420989

0x42058b VMOVAPD	%YMM10,%YMM20

0x420591 VMOVAPD	%YMM29,%YMM18

0x420597 VMOVAPD	%YMM26,%YMM2

0x42059d VPBROADCASTQ	%RBX,%YMM10

0x4205a3 VMOVAPD	%YMM27,%YMM26

0x4205a9 VMOVAPD	%YMM3,%YMM29

0x4205af VMOVUPD	%YMM9,0x220(%RSP)

0x4205b8 VMOVAPD	%YMM8,%YMM5

0x4205bc VMOVAPD	%YMM16,%YMM8

0x4205c2 VMOVAPD	%YMM31,%YMM7

0x4205c8 VMOVAPD	%YMM0,%YMM14

0x4205cc VMOVAPD	%YMM4,%YMM0

0x4205d0 VMOVUPD	%YMM2,0xa0(%RSP)

0x4205d9 VMOVAPD	%YMM28,%YMM4

0x4205df VMOVAPD	%YMM17,%YMM3

0x4205e5 VMOVUPD	%YMM18,0x200(%RSP)

0x4205ed VMOVUPD	%YMM20,0x1e0(%RSP)

0x4205f5 VMOVUPD	%YMM21,0x80(%RSP)

0x4205fd VMOVDQU	0x300(%RSP),%YMM13

0x420606 VMOVUPD	0x2e0(%RSP),%YMM21

0x42060e VMOVUPD	0x2c0(%RSP),%YMM31

0x420616 VMOVUPD	0x2a0(%RSP),%YMM16

0x42061e VMOVUPD	0x280(%RSP),%YMM9

0x420627 VMOVUPD	0x260(%RSP),%YMM28

0x42062f VMOVUPD	0x240(%RSP),%YMM27

0x420637 JMP	4207cb

0x42063c VBROADCASTSD	%XMM0,%YMM0

0x420641 VMOVAPD	%XMM28,%XMM4

0x420647 VBROADCASTSD	%XMM13,%YMM28

0x42064d VPBROADCASTQ	%XMM7,%YMM13

0x420652 VBROADCASTSD	%XMM14,%YMM27

0x420658 VBROADCASTSD	%XMM16,%YMM29

0x42065e VMOVAPD	%XMM3,%XMM16

0x420664 VBROADCASTSD	%XMM15,%YMM3

0x420669 VMOVUPS	%YMM3,0xc0(%RSP)

0x420672 VBROADCASTSD	%XMM12,%YMM3

0x420677 VMOVUPS	%YMM3,0x120(%RSP)

0x420680 VBROADCASTSD	%XMM2,%YMM2

0x420685 VMOVUPD	%YMM2,0x100(%RSP)

0x42068e VMOVAPD	%XMM26,%XMM12

0x420694 VBROADCASTSD	%XMM31,%YMM26

0x42069a VBROADCASTSD	%XMM17,%YMM2

0x4206a0 VMOVUPD	%YMM2,0x20(%RSP)

0x4206a6 VBROADCASTSD	%XMM22,%YMM31

0x4206ac VBROADCASTSD	%XMM21,%YMM21

0x4206b2 VBROADCASTSD	%XMM10,%YMM3

0x4206b7 VBROADCASTSD	%XMM9,%YMM9

0x4206bc VBROADCASTSD	%XMM6,%YMM6

0x4206c1 VBROADCASTSD	%XMM11,%YMM7

0x4206c6 VBROADCASTSD	%XMM30,%YMM2

0x4206cc VMOVUPS	%YMM2,0x1c0(%RSP)

0x4206d5 VBROADCASTSD	%XMM1,%YMM1

0x4206da VMOVUPD	%YMM1,0x1a0(%RSP)

0x4206e3 VBROADCASTSD	%XMM5,%YMM5

0x4206e8 VBROADCASTSD	%XMM20,%YMM1

0x4206ee VMOVUPD	%YMM1,0xe0(%RSP)

0x4206f7 VBROADCASTSD	%XMM19,%YMM1

0x4206fd VMOVUPD	%YMM1,0x220(%RSP)

0x420706 VMOVAPD	%XMM8,%XMM2

0x42070a VBROADCASTSD	%XMM23,%YMM8

0x420710 VBROADCASTSD	%XMM18,%YMM1

0x420716 VMOVUPD	%YMM1,0x1e0(%RSP)

0x42071f VBROADCASTSD	%XMM25,%YMM1

0x420725 VMOVUPD	%YMM1,0x200(%RSP)

0x42072e VBROADCASTSD	%XMM24,%YMM24

0x420734 VBROADCASTSD	%XMM4,%YMM4

0x420739 VBROADCASTSD	0x40(%RSP),%YMM1

0x420740 VMOVUPS	%YMM1,0x40(%RSP)

0x420746 VBROADCASTSD	0x60(%RSP),%YMM1

0x42074d VMOVUPS	%YMM1,0x60(%RSP)

0x420753 VBROADCASTSD	0x80(%RSP),%YMM1

0x42075d VMOVUPS	%YMM1,0x80(%RSP)

0x420766 VBROADCASTSD	0xa0(%RSP),%YMM14

0x420770 VBROADCASTSD	%XMM12,%YMM1

0x420775 VMOVUPD	%YMM1,0xa0(%RSP)

0x42077e VBROADCASTSD	0x190(%RSP),%YMM19

0x420786 VBROADCASTSD	%XMM2,%YMM30

0x42078c VBROADCASTSD	%XMM16,%YMM12

0x420792 VMOVAPD	%YMM6,%YMM16

0x420798 VBROADCASTSD	0x150(%RSP),%YMM11

0x4207a2 VBROADCASTSD	0x160(%RSP),%YMM25

0x4207aa VBROADCASTSD	0x170(%RSP),%YMM23

0x4207b2 VBROADCASTSD	0x180(%RSP),%YMM15

0x4207bc XOR	%R8D,%R8D

0x4207bf VPBROADCASTQ	%RBX,%YMM10

0x4207c5 VPBROADCASTQ	%R12,%YMM22

0x4207cb VPBROADCASTQ	%R8,%YMM1

0x4207d1 VPSUBQ	%YMM1,%YMM10,%YMM1

0x4207d5 VPCMPNLEUQ	0xddc00(%RIP),%YMM1,%K1

0x4207e0 VMOVUPD	(%R10,%R8,8),%YMM10{%K1}{z}

0x4207e7 KMOVQ	%K1,%K2

0x4207ec VMULPD	%YMM0,%YMM10,%YMM1

0x4207f0 VCVTTPD2DQ	%YMM1,%XMM18

0x4207f6 VXORPD	%XMM20,%XMM20,%XMM20

0x4207fc VGATHERDPD	(%RSI,%XMM18,8),%YMM20{%K2}

0x420803 KMOVQ	%K1,%K2

0x420808 VXORPD	%XMM2,%XMM2,%XMM2

0x42080c VGATHERDPD	0x8(%RSI,%XMM18,8),%YMM2{%K2}

0x420814 VROUNDPD	$0xb,%YMM1,%YMM6

0x42081a VSUBPD	%YMM6,%YMM1,%YMM17

0x420820 VFMADD231PD	%YMM28,%YMM17,%YMM13

0x420826 VFMADD231PD	%YMM27,%YMM17,%YMM29

0x42082c VMULPD	%YMM20,%YMM13,%YMM1

0x420832 VFMADD213PD	%YMM1,%YMM2,%YMM29

0x420838 VMULPD	%YMM17,%YMM17,%YMM1

0x42083e VFMADD231PD	%YMM31,%YMM1,%YMM3

0x420844 VFMADD231PD	%YMM21,%YMM17,%YMM3

0x42084a VFMADD231PD	%YMM9,%YMM1,%YMM7

0x42084f VFMADD231PD	%YMM16,%YMM17,%YMM7

0x420855 VMULPD	%YMM20,%YMM3,%YMM3

0x42085b VFMADD213PD	%YMM3,%YMM2,%YMM7

0x420860 VMULPD	%YMM17,%YMM1,%YMM3

0x420866 VFMADD231PD	0x1e0(%RSP),%YMM3,%YMM4

0x420870 VFMADD231PD	0x200(%RSP),%YMM1,%YMM4

0x42087a VFMADD231PD	%YMM24,%YMM17,%YMM4

0x420880 VMULPD	%YMM20,%YMM4,%YMM4

0x420886 VFMADD231PD	0x40(%RSP),%YMM3,%YMM14

0x42088d VFMADD231PD	0x60(%RSP),%YMM1,%YMM14

0x420894 VFMADD231PD	0x80(%RSP),%YMM17,%YMM14

0x42089c VFMADD213PD	%YMM4,%YMM2,%YMM14

0x4208a1 VXORPD	%XMM2,%XMM2,%XMM2

0x4208a5 KMOVQ	%K1,%K2

0x4208aa VGATHERDPD	0x10(%RSI,%XMM18,8),%YMM2{%K2}

0x4208b2 VMOVUPD	0x120(%RSP),%YMM4

0x4208bb VFMADD231PD	0xc0(%RSP),%YMM17,%YMM4

0x4208c3 VFMADD213PD	%YMM29,%YMM2,%YMM4

0x4208c9 VFMADD231PD	0x1c0(%RSP),%YMM1,%YMM5

0x4208d3 VFMADD231PD	0x1a0(%RSP),%YMM17,%YMM5

0x4208db VFMADD213PD	%YMM7,%YMM2,%YMM5

0x4208e0 VFMADD231PD	0xa0(%RSP),%YMM3,%YMM12

0x4208ea VFMADD231PD	%YMM19,%YMM1,%YMM12

0x4208f0 VFMADD231PD	%YMM30,%YMM17,%YMM12

0x4208f6 VFMADD213PD	%YMM14,%YMM2,%YMM12

0x4208fb VFMADD231PD	%YMM11,%YMM3,%YMM15

0x420900 VXORPD	%XMM2,%XMM2,%XMM2

0x420904 KMOVQ	%K1,%K2

0x420909 VGATHERDPD	0x18(%RSI,%XMM18,8),%YMM2{%K2}

0x420911 VFMADD231PD	0x100(%RSP),%YMM17,%YMM26

0x420919 VFMADD213PD	%YMM4,%YMM2,%YMM26

0x42091f VMULPD	0x20(%RSP),%YMM26,%YMM3

0x420927 VMOVDQU32	(%R11,%R8,4),%XMM4{%K1}{z}

0x42092e VPMOVSXDQ	%XMM4,%YMM4

0x420933 VPADDQ	%YMM4,%YMM22,%YMM22{%K1}

0x420939 KMOVQ	%K1,%K2

0x42093e VSCATTERQPD	%YMM3,(%RDX,%YMM22,8){%K2}

0x420945 VFMADD231PD	0xe0(%RSP),%YMM1,%YMM8

0x42094f VFMADD231PD	%YMM25,%YMM1,%YMM15

0x420955 VFMADD231PD	0x220(%RSP),%YMM17,%YMM8

0x42095d VFMADD231PD	%YMM23,%YMM17,%YMM15

0x420963 VFMADD213PD	%YMM5,%YMM2,%YMM8

0x420968 VMULPD	%YMM0,%YMM8,%YMM0

0x42096c VDIVPD	%YMM10,%YMM0,%YMM0

0x420971 KMOVQ	%K1,%K2

0x420976 VSCATTERQPD	%YMM0,(%RCX,%YMM22,8){%K2}

0x42097d VFMADD213PD	%YMM12,%YMM2,%YMM15

0x420982 VSCATTERQPD	%YMM15,(%R9,%YMM22,8){%K1}

0x420989 LEA	-0x28(%RBP),%RSP

0x42098d POP	%RBX

0x42098e POP	%R12

0x420990 POP	%R13

0x420992 POP	%R14

0x420994 POP	%R15

0x420996 POP	%RBP

0x420997 VZEROUPPER

0x42099a RET

0x42099b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►49.03+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►43.16+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►5.61+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.extracted.112	miniqmc.cpp:397	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►2.09+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:218	exec
○	miniqmcreference::OneBodyJastr[...]	stl_vector.h:1169	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	BsplineFunctor.h:275-339
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:275-276,284-285,291-339

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 110.00 to 96.00 cycles (1.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions).

Details

54% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

44% of SSE/AVX loads are used in vector version.
93% of SSE/AVX stores are used in vector version.
88% of SSE/AVX multiply instructions are used in vector version.
31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 110.00 to 81.83 cycles (1.34x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 132 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:294
VCOMPRESSPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VPCOMPRESSD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VPMOVSXBD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:339

Vector unaligned load/store instructions

Detected 56 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 47 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:322
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:323
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:323
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:325
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:325
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:328
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:328
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:328
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:329
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:329
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:329
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:331
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:325
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:331
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:331
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:335
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
VMOVUPS: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:334
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:334
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:334

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VPMOVQD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VPMOVSXBD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 48 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 305 FP arithmetical operations:

136: addition or subtraction (132 inside FMA instructions)
165: multiply (132 inside FMA instructions)
4: divide

The binary function is loading 1896 bytes (237 double precision FP elements). The binary function is storing 1744 bytes (218 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	430
nb uops	491
loop length	2596
used x86 registers	16
used mmx registers	0
used xmm registers	30
used ymm registers	32
used zmm registers	0
nb stack references	38
ADD-SUB / MUL ratio	0.11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	81.83 cycles
front end	81.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	48.67	48.33	42.33	42.33	40.00	110.00	14.00	40.00	40.00	40.00	14.00	42.33
cycles	48.67	48.33	42.33	42.33	40.00	110.00	14.00	40.00	40.00	40.00	14.00	42.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

8.00

Cycles summary

Front-end	81.83
Dispatch	110.00
DIV/SQRT	8.00
Overall L1	110.00

Vectorization ratios

INT

all	44%
load	84%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	56%
load	38%
store	100%
mul	88%
add-sub	100%
fma	100%
div/sqrt	100%
other	30%

INT+FP

all	54%
load	44%
store	93%
mul	88%
add-sub	100%
fma	100%
div/sqrt	100%
other	31%

Vector efficiency ratios

INT

all	24%
load	36%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	32%
load	26%
store	45%
mul	45%
add-sub	50%
fma	50%
div/sqrt	50%
other	22%

INT+FP

all	30%
load	28%
store	43%
mul	45%
add-sub	50%
fma	50%
div/sqrt	50%
other	21%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 110.00 cycles. At this rate:

8% of peak load performance is reached (17.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41fba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x3e0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 420989 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xde9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x28(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0x238(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EDX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVSD 0x8(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %ECX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffff0,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 41fbf8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x58>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x7,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JA 41fc02 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x62>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fdc5 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x225>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fdac <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x20c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R9,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTD %ESI,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSD %XMM1,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %EDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R8,%R12,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBD 0xde693(%RIP),%YMM4	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0xde692(%RIP),%YMM5	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x100(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 41ffab <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x40b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %R15,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVD %R14D,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPSUBQ %YMM2,%YMM3,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VMOVQ %XMM3,%RCX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP $0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 41fdfe <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x25e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R8,%R12,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fddc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x23c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %XMM3,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPNLEUQ 0xde5d2(%RIP),%YMM3,%K2																vect (50.0%)
VPCMPNLEUQ 0xde5e7(%RIP),%YMM3,%K3																vect (50.0%)
KSHIFTLB $0x4,%K3,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K0,%K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VPCMPNLEUQ 0xde5f2(%RIP),%YMM3,%K4																vect (50.0%)
VPCMPNLEUQ 0xde607(%RIP),%YMM3,%K5																vect (50.0%)
KSHIFTLB $0x4,%K5,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
ADD %R12,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD 0x60(%R8,%R14,8),%YMM3{%K5}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R8,%R14,8),%YMM4{%K4}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KORB %K0,%K4,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K0,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
VMOVUPD 0x20(%R8,%R14,8),%YMM5{%K3}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R8,%R14,8),%YMM6{%K2}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPBROADCASTD %EDX,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPMOVQD %YMM2,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %XMM2,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPOR 0xde61c(%RIP),%YMM2,%YMM8	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPOR 0xde634(%RIP),%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD %YMM2,%YMM7,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM7,%YMM8,%YMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTD %ESI,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPCMPNEQD %YMM10,%YMM7,%K3																vect (50.0%)
VPCMPNEQD %YMM10,%YMM9,%K4																vect (50.0%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VCMPPD $0x1,%YMM1,%YMM6,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM1,%YMM5,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K5,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K5,%K2,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VCMPPD $0x1,%YMM1,%YMM4,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM1,%YMM3,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K6,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K6,%K5,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOVSXD %EBX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R11,%RCX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KANDB %K3,%K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDB %K2,%K6,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VPCOMPRESSD %YMM8,(%R11,%RCX,4){%K6}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KANDB %K4,%K0,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDB %K5,%K7,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVB %K6,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
POPCNT %EDX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPCOMPRESSD %YMM2,(%RAX,%RDX,4){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
LEA (%R10,%RCX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCOMPRESSPD %YMM4,(%RAX,%RDX,8){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
VCOMPRESSPD %YMM6,(%R10,%RCX,8){%K6}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KSHIFTLB $0x4,%K7,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTRB $0x4,%K0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVB %K0,0x1d(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
LEA (%RAX,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KSHIFTRB $0x4,%K7,%K7	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
MOVZX 0x1d(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %ESI,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM3,(%RDX,%RSI,8){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KUNPCKBW %K3,%K4,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTLB $0x4,%K6,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTRB $0x4,%K3,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVB %K3,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KSHIFTRB $0x4,%K6,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
MOVZX 0x1c(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %EDX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM5,(%RAX,%RDX,8){%K3}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KUNPCKBW %K2,%K5,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW 0x20(%RSP),%K3	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
KUNPCKBW %K1,%K3,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KANDW %K0,%K3,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDW %K0,%K3,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDW %K2,%K0,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %EBX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
POPCNT %EAX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVD %ECX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VINSERTI32X4 $0,%XMM2,%YMM0,%YMM1{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVD %XMM1,%EBX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 420989 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xde9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x218(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x128(%RDI),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ 0x130(%RDI),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x148(%RDI),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x150(%RDI),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x168(%RDI),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x170(%RDI),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x188(%RDI),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x190(%RDI),%XMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa0(%RDI),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa8(%RDI),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0(%RDI),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc0(%RDI),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc8(%RDI),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd0(%RDI),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe0(%RDI),%XMM30	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xf0(%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x100(%RDI),%XMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x108(%RDI),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x110(%RDI),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%RDI),%XMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x20(%RDI),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x28(%RDI),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x30(%RDI),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x38(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x40(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x48(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x50(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x58(%RDI),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x60(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x68(%RDI),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x78(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x80(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x88(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x90(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM0,%XMM0,%XMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $0x7ffffffc,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 42063c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VBROADCASTSD %XMM0,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM13,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x260(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VPBROADCASTQ %XMM7,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x300(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM14,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x240(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM16,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x3a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM12,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM2,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM31,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x380(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM17,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM22,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM21,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x2e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM10,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x340(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM9,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM6,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x2a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM11,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x360(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM30,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM5,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x320(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM20,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM19,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM23,%YMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM18,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM25,%YMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM24,%YMM27	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM28,%YMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x40(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x60(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x80(%RSP),%YMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xa0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM26,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x190(%RSP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM8,%YMM30	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x150(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x160(%RSP),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x170(%RSP),%YMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x180(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R12,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %YMM14,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM13,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %YMM31,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM27,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD 0x340(%RSP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x360(%RSP),%YMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x320(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x3a0(%RSP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x380(%RSP),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
CMP %EBX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 420989 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xde9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPD %YMM10,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM29,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM26,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPBROADCASTQ %RBX,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM27,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD %YMM9,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM31,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD %YMM2,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM17,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD %YMM18,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM20,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM21,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVDQU 0x300(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x2e0(%RSP),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x2c0(%RSP),%YMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x2a0(%RSP),%YMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x280(%RSP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x260(%RSP),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x240(%RSP),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
JMP 4207cb <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xc2b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM28,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM13,%YMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %XMM7,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM14,%YMM27	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM16,%YMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM15,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM3,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM12,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM3,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM2,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM2,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM26,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM31,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM17,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM2,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM22,%YMM31	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM21,%YMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM10,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM9,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM11,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM30,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM2,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM5,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM20,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM19,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM23,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM18,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM25,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM24,%YMM24	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x40(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPS %YMM1,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x60(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPS %YMM1,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x80(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPS %YMM1,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0xa0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM12,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x190(%RSP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM2,%YMM30	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM16,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VBROADCASTSD 0x150(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x160(%RSP),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x170(%RSP),%YMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x180(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RBX,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R8,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM1,%YMM10,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ 0xddc00(%RIP),%YMM1,%K1																vect (50.0%)
VMOVUPD (%R10,%R8,8),%YMM10{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMULPD %YMM0,%YMM10,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCVTTPD2DQ %YMM1,%XMM18	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD (%RSI,%XMM18,8),%YMM20{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x8(%RSI,%XMM18,8),%YMM2{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VROUNDPD $0xb,%YMM1,%YMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM6,%YMM1,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM17,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM17,%YMM29	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM13,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM1,%YMM2,%YMM29	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM17,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM17,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM1,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM16,%YMM17,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM3,%YMM2,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x1e0(%RSP),%YMM3,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x200(%RSP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM17,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x40(%RSP),%YMM3,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x60(%RSP),%YMM1,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x80(%RSP),%YMM17,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM4,%YMM2,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPD 0x10(%RSI,%XMM18,8),%YMM2{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVUPD 0x120(%RSP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD 0xc0(%RSP),%YMM17,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM29,%YMM2,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x1c0(%RSP),%YMM1,%YMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x1a0(%RSP),%YMM17,%YMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM7,%YMM2,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0xa0(%RSP),%YMM3,%YMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM1,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM30,%YMM17,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM14,%YMM2,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM11,%YMM3,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPD 0x18(%RSI,%XMM18,8),%YMM2{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VFMADD231PD 0x100(%RSP),%YMM17,%YMM26	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM4,%YMM2,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%RSP),%YMM26,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVDQU32 (%R11,%R8,4),%XMM4{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %YMM4,%YMM22,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VSCATTERQPD %YMM3,(%RDX,%YMM22,8){%K2}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VFMADD231PD 0xe0(%RSP),%YMM1,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM1,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x220(%RSP),%YMM17,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM17,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM2,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM10,%YMM0,%YMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VSCATTERQPD %YMM0,(%RCX,%YMM22,8){%K2}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VFMADD213PD %YMM12,%YMM2,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSCATTERQPD %YMM15,(%R9,%YMM22,8){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	BsplineFunctor.h:275-339
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:275-276,284-285,291-339

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions).

Details

54% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

44% of SSE/AVX loads are used in vector version.
93% of SSE/AVX stores are used in vector version.
88% of SSE/AVX multiply instructions are used in vector version.
31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 132 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:294
VCOMPRESSPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VPCOMPRESSD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VPMOVSXBD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:339

Vector unaligned load/store instructions

Detected 56 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 47 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:322
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:323
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:323
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:325
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:325
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:328
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:328
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:328
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:329
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:329
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:329
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:331
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:338
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:325
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:331
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:331
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:335
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
VMOVUPS: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:324
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:330
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:334
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:334
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:334

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VPMOVQD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
VPMOVSXBD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 305 FP arithmetical operations:

136: addition or subtraction (132 inside FMA instructions)
165: multiply (132 inside FMA instructions)
4: divide

The binary function is loading 1896 bytes (237 double precision FP elements). The binary function is storing 1744 bytes (218 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	430
nb uops	491
loop length	2596
used x86 registers	16
used mmx registers	0
used xmm registers	30
used ymm registers	32
used zmm registers	0
nb stack references	38
ADD-SUB / MUL ratio	0.11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	81.83 cycles
front end	81.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	48.67	48.33	42.33	42.33	40.00	110.00	14.00	40.00	40.00	40.00	14.00	42.33
cycles	48.67	48.33	42.33	42.33	40.00	110.00	14.00	40.00	40.00	40.00	14.00	42.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

8.00

Cycles summary

Front-end	81.83
Dispatch	110.00
DIV/SQRT	8.00
Overall L1	110.00

Vectorization ratios

INT

all	44%
load	84%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	56%
load	38%
store	100%
mul	88%
add-sub	100%
fma	100%
div/sqrt	100%
other	30%

INT+FP

all	54%
load	44%
store	93%
mul	88%
add-sub	100%
fma	100%
div/sqrt	100%
other	31%

Vector efficiency ratios

INT

all	24%
load	36%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	32%
load	26%
store	45%
mul	45%
add-sub	50%
fma	50%
div/sqrt	50%
other	22%

INT+FP

all	30%
load	28%
store	43%
mul	45%
add-sub	50%
fma	50%
div/sqrt	50%
other	21%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 110.00 cycles. At this rate:

8% of peak load performance is reached (17.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41fba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x3e0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 420989 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xde9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x28(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0x238(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EDX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVSD 0x8(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %ECX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffff0,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 41fbf8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x58>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x7,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JA 41fc02 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x62>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fdc5 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x225>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fdac <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x20c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R9,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTD %ESI,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSD %XMM1,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %EDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R8,%R12,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPMOVSXBD 0xde693(%RIP),%YMM4	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0xde692(%RIP),%YMM5	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x100(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 41ffab <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x40b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %R15,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVD %R14D,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPSUBQ %YMM2,%YMM3,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VMOVQ %XMM3,%RCX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP $0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 41fdfe <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x25e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R8,%R12,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fddc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x23c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %XMM3,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPNLEUQ 0xde5d2(%RIP),%YMM3,%K2																vect (50.0%)
VPCMPNLEUQ 0xde5e7(%RIP),%YMM3,%K3																vect (50.0%)
KSHIFTLB $0x4,%K3,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K0,%K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VPCMPNLEUQ 0xde5f2(%RIP),%YMM3,%K4																vect (50.0%)
VPCMPNLEUQ 0xde607(%RIP),%YMM3,%K5																vect (50.0%)
KSHIFTLB $0x4,%K5,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
ADD %R12,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD 0x60(%R8,%R14,8),%YMM3{%K5}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R8,%R14,8),%YMM4{%K4}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KORB %K0,%K4,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K0,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
VMOVUPD 0x20(%R8,%R14,8),%YMM5{%K3}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%R8,%R14,8),%YMM6{%K2}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPBROADCASTD %EDX,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPMOVQD %YMM2,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %XMM2,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPOR 0xde61c(%RIP),%YMM2,%YMM8	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPOR 0xde634(%RIP),%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD %YMM2,%YMM7,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM7,%YMM8,%YMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTD %ESI,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPCMPNEQD %YMM10,%YMM7,%K3																vect (50.0%)
VPCMPNEQD %YMM10,%YMM9,%K4																vect (50.0%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VCMPPD $0x1,%YMM1,%YMM6,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM1,%YMM5,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K5,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K5,%K2,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VCMPPD $0x1,%YMM1,%YMM4,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VCMPPD $0x1,%YMM1,%YMM3,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KSHIFTLB $0x4,%K6,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K6,%K5,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
MOVSXD %EBX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R11,%RCX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KANDB %K3,%K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDB %K2,%K6,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VPCOMPRESSD %YMM8,(%R11,%RCX,4){%K6}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KANDB %K4,%K0,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDB %K5,%K7,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVB %K6,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
POPCNT %EDX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPCOMPRESSD %YMM2,(%RAX,%RDX,4){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
LEA (%R10,%RCX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCOMPRESSPD %YMM4,(%RAX,%RDX,8){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
VCOMPRESSPD %YMM6,(%R10,%RCX,8){%K6}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KSHIFTLB $0x4,%K7,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTRB $0x4,%K0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVB %K0,0x1d(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
LEA (%RAX,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KSHIFTRB $0x4,%K7,%K7	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
MOVZX 0x1d(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %ESI,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM3,(%RDX,%RSI,8){%K7}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KUNPCKBW %K3,%K4,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTLB $0x4,%K6,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KSHIFTRB $0x4,%K3,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVB %K3,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
KSHIFTRB $0x4,%K6,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
MOVZX 0x1c(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
POPCNT %EDX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCOMPRESSPD %YMM5,(%RAX,%RDX,8){%K3}	3	0	0	0	0	0.50	2	0	0.50	0.50	0.50	0	0	3	2	vect (50.0%)
KUNPCKBW %K2,%K5,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW 0x20(%RSP),%K3	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
KUNPCKBW %K1,%K3,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KANDW %K0,%K3,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDW %K0,%K3,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KANDW %K2,%K0,%K0	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %EBX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
POPCNT %EAX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVD %ECX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VINSERTI32X4 $0,%XMM2,%YMM0,%YMM1{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVD %XMM1,%EBX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 420989 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xde9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x218(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x128(%RDI),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ 0x130(%RDI),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x148(%RDI),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x150(%RDI),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x168(%RDI),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x170(%RDI),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x188(%RDI),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x190(%RDI),%XMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa0(%RDI),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa8(%RDI),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0(%RDI),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc0(%RDI),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc8(%RDI),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd0(%RDI),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe0(%RDI),%XMM30	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xf0(%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x100(%RDI),%XMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x108(%RDI),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x110(%RDI),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%RDI),%XMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x20(%RDI),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x28(%RDI),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x30(%RDI),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x38(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x40(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x48(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x50(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x58(%RDI),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x60(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM3,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x68(%RDI),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x78(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x80(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x88(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x90(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM4,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM0,%XMM0,%XMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $0x7ffffffc,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 42063c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VBROADCASTSD %XMM0,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM13,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x260(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VPBROADCASTQ %XMM7,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x300(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM14,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x240(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM16,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x3a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM12,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM2,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM31,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x380(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM17,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM22,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM21,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x2e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM10,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x340(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM9,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM6,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x2a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM11,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x360(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM30,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM5,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0x320(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM20,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM19,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM23,%YMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM18,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM25,%YMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM24,%YMM27	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM28,%YMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x40(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x60(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x80(%RSP),%YMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0xa0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM26,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x190(%RSP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM8,%YMM30	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x150(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x160(%RSP),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x170(%RSP),%YMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x180(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R12,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %YMM14,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM13,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %YMM31,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM27,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD 0x340(%RSP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x360(%RSP),%YMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x320(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x3a0(%RSP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x380(%RSP),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
CMP %EBX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 420989 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xde9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPD %YMM10,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM29,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM26,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPBROADCASTQ %RBX,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM27,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD %YMM9,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM31,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD %YMM2,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM17,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD %YMM18,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM20,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM21,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVDQU 0x300(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x2e0(%RSP),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x2c0(%RSP),%YMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x2a0(%RSP),%YMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x280(%RSP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x260(%RSP),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x240(%RSP),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
JMP 4207cb <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xc2b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM28,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM13,%YMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %XMM7,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM14,%YMM27	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM16,%YMM29	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM15,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM3,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM12,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM3,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM2,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM2,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM26,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM31,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM17,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM2,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM22,%YMM31	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM21,%YMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM10,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM9,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM11,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM30,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPS %YMM2,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM5,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM20,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM19,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM23,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM18,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM25,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD %XMM24,%YMM24	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD 0x40(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPS %YMM1,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x60(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPS %YMM1,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x80(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPS %YMM1,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0xa0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM12,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM1,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x190(%RSP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD %XMM2,%YMM30	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM16,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VBROADCASTSD 0x150(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x160(%RSP),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x170(%RSP),%YMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD 0x180(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RBX,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R8,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM1,%YMM10,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ 0xddc00(%RIP),%YMM1,%K1																vect (50.0%)
VMOVUPD (%R10,%R8,8),%YMM10{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMULPD %YMM0,%YMM10,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCVTTPD2DQ %YMM1,%XMM18	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD (%RSI,%XMM18,8),%YMM20{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x8(%RSI,%XMM18,8),%YMM2{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VROUNDPD $0xb,%YMM1,%YMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM6,%YMM1,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM17,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM17,%YMM29	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM13,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM1,%YMM2,%YMM29	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM17,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM17,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM1,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM16,%YMM17,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM3,%YMM2,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x1e0(%RSP),%YMM3,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x200(%RSP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM17,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM4,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x40(%RSP),%YMM3,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x60(%RSP),%YMM1,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x80(%RSP),%YMM17,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM4,%YMM2,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPD 0x10(%RSI,%XMM18,8),%YMM2{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVUPD 0x120(%RSP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD 0xc0(%RSP),%YMM17,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM29,%YMM2,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x1c0(%RSP),%YMM1,%YMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x1a0(%RSP),%YMM17,%YMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM7,%YMM2,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0xa0(%RSP),%YMM3,%YMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM1,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM30,%YMM17,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM14,%YMM2,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM11,%YMM3,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPD 0x18(%RSI,%XMM18,8),%YMM2{%K2}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VFMADD231PD 0x100(%RSP),%YMM17,%YMM26	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD %YMM4,%YMM2,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%RSP),%YMM26,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVDQU32 (%R11,%R8,4),%XMM4{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %YMM4,%YMM22,%YMM22{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VSCATTERQPD %YMM3,(%RDX,%YMM22,8){%K2}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VFMADD231PD 0xe0(%RSP),%YMM1,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM1,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x220(%RSP),%YMM17,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM17,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM2,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM10,%YMM0,%YMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VSCATTERQPD %YMM0,(%RCX,%YMM22,8){%K2}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VFMADD213PD %YMM12,%YMM2,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSCATTERQPD %YMM15,(%R9,%YMM22,8){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const–	0.52	0.45
○Loop 348 - BsplineFunctor.h:291-297 - exec	0.45	0.38
○Loop 346 - BsplineFunctor.h:303-338 - exec	0.05	0.04
○Loop 347 - BsplineFunctor.h:291-298 - exec	0.00	0.00

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ASM code

Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code