OV - exec - Function qmcplusplus::Vector<double, std::allocator<double> >::resize(unsigned long, double)

	Function: qmcplusplus::Vector<double, std::allocator<double> >::resize(unsigned long, double)	Module: exec	Source: OhmmsVector.h:182-302 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 111 - 147

--------------------------------------------------------------------------------

111: 	if (__builtin_expect(__n > this->_M_max_size(), false))

112: 	  {

113: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

114: 	    // 3190. allocator::allocate sometimes returns too little storage

115: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

116: 	      std::__throw_bad_array_new_length();

117: 	    std::__throw_bad_alloc();

[...]

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

146: #if __cpp_sized_deallocation

147: 			  , __t * sizeof(_Tp)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 924

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 182 - 302

--------------------------------------------------------------------------------

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

302:     nAllocated = n;

0x41eef0 PUSH	%RBP

0x41eef1 MOV	%RSP,%RBP

0x41eef4 PUSH	%R14

0x41eef6 PUSH	%RBX

0x41eef7 SUB	$0x10,%RSP

0x41eefb MOV	%RSI,%RBX

0x41eefe MOV	0x8(%RDI),%RAX

0x41ef02 MOV	0x10(%RDI),%RSI

0x41ef06 CMP	%RSI,%RAX

0x41ef09 JA	41f023

0x41ef0f MOV	%RDI,%R14

0x41ef12 CMP	%RBX,%RSI

0x41ef15 JAE	41ef93

0x41ef17 TEST	%RSI,%RSI

0x41ef1a VMOVUPS	%XMM0,-0x20(%RBP)

0x41ef1f JE	41ef2e

0x41ef21 MOV	0x18(%R14),%RDI

0x41ef25 SAL	$0x3,%RSI

0x41ef29 CALL	404070 <_ZdlPvm@plt>

0x41ef2e MOV	%RBX,%RAX

0x41ef31 SHR	$0x3c,%RAX

0x41ef35 JNE	41f013

0x41ef3b LEA	(,%RBX,8),%RDI

0x41ef43 CALL	404450 <_Znwm@plt>

0x41ef48 MOV	%RAX,0x18(%R14)

0x41ef4c MOV	%RBX,0x8(%R14)

0x41ef50 MOV	%RBX,0x10(%R14)

0x41ef54 LEA	-0x8(,%RBX,8),%RCX

0x41ef5c SHR	$0x3,%RCX

0x41ef60 INC	%RCX

0x41ef63 MOV	$0x3ffffffffffffffc,%RDX

0x41ef6d AND	%RCX,%RDX

0x41ef70 JE	41efe6

0x41ef72 VMOVUPS	-0x20(%RBP),%XMM1

0x41ef77 VBROADCASTSD	%XMM1,%YMM0

0x41ef7c XOR	%ESI,%ESI

0x41ef7e XCHG	%AX,%AX

(333) 0x41ef80 VMOVUPS	%YMM0,(%RAX,%RSI,8)

(333) 0x41ef85 ADD	$0x4,%RSI

(333) 0x41ef89 CMP	%RDX,%RSI

(333) 0x41ef8c JB	41ef80

0x41ef8e JMP	41f06e

0x41ef93 CMP	%RAX,%RBX

0x41ef96 JBE	41f00d

0x41ef98 MOV	0x18(%R14),%RDX

0x41ef9c MOV	%RAX,%RCX

0x41ef9f NOT	%RCX

0x41efa2 ADD	%RBX,%RCX

0x41efa5 MOV	$0x3d,%SIL

0x41efa8 BZHI	%RSI,%RCX,%RCX

0x41efad INC	%RCX

0x41efb0 MOV	$0x3ffffffffffffffc,%RSI

0x41efba AND	%RCX,%RSI

0x41efbd JE	41eff2

0x41efbf VBROADCASTSD	%XMM0,%YMM1

0x41efc4 LEA	(%RDX,%RAX,8),%RDI

0x41efc8 XOR	%R8D,%R8D

0x41efcb NOPL	(%RAX,%RAX,1)

(331) 0x41efd0 VMOVUPS	%YMM1,(%RDI,%R8,8)

(331) 0x41efd6 ADD	$0x4,%R8

(331) 0x41efda CMP	%RSI,%R8

(331) 0x41efdd JB	41efd0

0x41efdf CMP	%RSI,%RCX

0x41efe2 JNE	41eff4

0x41efe4 JMP	41f00d

0x41efe6 XOR	%EDX,%EDX

0x41efe8 VMOVUPS	-0x20(%RBP),%XMM1

0x41efed JMP	41f073

0x41eff2 XOR	%ESI,%ESI

0x41eff4 LEA	(%RDX,%RAX,8),%RAX

0x41eff8 NOPL	(%RAX,%RAX,1)

(330) 0x41f000 VMOVSD	%XMM0,(%RAX,%RSI,8)

(330) 0x41f005 INC	%RSI

(330) 0x41f008 CMP	%RSI,%RCX

(330) 0x41f00b JNE	41f000

0x41f00d MOV	%RBX,0x8(%R14)

0x41f011 JMP	41f062

0x41f013 SHR	$0x3d,%RBX

0x41f017 JE	41f01e

0x41f019 CALL	404530 <_ZSt28__throw_bad_array_new_lengthv@plt>

0x41f01e CALL	404440 <_ZSt17__throw_bad_allocv@plt>

0x41f023 MOV	$0x10,%EDI

0x41f028 CALL	404510 <__cxa_allocate_exception@plt>

0x41f02d MOV	%RAX,%RBX

0x41f030 MOV	$0x4fe5fe,%ESI

0x41f035 MOV	%RAX,%RDI

0x41f038 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x41f03d MOV	$0x5657c0,%ESI

0x41f042 MOV	$0x404770,%EDX

0x41f047 MOV	%RBX,%RDI

0x41f04a CALL	404230 <__cxa_throw@plt>

0x41f04f MOV	%RAX,%R14

0x41f052 MOV	%RBX,%RDI

0x41f055 CALL	4047a0 <__cxa_free_exception@plt>

0x41f05a MOV	%R14,%RDI

0x41f05d CALL	404270 <_Unwind_Resume@plt>

0x41f062 ADD	$0x10,%RSP

0x41f066 POP	%RBX

0x41f067 POP	%R14

0x41f069 POP	%RBP

0x41f06a VZEROUPPER

0x41f06d RET

(332) 0x41f06e CMP	%RDX,%RCX

(332) 0x41f071 JE	41f062

(332) 0x41f073 VMOVSD	%XMM1,(%RAX,%RDX,8)

(332) 0x41f078 INC	%RDX

(332) 0x41f07b JMP	41f06e

0x41f07d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►19.14+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:101	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:80	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►17.58+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:70	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:80	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►17.22+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:104	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:80	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►16.03+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:101	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:81	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►15.75+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:70	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:81	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►13.74+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:104	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:81	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145-147
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.83 to 4.50 cycles (3.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

13% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_Unwind_Resume@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_allocate_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_free_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_throw@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
operator delete(void*, unsigned long): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
operator new(unsigned long): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127
std::__throw_bad_alloc(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:117
std::__throw_bad_array_new_length(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:116
std::runtime_error::runtime_error(char const*): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:199

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	91
nb uops	101
loop length	343
used x86 registers	10
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	6.40	3.33	3.33	8.50	6.20	7.00	8.50	8.50	8.50	6.40	3.33
cycles	7.00	6.40	3.33	3.33	8.50	6.20	7.00	8.50	8.50	8.50	6.40	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	8.50
Overall L1	16.83

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	60%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	66%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	13%
load	20%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.83 cycles. At this rate:

1% of peak load performance is reached (3.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.83 to 8.50 cycles (1.98x speedup).

ASM code

In the binary file, the address of the function is: 41eef0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41f023 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x133>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 41ef93 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xa3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
VMOVUPS %XMM0,-0x20(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JE 41ef2e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
CALL 404070 <_ZdlPvm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3c,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 41f013 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x123>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RBX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404450 <_Znwm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x18(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x10(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x8(,%RBX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x3ffffffffffffffc,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 41efe6 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xf6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS -0x20(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41f06e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x17e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 41f00d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x11d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOT %RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x3d,%SIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
BZHI %RSI,%RCX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x3ffffffffffffffc,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
JE 41eff2 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x102>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 41eff4 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x104>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 41f00d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x11d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPS -0x20(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 41f073 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x183>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,0x8(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 41f062 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x172>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
SHR $0x3d,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 41f01e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x12e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CALL 404530 <_ZSt28__throw_bad_array_new_lengthv@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 404440 <_ZSt17__throw_bad_allocv@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404510 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x4fe5fe,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x5657c0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x404770,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404230 <__cxa_throw@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4047a0 <__cxa_free_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404270 <_Unwind_Resume@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145-147
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.83 to 4.50 cycles (3.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

13% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

_Unwind_Resume@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_allocate_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_free_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_throw@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
operator delete(void*, unsigned long): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
operator new(unsigned long): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127
std::__throw_bad_alloc(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:117
std::__throw_bad_array_new_length(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:116
std::runtime_error::runtime_error(char const*): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:199

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	91
nb uops	101
loop length	343
used x86 registers	10
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	6.40	3.33	3.33	8.50	6.20	7.00	8.50	8.50	8.50	6.40	3.33
cycles	7.00	6.40	3.33	3.33	8.50	6.20	7.00	8.50	8.50	8.50	6.40	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	8.50
Overall L1	16.83

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	60%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	66%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	13%
load	20%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.83 cycles. At this rate:

1% of peak load performance is reached (3.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41eef0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41f023 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x133>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 41ef93 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xa3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
VMOVUPS %XMM0,-0x20(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JE 41ef2e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
CALL 404070 <_ZdlPvm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3c,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 41f013 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x123>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RBX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404450 <_Znwm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x18(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x10(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x8(,%RBX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x3ffffffffffffffc,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 41efe6 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xf6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS -0x20(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41f06e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x17e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 41f00d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x11d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOT %RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x3d,%SIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
BZHI %RSI,%RCX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x3ffffffffffffffc,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
JE 41eff2 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x102>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 41eff4 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x104>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 41f00d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x11d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPS -0x20(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 41f073 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x183>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,0x8(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 41f062 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x172>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
SHR $0x3d,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 41f01e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x12e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CALL 404530 <_ZSt28__throw_bad_array_new_lengthv@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 404440 <_ZSt17__throw_bad_allocv@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404510 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x4fe5fe,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x5657c0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x404770,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404230 <__cxa_throw@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4047a0 <__cxa_free_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404270 <_Unwind_Resume@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::Vector >::resize(unsigned long, double)–	0.03	0.02
○Loop 333 - stl_algobase.h:923-924 - exec	0.03	0.02
○Loop 331 - stl_algobase.h:923-924 - exec	0.00	0.00
○Loop 332 - stl_algobase.h:923-924 - exec	0.00	0.00
○Loop 330 - stl_algobase.h:923-924 - exec	0.00	0.00

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512-bits vectorization

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Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code