OV - exec - Loop 927

	Loop Id: 927	Module: exec	Source: MultiBsplineRef.hpp:187-286 [...]	Coverage: 0.01%

0x450380 MOV	0xc0(%RSP),%RDX

0x450388 CMP	0x48(%RSP),%RDX

0x45038d LEA	0x1(%RDX),%RDX

0x450391 MOV	0xb8(%RSP),%R15

0x450399 MOV	0xb0(%RSP),%R12

0x4503a1 JE	451340

0x4503a7 LEA	(,%RDX,8),%RAX

0x4503af MOV	0xa0(%RSP),%RCX

0x4503b7 MOV	(%RCX,%RDX,8),%R10

0x4503bb MOV	%RDX,0xc0(%RSP)

0x4503c3 LEA	(%RDX,%RDX,2),%RCX

0x4503c7 MOV	0x98(%RSP),%RDX

0x4503cf MOV	(%RDX,%RCX,8),%R14

0x4503d3 LEA	(%RAX,%RAX,4),%RAX

0x4503d7 MOV	0x90(%RSP),%RCX

0x4503df MOV	0x18(%RCX,%RAX,1),%RCX

0x4503e4 MOV	%RCX,0x18(%RSP)

0x4503e9 VMOVUPD	0x1c0(%RSP),%XMM0

0x4503f2 VSUBSD	0x28(%R10),%XMM0,%XMM0

0x4503f8 MOV	0x88(%RSP),%RCX

0x450400 MOV	0x18(%RCX,%RAX,1),%RBX

0x450405 VMOVUPD	0x1b0(%RSP),%XMM1

0x45040e VSUBSD	0x50(%R10),%XMM1,%XMM1

0x450414 VMOVUPD	0x1a0(%RSP),%XMM2

0x45041d VSUBSD	0x78(%R10),%XMM2,%XMM2

0x450423 VMOVSD	0x48(%R10),%XMM3

0x450429 VMOVSD	0x70(%R10),%XMM4

0x45042f VMOVUPD	%XMM3,0x1f0(%RSP)

0x450438 VMULSD	%XMM0,%XMM3,%XMM0

0x45043c MOVSXD	0x38(%R10),%RAX

0x450440 MOV	%RAX,0x8(%RSP)

0x450445 VRNDSCALESD	$0x9,%XMM0,%XMM0,%XMM19

0x45044c VSUBSD	%XMM19,%XMM0,%XMM3

0x450452 VMOVUPD	%XMM4,0x1e0(%RSP)

0x45045b VMULSD	%XMM1,%XMM4,%XMM1

0x45045f MOVSXD	0x60(%R10),%R13

0x450463 VRNDSCALESD	$0x9,%XMM1,%XMM1,%XMM25

0x45046a VMOVSD	0x98(%R10),%XMM0

0x450473 VMOVUPD	%XMM0,0x1d0(%RSP)

0x45047c VMULSD	%XMM2,%XMM0,%XMM0

0x450480 MOVSXD	0x88(%R10),%RAX

0x450487 MOV	%RAX,0x20(%RSP)

0x45048c VRNDSCALESD	$0x9,%XMM0,%XMM0,%XMM20

0x450493 VMULSD	%XMM16,%XMM3,%XMM2

0x450499 VSUBSD	%XMM2,%XMM22,%XMM4

0x45049f VMULSD	%XMM3,%XMM3,%XMM5

0x4504a3 VMOVDDUP	%XMM3,%XMM6

0x4504a7 VMOVUPD	0x190(%RSP),%XMM8

0x4504b0 VBLENDPD	$0x1,%XMM4,%XMM8,%XMM4

0x4504b6 VMULPD	%XMM4,%XMM6,%XMM4

0x4504ba VMOVUPD	0xe99ae(%RIP),%XMM9

0x4504c2 VADDPD	%XMM4,%XMM9,%XMM7

0x4504c6 VPUNPCKLQDQ	%XMM5,%XMM6,%XMM6

0x4504ca VMOVUPD	0xe99ae(%RIP),%XMM10

0x4504d2 VFMADD213PD	%XMM10,%XMM7,%XMM6

0x4504d7 VMOVUPD	%XMM6,0x2e0(%RSP)

0x4504e0 VMULSD	%XMM23,%XMM3,%XMM6

0x4504e6 VADDSD	%XMM22,%XMM6,%XMM7

0x4504ec VFMADD213SD	%XMM22,%XMM3,%XMM7

0x4504f2 VFMADD213SD	%XMM16,%XMM3,%XMM7

0x4504f8 VMOVSD	%XMM7,0x2f0(%RSP)

0x450501 VMULSD	%XMM5,%XMM2,%XMM2

0x450505 VMOVSD	%XMM2,0x2f8(%RSP)

0x45050e VADDSD	%XMM24,%XMM6,%XMM2

0x450514 VFMADD213SD	%XMM23,%XMM3,%XMM2

0x45051a VMOVSD	%XMM2,0x160(%RSP)

0x450523 VMULSD	%XMM26,%XMM3,%XMM2

0x450529 VADDSD	%XMM27,%XMM2,%XMM5

0x45052f VMULSD	%XMM3,%XMM5,%XMM5

0x450533 VMOVSD	%XMM5,0x168(%RSP)

0x45053c VSUBSD	%XMM2,%XMM24,%XMM2

0x450542 VFMADD213SD	%XMM22,%XMM3,%XMM2

0x450548 VMOVSD	%XMM2,0x170(%RSP)

0x450551 VSHUFPD	$0x1,%XMM4,%XMM4,%XMM2

0x450556 VMULSD	%XMM3,%XMM2,%XMM2

0x45055a VMOVSD	%XMM2,0x178(%RSP)

0x450563 VMULSD	%XMM28,%XMM3,%XMM2

0x450569 VMOVDDUP	%XMM2,%XMM4

0x45056d VSUBSD	%XMM3,%XMM24,%XMM5

0x450573 VMOVUPD	0x180(%RSP),%XMM7

0x45057c VADDSD	%XMM7,%XMM4,%XMM4

0x450580 VMOVDDUP	%XMM4,%XMM4

0x450584 VBLENDPD	$0x1,%XMM5,%XMM4,%XMM4

0x45058a VMOVUPD	%XMM4,0x2a0(%RSP)

0x450593 VSUBSD	%XMM25,%XMM1,%XMM1

0x450599 VSUBSD	%XMM2,%XMM24,%XMM2

0x45059f VMOVSD	%XMM2,0x2b0(%RSP)

0x4505a8 VMOVSD	%XMM3,0x2b8(%RSP)

0x4505b1 VMULSD	%XMM16,%XMM1,%XMM2

0x4505b7 VSUBSD	%XMM2,%XMM22,%XMM3

0x4505bd VMULSD	%XMM1,%XMM1,%XMM4

0x4505c1 VMOVDDUP	%XMM1,%XMM5

0x4505c5 VBLENDPD	$0x1,%XMM3,%XMM8,%XMM3

0x4505cb VMULPD	%XMM3,%XMM5,%XMM3

0x4505cf VADDPD	%XMM3,%XMM9,%XMM6

0x4505d3 VPUNPCKLQDQ	%XMM4,%XMM5,%XMM5

0x4505d7 VFMADD213PD	%XMM10,%XMM6,%XMM5

0x4505dc VMOVUPD	%XMM5,0x2c0(%RSP)

0x4505e5 VMULSD	%XMM23,%XMM1,%XMM5

0x4505eb VADDSD	%XMM22,%XMM5,%XMM6

0x4505f1 VFMADD213SD	%XMM22,%XMM1,%XMM6

0x4505f7 VFMADD213SD	%XMM16,%XMM1,%XMM6

0x4505fd VMOVSD	%XMM6,0x2d0(%RSP)

0x450606 VMULSD	%XMM4,%XMM2,%XMM2

0x45060a VMOVSD	%XMM2,0x2d8(%RSP)

0x450613 VADDSD	%XMM24,%XMM5,%XMM2

0x450619 VFMADD213SD	%XMM23,%XMM1,%XMM2

0x45061f VMOVSD	%XMM2,0x140(%RSP)

0x450628 VMULSD	%XMM26,%XMM1,%XMM2

0x45062e VADDSD	%XMM27,%XMM2,%XMM4

0x450634 VMULSD	%XMM1,%XMM4,%XMM4

0x450638 VMOVSD	%XMM4,0x148(%RSP)

0x450641 VSUBSD	%XMM20,%XMM0,%XMM21

0x450647 VSUBSD	%XMM2,%XMM24,%XMM0

0x45064d VFMADD213SD	%XMM22,%XMM1,%XMM0

0x450653 VMOVSD	%XMM0,0x150(%RSP)

0x45065c VSHUFPD	$0x1,%XMM3,%XMM3,%XMM0

0x450661 VMULSD	%XMM1,%XMM0,%XMM0

0x450665 VMOVSD	%XMM0,0x158(%RSP)

0x45066e VMULSD	%XMM28,%XMM1,%XMM0

0x450674 VMOVDDUP	%XMM0,%XMM2

0x450678 VSUBSD	%XMM1,%XMM24,%XMM3

0x45067e VADDSD	%XMM7,%XMM2,%XMM2

0x450682 VMOVDDUP	%XMM2,%XMM2

0x450686 VBLENDPD	$0x1,%XMM3,%XMM2,%XMM2

0x45068c VMOVUPD	%XMM2,0x280(%RSP)

0x450695 VSUBSD	%XMM0,%XMM24,%XMM0

0x45069b VMOVSD	%XMM0,0x290(%RSP)

0x4506a4 VMOVSD	%XMM1,0x298(%RSP)

0x4506ad VMULSD	%XMM21,%XMM21,%XMM17

0x4506b3 VMULSD	%XMM23,%XMM21,%XMM18

0x4506b9 VADDSD	%XMM22,%XMM18,%XMM0

0x4506bf VMOVDDUP	0xe6959(%RIP),%XMM1

0x4506c7 VPUNPCKLQDQ	%XMM0,%XMM1,%XMM0

0x4506cb VMOVDDUP	%XMM21,%XMM1

0x4506d1 VMULPD	%XMM0,%XMM1,%XMM15

0x4506d5 VADDPD	0xe97c3(%RIP),%XMM15,%XMM0

0x4506dd VPUNPCKLQDQ	%XMM1,%XMM17,%XMM1

0x4506e3 VFMADD213PD	0xe97c4(%RIP),%XMM0,%XMM1

0x4506ec VMOVUPD	%YMM1,0x300(%RSP)

0x4506f5 MOV	0x10(%R10),%RAX

0x4506f9 MOV	%RAX,0x38(%RSP)

0x4506fe MOV	0x18(%R10),%RAX

0x450702 MOV	%RAX,0x40(%RSP)

0x450707 MOV	0x20(%R10),%RAX

0x45070b MOV	%RAX,0x10(%RSP)

0x450710 MOVSXD	0xe8(%R10),%RAX

0x450717 MOV	0x80(%RSP),%R15

0x45071f TEST	%R15,%R15

0x450722 MOV	%RAX,(%RSP)

0x450726 VMOVUPD	%XMM15,0x130(%RSP)

0x45072f JE	450805

0x450735 MOV	%R14,%RDI

0x450738 XOR	%ESI,%ESI

0x45073a MOV	%R15,%RDX

0x45073d MOV	%R10,0x28(%RSP)

0x450742 VZEROUPPER

0x450745 CALL	534740 <__intel_avx_rep_memset>

0x45074a MOV	0x18(%RSP),%R12

0x45074f MOV	%R12,%RDI

0x450752 XOR	%ESI,%ESI

0x450754 MOV	%R15,%RDX

0x450757 CALL	534740 <__intel_avx_rep_memset>

0x45075c MOV	(%RSP),%RAX

0x450760 LEA	(%R12,%RAX,8),%RDI

0x450764 XOR	%ESI,%ESI

0x450766 MOV	%R15,%RDX

0x450769 CALL	534740 <__intel_avx_rep_memset>

0x45076e MOV	(%RSP),%RAX

0x450772 SAL	$0x4,%RAX

0x450776 LEA	(%R12,%RAX,1),%RDI

0x45077a MOV	%RAX,%R12

0x45077d XOR	%ESI,%ESI

0x45077f MOV	%R15,%RDX

0x450782 CALL	534740 <__intel_avx_rep_memset>

0x450787 MOV	%RBX,%RDI

0x45078a XOR	%ESI,%ESI

0x45078c MOV	%R15,%RDX

0x45078f CALL	534740 <__intel_avx_rep_memset>

0x450794 MOV	(%RSP),%RAX

0x450798 LEA	(%RBX,%RAX,8),%RDI

0x45079c XOR	%ESI,%ESI

0x45079e MOV	%R15,%RDX

0x4507a1 CALL	534740 <__intel_avx_rep_memset>

0x4507a6 ADD	%RBX,%R12

0x4507a9 MOV	%R12,%RDI

0x4507ac XOR	%ESI,%ESI

0x4507ae MOV	%R15,%RDX

0x4507b1 CALL	534740 <__intel_avx_rep_memset>

0x4507b6 MOV	(%RSP),%RAX

0x4507ba LEA	(%RAX,%RAX,2),%RAX

0x4507be LEA	(%RBX,%RAX,8),%RDI

0x4507c2 XOR	%ESI,%ESI

0x4507c4 MOV	%R15,%RDX

0x4507c7 CALL	534740 <__intel_avx_rep_memset>

0x4507cc MOV	(%RSP),%RDI

0x4507d0 SAL	$0x5,%RDI

0x4507d4 ADD	%RBX,%RDI

0x4507d7 XOR	%ESI,%ESI

0x4507d9 MOV	%R15,%RDX

0x4507dc CALL	534740 <__intel_avx_rep_memset>

0x4507e1 MOV	(%RSP),%RAX

0x4507e5 LEA	(%RAX,%RAX,4),%RAX

0x4507e9 LEA	(%RBX,%RAX,8),%RDI

0x4507ed XOR	%ESI,%ESI

0x4507ef MOV	%R15,%RDX

0x4507f2 CALL	534740 <__intel_avx_rep_memset>

0x4507f7 MOV	0x28(%RSP),%R10

0x4507fc VMOVUPD	0x130(%RSP),%XMM15

0x450805 VCVTTSD2SI	%XMM19,%ECX

0x45080b VCVTTSD2SI	%XMM25,%EDX

0x450811 VCVTTSD2SI	%XMM20,%EAX

0x450817 MOV	0x20(%RSP),%RDI

0x45081c DEC	%RDI

0x45081f MOV	%EAX,%ESI

0x450821 SAR	$0x1f,%ESI

0x450824 ANDN	%EAX,%ESI,%EAX

0x450829 CMP	%RAX,%RDI

0x45082c CMOVGE	%RAX,%RDI

0x450830 MOV	0x10(%RSP),%RSI

0x450835 MOV	%RSI,%RAX

0x450838 MOV	%RSI,%R9

0x45083b IMUL	%RDI,%RAX

0x45083f MOV	%RAX,0x20(%RSP)

0x450844 DEC	%R13

0x450847 MOV	%EDX,%ESI

0x450849 SAR	$0x1f,%ESI

0x45084c ANDN	%EDX,%ESI,%EDX

0x450851 CMP	%RDX,%R13

0x450854 CMOVGE	%RDX,%R13

0x450858 MOV	0x40(%RSP),%R8

0x45085d MOV	%R8,%RDX

0x450860 IMUL	%R13,%RDX

0x450864 MOV	0x8(%RSP),%RAX

0x450869 DEC	%RAX

0x45086c MOV	%ECX,%ESI

0x45086e SAR	$0x1f,%ESI

0x450871 ANDN	%ECX,%ESI,%ECX

0x450876 CMP	%RCX,%RAX

0x450879 CMOVGE	%RCX,%RAX

0x45087d MOV	0x38(%RSP),%RCX

0x450882 MOV	%RCX,%RSI

0x450885 IMUL	%RAX,%RSI

0x450889 ADD	%RDX,%RSI

0x45088c MOV	%RSI,0x8(%RSP)

0x450891 SAL	$0x3,%R8

0x450895 MOV	%R8,0x40(%RSP)

0x45089a IMUL	%R8,%R13

0x45089e SAL	$0x3,%RCX

0x4508a2 MOV	%RCX,0x38(%RSP)

0x4508a7 IMUL	%RCX,%RAX

0x4508ab LEA	(%R13,%RAX,1),%RCX

0x4508b0 LEA	(,%R9,8),%R11

0x4508b8 LEA	0x3(%RDI),%R9

0x4508bc LEA	0x2(%RDI),%R8

0x4508c0 MOV	%R11,%R15

0x4508c3 LEA	0x1(%RDI),%RDX

0x4508c7 MOV	%R11,%R12

0x4508ca IMUL	%R11,%RDI

0x4508ce IMUL	%R9,%R11

0x4508d2 ADD	%RCX,%R11

0x4508d5 IMUL	%R8,%R15

0x4508d9 ADD	%RCX,%R15

0x4508dc IMUL	%RDX,%R12

0x4508e0 ADD	%RCX,%R12

0x4508e3 VMULSD	%XMM16,%XMM21,%XMM7

0x4508e9 VSUBSD	%XMM7,%XMM22,%XMM0

0x4508ef VFMADD213SD	%XMM23,%XMM21,%XMM0

0x4508f5 VFMADD213SD	%XMM16,%XMM21,%XMM0

0x4508fb VADDSD	%XMM24,%XMM18,%XMM1

0x450901 VFMADD213SD	%XMM23,%XMM21,%XMM1

0x450907 VMULSD	%XMM26,%XMM21,%XMM3

0x45090d VADDSD	%XMM27,%XMM3,%XMM2

0x450913 VSUBSD	%XMM3,%XMM24,%XMM3

0x450919 VFMADD213SD	%XMM22,%XMM21,%XMM3

0x45091f VSUBSD	%XMM21,%XMM24,%XMM8

0x450925 VMULSD	%XMM28,%XMM21,%XMM6

0x45092b VADDSD	%XMM27,%XMM6,%XMM9

0x450931 VSUBSD	%XMM6,%XMM24,%XMM10

0x450937 MOV	0x8(%R10),%R10

0x45093b VMULSD	%XMM17,%XMM7,%XMM11

0x450941 VBROADCASTSD	%XMM0,%YMM19

0x450947 VMOVUPD	0x300(%RSP),%YMM16

0x45094f VBROADCASTSD	%XMM16,%YMM18

0x450955 VPERMPD	$0x55,%YMM16,%YMM22

0x45095c VBROADCASTSD	%XMM11,%YMM25

0x450962 VBROADCASTSD	%XMM1,%YMM26

0x450968 VBROADCASTSD	%XMM2,%YMM27

0x45096e VBROADCASTSD	%XMM3,%YMM28

0x450974 VBROADCASTSD	%XMM15,%YMM4

0x450979 VMOVUPD	%YMM4,0x380(%RSP)

0x450982 VMOVAPD	%XMM8,%XMM4

0x450986 VBROADCASTSD	%XMM21,%YMM17

0x45098c VBROADCASTSD	%XMM8,%YMM5

0x450991 VMOVUPD	%YMM5,0x360(%RSP)

0x45099a VMOVAPD	%XMM9,%XMM5

0x45099e VBROADCASTSD	%XMM9,%YMM6

0x4509a3 VMOVUPD	%YMM6,0x340(%RSP)

0x4509ac VMOVAPD	%XMM10,%XMM6

0x4509b0 VBROADCASTSD	%XMM10,%YMM7

0x4509b5 VMOVUPD	%YMM7,0x320(%RSP)

0x4509be VMOVAPD	%XMM11,%XMM7

0x4509c2 ADD	%RAX,%RDI

0x4509c5 MOV	(%RSP),%RAX

0x4509c9 MOV	%RAX,%RCX

0x4509cc SAL	$0x4,%RCX

0x4509d0 ADD	%R10,%R13

0x4509d3 ADD	%RDI,%R13

0x4509d6 MOV	%RCX,0x50(%RSP)

0x4509db MOV	0x18(%RSP),%RSI

0x4509e0 ADD	%RSI,%RCX

0x4509e3 MOV	0x10(%RSP),%RDI

0x4509e8 IMUL	%RDI,%R9

0x4509ec MOV	%R9,%RSI

0x4509ef IMUL	%RDI,%R8

0x4509f3 IMUL	%RDX,%RDI

0x4509f7 LEA	(,%RAX,8),%R9

0x4509ff MOV	0x8(%RSP),%RDX

0x450a04 ADD	%RDX,%RSI

0x450a07 ADD	%RDX,%R8

0x450a0a ADD	%RDX,%RDI

0x450a0d MOV	%RDI,0x10(%RSP)

0x450a12 ADD	0x20(%RSP),%RDX

0x450a17 MOV	%RDX,0x8(%RSP)

0x450a1c MOV	0x18(%RSP),%RDX

0x450a21 LEA	(%RDX,%RAX,8),%RDX

0x450a25 ADD	%R10,%R11

0x450a28 ADD	%R10,%R15

0x450a2b ADD	%R10,%R12

0x450a2e LEA	(%R10,%RSI,8),%RAX

0x450a32 MOV	%R11,%RDI

0x450a35 LEA	(%R10,%R8,8),%R11

0x450a39 MOV	0x10(%RSP),%RSI

0x450a3e LEA	(%R10,%RSI,8),%R8

0x450a42 MOV	0x8(%RSP),%RSI

0x450a47 LEA	(%R10,%RSI,8),%RSI

0x450a4b MOV	%RAX,%R10

0x450a4e XOR	%EAX,%EAX

0x450a50 VMOVUPD	%XMM1,0x270(%RSP)

0x450a59 VMOVUPD	%XMM0,0x260(%RSP)

0x450a62 VMOVUPD	%XMM2,0x250(%RSP)

0x450a6b VMOVUPD	%XMM3,0x240(%RSP)

0x450a74 VMOVUPD	%XMM8,0x230(%RSP)

0x450a7d VMOVUPD	%XMM9,0x220(%RSP)

0x450a86 VMOVUPD	%XMM10,0x210(%RSP)

0x450a8f VMOVUPD	%XMM11,0x200(%RSP)

0x450a98 JMP	450b33

  (930) 0x450ac0 MOV	0x38(%RSP),%RAX

  (930) 0x450ac5 MOV	0xf0(%RSP),%RDI

  (930) 0x450acd ADD	%RAX,%RDI

  (930) 0x450ad0 MOV	0x100(%RSP),%R15

  (930) 0x450ad8 ADD	%RAX,%R15

  (930) 0x450adb MOV	0xf8(%RSP),%R12

  (930) 0x450ae3 ADD	%RAX,%R12

  (930) 0x450ae6 MOV	0x108(%RSP),%R13

  (930) 0x450aee ADD	%RAX,%R13

  (930) 0x450af1 MOV	0xe8(%RSP),%R10

  (930) 0x450af9 ADD	%RAX,%R10

  (930) 0x450afc MOV	0xe0(%RSP),%R11

  (930) 0x450b04 ADD	%RAX,%R11

  (930) 0x450b07 MOV	0xd8(%RSP),%R8

  (930) 0x450b0f ADD	%RAX,%R8

  (930) 0x450b12 MOV	0xd0(%RSP),%RSI

  (930) 0x450b1a ADD	%RAX,%RSI

  (930) 0x450b1d MOV	0xc8(%RSP),%RAX

  (930) 0x450b25 CMP	$0x3,%RAX

  (930) 0x450b29 LEA	0x1(%RAX),%RAX

  (930) 0x450b2d JE	4510c0

  (930) 0x450b33 VMOVSD	0x2a0(%RSP,%RAX,8),%XMM8

  (930) 0x450b3c VMOVSD	%XMM8,0x120(%RSP)

  (930) 0x450b45 VMOVSD	0x160(%RSP,%RAX,8),%XMM8

  (930) 0x450b4e VMOVSD	%XMM8,0x118(%RSP)

  (930) 0x450b57 MOV	%RAX,0xc8(%RSP)

  (930) 0x450b5f VMOVSD	0x2e0(%RSP,%RAX,8),%XMM8

  (930) 0x450b68 VMOVSD	%XMM8,0x110(%RSP)

  (930) 0x450b71 MOV	%RSI,0xd0(%RSP)

  (930) 0x450b79 MOV	%R8,0xd8(%RSP)

  (930) 0x450b81 MOV	%R8,0x8(%RSP)

  (930) 0x450b86 MOV	%R11,0xe0(%RSP)

  (930) 0x450b8e MOV	%R10,0xe8(%RSP)

  (930) 0x450b96 MOV	%R13,0x108(%RSP)

  (930) 0x450b9e MOV	%R12,0xf8(%RSP)

  (930) 0x450ba6 MOV	%R15,0x100(%RSP)

  (930) 0x450bae MOV	%R15,%R8

  (930) 0x450bb1 MOV	%R12,%R15

  (930) 0x450bb4 MOV	%R8,%R12

  (930) 0x450bb7 MOV	%RDI,0xf0(%RSP)

  (930) 0x450bbf MOV	%RDI,%RAX

  (930) 0x450bc2 MOVQ	$0,0x10(%RSP)

  (930) 0x450bcb JMP	450c47

    (931) 0x450c00 MOV	0x40(%RSP),%RDI

    (931) 0x450c05 MOV	%RAX,%R8

    (931) 0x450c08 MOV	0x28(%RSP),%RAX

    (931) 0x450c0d ADD	%RDI,%RAX

    (931) 0x450c10 ADD	%RDI,%R12

    (931) 0x450c13 ADD	%RDI,%R15

    (931) 0x450c16 MOV	0x20(%RSP),%R13

    (931) 0x450c1b ADD	%RDI,%R13

    (931) 0x450c1e ADD	%RDI,%R10

    (931) 0x450c21 ADD	%RDI,%R11

    (931) 0x450c24 ADD	%RDI,%R8

    (931) 0x450c27 MOV	%R8,0x8(%RSP)

    (931) 0x450c2c ADD	%RDI,%RSI

    (931) 0x450c2f MOV	0x10(%RSP),%RDI

    (931) 0x450c34 CMP	$0x3,%RDI

    (931) 0x450c38 LEA	0x1(%RDI),%RDI

    (931) 0x450c3c MOV	%RDI,0x10(%RSP)

    (931) 0x450c41 JE	450ac0

    (931) 0x450c47 MOV	%RAX,0x28(%RSP)

    (931) 0x450c4c MOV	%R13,0x20(%RSP)

    (931) 0x450c51 CMPL	$0,0x60(%RSP)

    (931) 0x450c56 MOV	0x8(%RSP),%RAX

    (931) 0x450c5b JLE	450c00

    (931) 0x450c5d MOV	0x10(%RSP),%RDI

    (931) 0x450c62 VMOVSD	0x2c0(%RSP,%RDI,8),%XMM8

    (931) 0x450c6b VMULSD	0x120(%RSP),%XMM8,%XMM23

    (931) 0x450c73 VMOVSD	0x118(%RSP),%XMM9

    (931) 0x450c7c VMULSD	%XMM9,%XMM8,%XMM20

    (931) 0x450c82 VMOVSD	0x110(%RSP),%XMM10

    (931) 0x450c8b VMULSD	%XMM10,%XMM8,%XMM24

    (931) 0x450c91 VMOVSD	0x140(%RSP,%RDI,8),%XMM8

    (931) 0x450c9a VMULSD	%XMM9,%XMM8,%XMM29

    (931) 0x450ca0 VMULSD	%XMM10,%XMM8,%XMM30

    (931) 0x450ca6 VMULSD	0x280(%RSP,%RDI,8),%XMM10,%XMM31

    (931) 0x450cae MOV	0x68(%RSP),%R8

    (931) 0x450cb3 TEST	%R8,%R8

    (931) 0x450cb6 JE	450f40

    (931) 0x450cbc MOV	%RSI,0x128(%RSP)

    (931) 0x450cc4 VMOVAPD	%YMM26,%YMM0

    (931) 0x450cca VBROADCASTSD	%XMM23,%YMM26

    (931) 0x450cd0 VMOVAPD	%YMM28,%YMM3

    (931) 0x450cd6 VBROADCASTSD	%XMM29,%YMM28

    (931) 0x450cdc VMOVAPD	%YMM25,%YMM1

    (931) 0x450ce2 VMOVAPD	%YMM18,%YMM25

    (931) 0x450ce8 VMOVAPD	%YMM19,%YMM18

    (931) 0x450cee VBROADCASTSD	%XMM20,%YMM19

    (931) 0x450cf4 VMOVAPD	%YMM27,%YMM2

    (931) 0x450cfa VMOVAPD	%YMM22,%YMM27

    (931) 0x450d00 VBROADCASTSD	%XMM31,%YMM22

    (931) 0x450d06 VBROADCASTSD	%XMM30,%YMM16

    (931) 0x450d0c VBROADCASTSD	%XMM24,%YMM8

    (931) 0x450d12 XOR	%R13D,%R13D

    (931) 0x450d15 MOV	0x18(%RSP),%RDI

    (931) 0x450d1a VMOVUPD	0x380(%RSP),%YMM4

    (931) 0x450d23 VMOVUPD	0x360(%RSP),%YMM5

    (931) 0x450d2c VMOVUPD	0x340(%RSP),%YMM6

    (931) 0x450d35 VMOVUPD	0x320(%RSP),%YMM7

    (931) 0x450d3e MOV	%R12,%RSI

    (931) 0x450d41 MOV	%R15,%R12

    (931) 0x450d44 MOV	0x20(%RSP),%R15

    (931) 0x450d49 MOV	0x28(%RSP),%RAX

    (931) 0x450d4e XCHG	%AX,%AX

      (933) 0x450d50 VMOVUPD	(%R15,%R13,8),%YMM10

      (933) 0x450d56 VMOVUPD	(%R12,%R13,8),%YMM11

      (933) 0x450d5c VMOVUPD	(%RSI,%R13,8),%YMM12

      (933) 0x450d62 VMOVUPD	(%RAX,%R13,8),%YMM13

      (933) 0x450d68 VMULPD	%YMM18,%YMM10,%YMM9

      (933) 0x450d6e VFMADD231PD	%YMM25,%YMM11,%YMM9

      (933) 0x450d74 VFMADD231PD	%YMM27,%YMM12,%YMM9

      (933) 0x450d7a VFMADD231PD	%YMM13,%YMM1,%YMM9

      (933) 0x450d7f VMULPD	%YMM0,%YMM10,%YMM14

      (933) 0x450d83 VMULPD	%YMM2,%YMM11,%YMM15

      (933) 0x450d87 VFMADD231PD	%YMM4,%YMM13,%YMM15

      (933) 0x450d8c VFMADD231PD	%YMM3,%YMM12,%YMM14

      (933) 0x450d91 VFMADD231PD	%YMM15,%YMM17,%YMM14

      (933) 0x450d97 LEA	(%RBX,%R13,8),%R8

      (933) 0x450d9b VMOVUPD	(%RBX,%R13,8),%YMM15

      (933) 0x450da1 VFMADD231PD	%YMM9,%YMM26,%YMM15

      (933) 0x450da7 VMOVUPD	%YMM15,(%RBX,%R13,8)

      (933) 0x450dad VMOVUPD	(%R9,%R8,1),%YMM15

      (933) 0x450db3 VFMADD231PD	%YMM9,%YMM28,%YMM15

      (933) 0x450db9 VMOVUPD	%YMM15,(%R9,%R8,1)

      (933) 0x450dbf VMULPD	%YMM5,%YMM10,%YMM10

      (933) 0x450dc3 LEA	(%R8,%R9,1),%R8

      (933) 0x450dc7 VMOVUPD	(%R9,%R8,1),%YMM15

      (933) 0x450dcd VFMADD231PD	%YMM19,%YMM14,%YMM15

      (933) 0x450dd3 VMOVUPD	%YMM15,(%R9,%R8,1)

      (933) 0x450dd9 VFMADD231PD	%YMM11,%YMM6,%YMM10

      (933) 0x450dde LEA	(%R8,%R9,1),%R8

      (933) 0x450de2 VMOVUPD	(%R9,%R8,1),%YMM11

      (933) 0x450de8 VFMADD231PD	%YMM9,%YMM22,%YMM11

      (933) 0x450dee VMOVUPD	%YMM11,(%R9,%R8,1)

      (933) 0x450df4 VFMADD231PD	%YMM12,%YMM7,%YMM10

      (933) 0x450df9 LEA	(%R8,%R9,1),%R8

      (933) 0x450dfd VMOVUPD	(%R9,%R8,1),%YMM11

      (933) 0x450e03 VFMADD231PD	%YMM16,%YMM14,%YMM11

      (933) 0x450e09 VMOVUPD	%YMM11,(%R9,%R8,1)

      (933) 0x450e0f VFMADD231PD	%YMM13,%YMM17,%YMM10

      (933) 0x450e15 LEA	(%R8,%R9,1),%R8

      (933) 0x450e19 VFMADD213PD	(%R9,%R8,1),%YMM8,%YMM10

      (933) 0x450e1f VMOVUPD	%YMM10,(%R9,%R8,1)

      (933) 0x450e25 MOV	0x68(%RSP),%R8

      (933) 0x450e2a VMOVUPD	(%RDI,%R13,8),%YMM10

      (933) 0x450e30 VFMADD231PD	%YMM19,%YMM9,%YMM10

      (933) 0x450e36 VMOVUPD	%YMM10,(%RDI,%R13,8)

      (933) 0x450e3c VMOVUPD	(%RDX,%R13,8),%YMM10

      (933) 0x450e42 VFMADD231PD	%YMM16,%YMM9,%YMM10

      (933) 0x450e48 VMOVUPD	%YMM10,(%RDX,%R13,8)

      (933) 0x450e4e VFMADD213PD	(%RCX,%R13,8),%YMM8,%YMM14

      (933) 0x450e54 VMOVUPD	%YMM14,(%RCX,%R13,8)

      (933) 0x450e5a VFMADD213PD	(%R14,%R13,8),%YMM8,%YMM9

      (933) 0x450e60 VMOVUPD	%YMM9,(%R14,%R13,8)

      (933) 0x450e66 ADD	$0x4,%R13

      (933) 0x450e6a CMP	%R8,%R13

      (933) 0x450e6d JB	450d50

    (931) 0x450e73 MOV	%R8,%R13

    (931) 0x450e76 MOV	%R8,%RAX

    (931) 0x450e79 MOV	0x30(%RSP),%R8

    (931) 0x450e7e CMP	%R8D,%EAX

    (931) 0x450e81 VMOVUPD	0x130(%RSP),%XMM15

    (931) 0x450e8a VMOVUPD	0x300(%RSP),%YMM16

    (931) 0x450e92 VMOVAPD	%YMM18,%YMM19

    (931) 0x450e98 VMOVAPD	%YMM25,%YMM18

    (931) 0x450e9e VMOVAPD	%YMM27,%YMM22

    (931) 0x450ea4 VMOVAPD	%YMM1,%YMM25

    (931) 0x450eaa VMOVUPD	0x270(%RSP),%XMM1

    (931) 0x450eb3 VMOVAPD	%YMM0,%YMM26

    (931) 0x450eb9 VMOVUPD	0x260(%RSP),%XMM0

    (931) 0x450ec2 VMOVAPD	%YMM2,%YMM27

    (931) 0x450ec8 VMOVUPD	0x250(%RSP),%XMM2

    (931) 0x450ed1 VMOVAPD	%YMM3,%YMM28

    (931) 0x450ed7 VMOVUPD	0x240(%RSP),%XMM3

    (931) 0x450ee0 VMOVUPD	0x230(%RSP),%XMM4

    (931) 0x450ee9 VMOVUPD	0x220(%RSP),%XMM5

    (931) 0x450ef2 VMOVUPD	0x210(%RSP),%XMM6

    (931) 0x450efb VMOVUPD	0x200(%RSP),%XMM7

    (931) 0x450f04 MOV	%R12,%R15

    (931) 0x450f07 MOV	%RSI,%R12

    (931) 0x450f0a MOV	0x128(%RSP),%RSI

    (931) 0x450f12 MOV	0x8(%RSP),%RAX

    (931) 0x450f17 JNE	450f50

    (931) 0x450f19 JMP	450c00

    (931) 0x450f40 XOR	%R13D,%R13D

    (931) 0x450f43 MOV	0x18(%RSP),%RDI

    (931) 0x450f48 NOPL	(%RAX,%RAX,1)

      (932) 0x450f50 VMOVSD	(%RSI,%R13,8),%XMM8

      (932) 0x450f56 VMOVSD	(%RAX,%R13,8),%XMM9

      (932) 0x450f5c VMOVSD	(%R11,%R13,8),%XMM10

      (932) 0x450f62 VMOVSD	(%R10,%R13,8),%XMM11

      (932) 0x450f68 VPUNPCKLQDQ	%XMM10,%XMM9,%XMM12

      (932) 0x450f6d VMULPD	%XMM16,%XMM12,%XMM12

      (932) 0x450f73 VMOVAPD	%XMM0,%XMM13

      (932) 0x450f77 VFMADD213SD	%XMM12,%XMM8,%XMM13

      (932) 0x450f7c VSHUFPD	$0x1,%XMM12,%XMM12,%XMM12

      (932) 0x450f82 VADDSD	%XMM12,%XMM13,%XMM12

      (932) 0x450f87 VFMADD231SD	%XMM11,%XMM7,%XMM12

      (932) 0x450f8c VMULSD	%XMM1,%XMM8,%XMM13

      (932) 0x450f90 VMULSD	%XMM2,%XMM9,%XMM14

      (932) 0x450f94 VFMADD231SD	%XMM15,%XMM11,%XMM14

      (932) 0x450f99 VFMADD231SD	%XMM3,%XMM10,%XMM13

      (932) 0x450f9e VFMADD231SD	%XMM14,%XMM21,%XMM13

      (932) 0x450fa4 LEA	(%RBX,%R13,8),%R8

      (932) 0x450fa8 VMOVSD	(%RBX,%R13,8),%XMM14

      (932) 0x450fae VFMADD231SD	%XMM12,%XMM23,%XMM14

      (932) 0x450fb4 VMOVSD	%XMM14,(%RBX,%R13,8)

      (932) 0x450fba VMOVSD	(%R9,%R8,1),%XMM14

      (932) 0x450fc0 VFMADD231SD	%XMM12,%XMM29,%XMM14

      (932) 0x450fc6 VMOVSD	%XMM14,(%R9,%R8,1)

      (932) 0x450fcc VMULSD	%XMM4,%XMM8,%XMM8

      (932) 0x450fd0 LEA	(%R8,%R9,1),%R8

      (932) 0x450fd4 VMOVSD	(%R9,%R8,1),%XMM14

      (932) 0x450fda VFMADD231SD	%XMM20,%XMM13,%XMM14

      (932) 0x450fe0 VMOVSD	%XMM14,(%R9,%R8,1)

      (932) 0x450fe6 VFMADD231SD	%XMM9,%XMM5,%XMM8

      (932) 0x450feb LEA	(%R8,%R9,1),%R8

      (932) 0x450fef VMOVSD	(%R9,%R8,1),%XMM9

      (932) 0x450ff5 VFMADD231SD	%XMM12,%XMM31,%XMM9

      (932) 0x450ffb VMOVSD	%XMM9,(%R9,%R8,1)

      (932) 0x451001 VFMADD231SD	%XMM10,%XMM6,%XMM8

      (932) 0x451006 LEA	(%R8,%R9,1),%R8

      (932) 0x45100a VMOVSD	(%R9,%R8,1),%XMM9

      (932) 0x451010 VFMADD231SD	%XMM30,%XMM13,%XMM9

      (932) 0x451016 VMOVSD	%XMM9,(%R9,%R8,1)

      (932) 0x45101c VFMADD231SD	%XMM11,%XMM21,%XMM8

      (932) 0x451022 LEA	(%R8,%R9,1),%R8

      (932) 0x451026 VFMADD213SD	(%R9,%R8,1),%XMM24,%XMM8

      (932) 0x45102d VMOVSD	%XMM8,(%R9,%R8,1)

      (932) 0x451033 VMOVSD	(%RDI,%R13,8),%XMM8

      (932) 0x451039 VFMADD231SD	%XMM20,%XMM12,%XMM8

      (932) 0x45103f VMOVSD	%XMM8,(%RDI,%R13,8)

      (932) 0x451045 VMOVSD	(%RDX,%R13,8),%XMM8

      (932) 0x45104b VFMADD231SD	%XMM30,%XMM12,%XMM8

      (932) 0x451051 VMOVSD	%XMM8,(%RDX,%R13,8)

      (932) 0x451057 VFMADD213SD	(%RCX,%R13,8),%XMM24,%XMM13

      (932) 0x45105e VMOVSD	%XMM13,(%RCX,%R13,8)

      (932) 0x451064 VFMADD213SD	(%R14,%R13,8),%XMM24,%XMM12

      (932) 0x45106b VMOVSD	%XMM12,(%R14,%R13,8)

      (932) 0x451071 INC	%R13

      (932) 0x451074 MOV	0x30(%RSP),%R8

      (932) 0x451079 CMP	%R13,%R8

      (932) 0x45107c JNE	450f50

    (931) 0x451082 JMP	450c00

0x4510c0 MOV	0x60(%RSP),%R11

0x4510c5 TEST	%R11D,%R11D

0x4510c8 MOV	0xa8(%RSP),%R13

0x4510d0 MOV	0x58(%RSP),%R14

0x4510d5 MOV	0x78(%RSP),%R10

0x4510da VMOVSD	0xe8d4c(%RIP),%XMM16

0x4510e4 VMOVSD	0xe5f32(%RIP),%XMM22

0x4510ee VMOVSD	0xe5f40(%RIP),%XMM23

0x4510f8 VMOVSD	0xe5f3e(%RIP),%XMM24

0x451102 VMOVSD	0xe8d34(%RIP),%XMM26

0x45110c VMOVSD	0xe5f6a(%RIP),%XMM27

0x451116 VMOVSD	0xe70d8(%RIP),%XMM28

0x451120 MOV	0x18(%RSP),%R15

0x451125 VMOVUPD	0x1f0(%RSP),%XMM17

0x45112d VMOVUPD	0x1e0(%RSP),%XMM18

0x451135 VMOVUPD	0x1d0(%RSP),%XMM19

0x45113d MOV	0x50(%RSP),%R12

0x451142 JE	450380

0x451148 VMULSD	%XMM17,%XMM17,%XMM0

0x45114e VMULSD	%XMM18,%XMM18,%XMM1

0x451154 VMULSD	%XMM19,%XMM19,%XMM2

0x45115a VMULSD	%XMM17,%XMM18,%XMM3

0x451160 VMULSD	%XMM17,%XMM19,%XMM4

0x451166 VMULSD	%XMM18,%XMM19,%XMM5

0x45116c TEST	%R10,%R10

0x45116f JE	451280

0x451175 VBROADCASTSD	%XMM17,%YMM6

0x45117b VBROADCASTSD	%XMM18,%YMM7

0x451181 VBROADCASTSD	%XMM19,%YMM8

0x451187 VBROADCASTSD	%XMM0,%YMM9

0x45118c VBROADCASTSD	%XMM1,%YMM10

0x451191 VBROADCASTSD	%XMM2,%YMM11

0x451196 VBROADCASTSD	%XMM3,%YMM12

0x45119b VBROADCASTSD	%XMM4,%YMM13

0x4511a0 VBROADCASTSD	%XMM5,%YMM14

0x4511a5 MOV	(%RSP),%R9

0x4511a9 MOV	%R9,%RAX

0x4511ac SAL	$0x5,%RAX

0x4511b0 ADD	%RBX,%RAX

0x4511b3 LEA	(%R9,%R9,4),%RSI

0x4511b7 LEA	(%RBX,%RSI,8),%RSI

0x4511bb LEA	(%R9,%R9,2),%RDI

0x4511bf LEA	(%RBX,%RDI,8),%RDI

0x4511c3 LEA	(%RBX,%R12,1),%R8

0x4511c7 LEA	(%RBX,%R9,8),%R9

0x4511cb MOV	%R10,%R12

0x4511ce XOR	%R10D,%R10D

0x4511d1 NOPW	%CS:(%RAX,%RAX,1)

  (929) 0x4511e0 VMULPD	(%R15,%R10,8),%YMM6,%YMM15

  (929) 0x4511e6 VMOVUPD	%YMM15,(%R15,%R10,8)

  (929) 0x4511ec VMULPD	(%RDX,%R10,8),%YMM7,%YMM15

  (929) 0x4511f2 VMOVUPD	%YMM15,(%RDX,%R10,8)

  (929) 0x4511f8 VMULPD	(%RCX,%R10,8),%YMM8,%YMM15

  (929) 0x4511fe VMOVUPD	%YMM15,(%RCX,%R10,8)

  (929) 0x451204 VMULPD	(%RBX,%R10,8),%YMM9,%YMM15

  (929) 0x45120a VMOVUPD	%YMM15,(%RBX,%R10,8)

  (929) 0x451210 VMULPD	(%RDI,%R10,8),%YMM10,%YMM15

  (929) 0x451216 VMOVUPD	%YMM15,(%RDI,%R10,8)

  (929) 0x45121c VMULPD	(%RSI,%R10,8),%YMM11,%YMM15

  (929) 0x451222 VMOVUPD	%YMM15,(%RSI,%R10,8)

  (929) 0x451228 VMULPD	(%R9,%R10,8),%YMM12,%YMM15

  (929) 0x45122e VMOVUPD	%YMM15,(%R9,%R10,8)

  (929) 0x451234 VMULPD	(%R8,%R10,8),%YMM13,%YMM15

  (929) 0x45123a VMOVUPD	%YMM15,(%R8,%R10,8)

  (929) 0x451240 VMULPD	(%RAX,%R10,8),%YMM14,%YMM15

  (929) 0x451246 VMOVUPD	%YMM15,(%RAX,%R10,8)

  (929) 0x45124c ADD	$0x4,%R10

  (929) 0x451250 CMP	%R12,%R10

  (929) 0x451253 JL	4511e0

0x451255 MOV	%R12,%RAX

0x451258 CMP	%R11,%R12

0x45125b MOV	0x50(%RSP),%R12

0x451260 JE	450380

0x451266 JMP	451282

0x451280 XOR	%EAX,%EAX

0x451282 MOV	(%RSP),%R9

0x451286 MOV	%R9,%RSI

0x451289 SAL	$0x5,%RSI

0x45128d ADD	%RBX,%RSI

0x451290 LEA	(%R9,%R9,4),%RDI

0x451294 LEA	(%RBX,%RDI,8),%RDI

0x451298 LEA	(%R9,%R9,2),%R8

0x45129c LEA	(%RBX,%R8,8),%R8

0x4512a0 ADD	%RBX,%R12

0x4512a3 LEA	(%RBX,%R9,8),%R9

0x4512a7 NOPW	(%RAX,%RAX,1)

  (928) 0x4512b0 VMULSD	(%R15,%RAX,8),%XMM17,%XMM6

  (928) 0x4512b7 VMOVSD	%XMM6,(%R15,%RAX,8)

  (928) 0x4512bd VMULSD	(%RDX,%RAX,8),%XMM18,%XMM6

  (928) 0x4512c4 VMOVSD	%XMM6,(%RDX,%RAX,8)

  (928) 0x4512c9 VMULSD	(%RCX,%RAX,8),%XMM19,%XMM6

  (928) 0x4512d0 VMOVSD	%XMM6,(%RCX,%RAX,8)

  (928) 0x4512d5 VMULSD	(%RBX,%RAX,8),%XMM0,%XMM6

  (928) 0x4512da VMOVSD	%XMM6,(%RBX,%RAX,8)

  (928) 0x4512df VMULSD	(%R8,%RAX,8),%XMM1,%XMM6

  (928) 0x4512e5 VMOVSD	%XMM6,(%R8,%RAX,8)

  (928) 0x4512eb VMULSD	(%RDI,%RAX,8),%XMM2,%XMM6

  (928) 0x4512f0 VMOVSD	%XMM6,(%RDI,%RAX,8)

  (928) 0x4512f5 VMULSD	(%R9,%RAX,8),%XMM3,%XMM6

  (928) 0x4512fb VMOVSD	%XMM6,(%R9,%RAX,8)

  (928) 0x451301 VMULSD	(%R12,%RAX,8),%XMM4,%XMM6

  (928) 0x451307 VMOVSD	%XMM6,(%R12,%RAX,8)

  (928) 0x45130d VMULSD	(%RSI,%RAX,8),%XMM5,%XMM6

  (928) 0x451312 VMOVSD	%XMM6,(%RSI,%RAX,8)

  (928) 0x451317 INC	%RAX

  (928) 0x45131a CMP	%RAX,%R11

  (928) 0x45131d JNE	4512b0

0x45131f JMP	450380

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 265 - 265

--------------------------------------------------------------------------------

265:   inline T* data() { return myData; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 206 - 207

--------------------------------------------------------------------------------

206:     for (int i = 0; i < nBlocks; ++i)

207:       MultiBsplineEvalRef::evaluate_vgh(einsplines[i], u[0], u[1], u[2], psi[i].data(), grad[i].data(), hess[i].data(),

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 924

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 61 - 61

--------------------------------------------------------------------------------

61:     for (size_t d = 0; d < D; ++d)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 45 - 47

--------------------------------------------------------------------------------

45:   T sf = std::floor(x);

46:   T dx2 = x - sf;

47:   int ind2 = std::min(std::max(0, static_cast<int>(sf)), nmax);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 68 - 79

--------------------------------------------------------------------------------

68:     a[0]   = ((A00 * tx + A01) * tx + A02) * tx + A03;

69:     a[1]   = ((A10 * tx + A11) * tx + A12) * tx + A13;

70:     a[2]   = ((A20 * tx + A21) * tx + A22) * tx + A23;

71:     a[3]   = ((A30 * tx + A31) * tx + A32) * tx + A33;

72:     da[0]  = (dA01 * tx + dA02) * tx + dA03;

73:     da[1]  = (dA11 * tx + dA12) * tx + dA13;

74:     da[2]  = (dA21 * tx + dA22) * tx + dA23;

75:     da[3]  = (dA31 * tx + dA32) * tx + dA33;

76:     d2a[0] = d2A02 * tx + d2A03;

77:     d2a[1] = d2A12 * tx + d2A13;

78:     d2a[2] = d2A22 * tx + d2A23;

79:     d2a[3] = d2A32 * tx + d2A33;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 187 - 286

--------------------------------------------------------------------------------

187:   x -= spline_m->x_grid.start;

188:   y -= spline_m->y_grid.start;

189:   z -= spline_m->z_grid.start;

190:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

191:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

192:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

198:   const intptr_t xs = spline_m->x_stride;

199:   const intptr_t ys = spline_m->y_stride;

200:   const intptr_t zs = spline_m->z_stride;

201:

202:   const size_t out_offset = spline_m->num_splines;

[...]

226:   for (int i = 0; i < 4; i++)

227:     for (int j = 0; j < 4; j++)

228:     {

229:       const T* restrict coefs    = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

230:       const T* restrict coefszs  = coefs + zs;

231:       const T* restrict coefs2zs = coefs + 2 * zs;

232:       const T* restrict coefs3zs = coefs + 3 * zs;

233:

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

[...]

269:   const T dxx   = dxInv * dxInv;

270:   const T dyy   = dyInv * dyInv;

271:   const T dzz   = dzInv * dzInv;

272:   const T dxy   = dxInv * dyInv;

273:   const T dxz   = dxInv * dzInv;

274:   const T dyz   = dyInv * dzInv;

275:

276:   for (int n = 0; n < num_splines; n++)

277:   {

278:     gx[n] *= dxInv;

279:     gy[n] *= dyInv;

280:     gz[n] *= dzInv;

281:     hxx[n] *= dxx;

282:     hyy[n] *= dyy;

283:     hzz[n] *= dzz;

284:     hxy[n] *= dxy;

285:     hxz[n] *= dxz;

286:     hyz[n] *= dyz;

Coverage (%)	Name	Source Location	Module
►97.67+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►1.40+	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.extracted.112	miniqmc.cpp:397	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.61
CQA speedup if FP arith vectorized	2.40
CQA speedup if fully vectorized	8.74
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	micro-operation queue,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	VectorSoAContainer.h:265-265,einspline_spo_ref.hpp:206-207,stl_vector.h:1046-1046,stl_vector.h:1169-1169,stl_algobase.h:923-924,TinyVector.h:61-61,MultiBsplineEvalHelper.hpp:45-47,MultiBsplineData.hpp:68-79,MultiBsplineRef.hpp:187-192,MultiBsplineRef.hpp:198-202,MultiBsplineRef.hpp:229-229,MultiBsplineRef.hpp:242-244,MultiBsplineRef.hpp:249-251,MultiBsplineRef.hpp:269-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	71.67
CQA cycles if no scalar integer	44.50
CQA cycles if FP arith vectorized	29.86
CQA cycles if fully vectorized	8.20
Front-end cycles	71.67
P0 cycles	48.00
P1 cycles	48.17
P2 cycles	26.33
P3 cycles	26.33
P4 cycles	31.50
P5 cycles	47.83
P6 cycles	24.40
P7 cycles	31.50
P8 cycles	31.50
P9 cycles	31.50
P10 cycles	24.60
P11 cycles	26.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	413.00
Nb uops	430.00
Nb loads	79.00
Nb stores	53.00
Nb stack references	64.00
FLOP/cycle	1.52
Nb FLOP add-sub	36.00
Nb FLOP mul	37.00
Nb FLOP fma	18.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.76
Bytes prefetched	0.00
Bytes loaded	744.00
Bytes stored	672.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.68
Vectorization ratio load	40.00
Vectorization ratio store	39.62
Vectorization ratio mul	8.33
Vectorization ratio add_sub	8.11
Vectorization ratio fma	20.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.69
Vector-efficiency ratio all	16.20
Vector-efficiency ratio load	18.21
Vector-efficiency ratio store	19.81
Vector-efficiency ratio mul	13.54
Vector-efficiency ratio add_sub	13.51
Vector-efficiency ratio fma	15.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.41

Metric	Value
CQA speedup if no scalar integer	1.61
CQA speedup if FP arith vectorized	2.40
CQA speedup if fully vectorized	8.74
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	micro-operation queue,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	VectorSoAContainer.h:265-265,einspline_spo_ref.hpp:206-207,stl_vector.h:1046-1046,stl_vector.h:1169-1169,stl_algobase.h:923-924,TinyVector.h:61-61,MultiBsplineEvalHelper.hpp:45-47,MultiBsplineData.hpp:68-79,MultiBsplineRef.hpp:187-192,MultiBsplineRef.hpp:198-202,MultiBsplineRef.hpp:229-229,MultiBsplineRef.hpp:242-244,MultiBsplineRef.hpp:249-251,MultiBsplineRef.hpp:269-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	71.67
CQA cycles if no scalar integer	44.50
CQA cycles if FP arith vectorized	29.86
CQA cycles if fully vectorized	8.20
Front-end cycles	71.67
P0 cycles	48.00
P1 cycles	48.17
P2 cycles	26.33
P3 cycles	26.33
P4 cycles	31.50
P5 cycles	47.83
P6 cycles	24.40
P7 cycles	31.50
P8 cycles	31.50
P9 cycles	31.50
P10 cycles	24.60
P11 cycles	26.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	413.00
Nb uops	430.00
Nb loads	79.00
Nb stores	53.00
Nb stack references	64.00
FLOP/cycle	1.52
Nb FLOP add-sub	36.00
Nb FLOP mul	37.00
Nb FLOP fma	18.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.76
Bytes prefetched	0.00
Bytes loaded	744.00
Bytes stored	672.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.68
Vectorization ratio load	40.00
Vectorization ratio store	39.62
Vectorization ratio mul	8.33
Vectorization ratio add_sub	8.11
Vectorization ratio fma	20.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.69
Vector-efficiency ratio all	16.20
Vector-efficiency ratio load	18.21
Vector-efficiency ratio store	19.81
Vector-efficiency ratio mul	13.54
Vector-efficiency ratio add_sub	13.51
Vector-efficiency ratio fma	15.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:187-286
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:265
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:206-207
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,198-202,226-262,269-286

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=32
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 32 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 71.67 to 44.50 cycles (1.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
39% of SSE/AVX stores are used in vector version.
8% of SSE/AVX addition or subtraction instructions are used in vector version.
8% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX fused multiply-add instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__intel_avx_rep_memset: 10 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Vector unaligned load/store instructions

Detected 6 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:69
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:249
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:250
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

76 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 109 FP arithmetical operations:

54: addition or subtraction (18 inside FMA instructions)
55: multiply (18 inside FMA instructions)

The binary loop is loading 744 bytes (93 double precision FP elements). The binary loop is storing 672 bytes (84 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	413
nb uops	430
loop length	2181
used x86 registers	15
used mmx registers	0
used xmm registers	26
used ymm registers	21
used zmm registers	0
nb stack references	64
ADD-SUB / MUL ratio	0.97

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	71.67 cycles
front end	71.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	48.00	48.17	26.33	26.33	31.50	47.83	24.40	31.50	31.50	31.50	24.60	26.33
cycles	48.00	48.17	26.33	26.33	31.50	47.83	24.40	31.50	31.50	31.50	24.60	26.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	71.67
Dispatch	48.17
Overall L1	71.67

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	28%
load	50%
store	56%
mul	8%
add-sub	9%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	40%
store	39%
mul	8%
add-sub	8%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	19%
store	22%
mul	13%
add-sub	13%
fma	15%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	16%
load	18%
store	19%
mul	13%
add-sub	13%
fma	15%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 71.67 cycles. At this rate:

5% of peak load performance is reached (10.38 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 71.67 to 48.17 cycles (1.49x speedup).

ASM code

In the binary file, the address of the loop is: 4503a7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xc0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x48(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xb8(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xb0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 451340 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xa0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RDX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD 0x1c0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x28(%R10),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x50(%R10),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVUPD 0x1a0(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x78(%R10),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x48(%R10),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70(%R10),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM3,0x1f0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM0,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x38(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM0,%XMM0,%XMM19	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM19,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD %XMM4,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x60(%R10),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD 0x98(%R10),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,0x1d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x88(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM0,%XMM0,%XMM20	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMULSD %XMM16,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM22,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM3,%XMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD 0x190(%RSP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBLENDPD $0x1,%XMM4,%XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM4,%XMM6,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD 0xe99ae(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDPD %XMM4,%XMM9,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM5,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVUPD 0xe99ae(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VFMADD213PD %XMM10,%XMM7,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM6,0x2e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM23,%XMM3,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM22,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM16,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,0x2f0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM5,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x2f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM24,%XMM6,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM26,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM2,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM5,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM24,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM4,%XMM4,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x178(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM28,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM3,%XMM24,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD 0x180(%RSP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDSD %XMM7,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM4,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM5,%XMM4,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM4,0x2a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM25,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM24,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x2b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,0x2b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM16,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM22,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM3,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM3,%XMM5,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPD %XMM3,%XMM9,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM4,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %XMM10,%XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM5,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM23,%XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM22,%XMM5,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM16,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,0x2d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x2d8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM24,%XMM5,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM26,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM2,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM4,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM20,%XMM0,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM24,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM0,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM3,%XMM3,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM0,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM28,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM1,%XMM24,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM3,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM2,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM0,%XMM24,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,0x290(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x298(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM21,%XMM21,%XMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM21,%XMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM22,%XMM18,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP 0xe6959(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM21,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMULPD %XMM0,%XMM1,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPD 0xe97c3(%RIP),%XMM15,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM1,%XMM17,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD 0xe97c4(%RIP),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %YMM1,0x300(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x10(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0xe8(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RAX,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM15,0x130(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JE 450805 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x705>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R12,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R12,%RAX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD %RBX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD 0x130(%RSP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VCVTTSD2SI %XMM19,%ECX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM25,%EDX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM20,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
MOV 0x20(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EAX,%ESI,%EAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RAX,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
DEC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EDX,%ESI,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RDX,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R13,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %ECX,%ESI,%ECX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV 0x38(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RSI,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R8,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R13,%RAX,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R9,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%RDI),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x2(%RDI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%RDI),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R11,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %R9,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %RDX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM16,%XMM21,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM22,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM21,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM16,%XMM21,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM24,%XMM18,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM21,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM26,%XMM21,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM24,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM21,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM21,%XMM24,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM28,%XMM21,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM6,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM24,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x8(%R10),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM17,%XMM7,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%YMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD 0x300(%RSP),%YMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSD %XMM16,%YMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPERMPD $0x55,%YMM16,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM11,%YMM25	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM2,%YMM27	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM15,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM4,0x380(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM21,%YMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM8,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM5,0x360(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM9,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM6,0x340(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM10,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM7,0x320(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM11,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R10,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x10(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RDX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RAX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD 0x20(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R10,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %R10,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %R10,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R8,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R10,%RSI,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R10,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM1,0x270(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM0,0x260(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM2,0x250(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM3,0x240(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM8,0x230(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM9,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM10,0x210(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM11,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 450b33 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xa33>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x60(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R11D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV 0xa8(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0xe8d4c(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f32(%RIP),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f40(%RIP),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f3e(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8d34(%RIP),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f6a(%RIP),%XMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe70d8(%RIP),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x1f0(%RSP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x1e0(%RSP),%XMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x1d0(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV 0x50(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 450380 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x280>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD %XMM17,%XMM17,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM18,%XMM18,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM19,%XMM19,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM17,%XMM18,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM17,%XMM19,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM18,%XMM19,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 451280 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VBROADCASTSD %XMM17,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM18,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM19,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM0,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM2,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x5,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R9,4),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R12,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R9,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x50(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 450380 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x280>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 451282 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1182>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R9,4),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RBX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%R9,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 450380 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x280>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:187-286
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:265
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:206-207
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,198-202,226-262,269-286

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=32
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
39% of SSE/AVX stores are used in vector version.
8% of SSE/AVX addition or subtraction instructions are used in vector version.
8% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX fused multiply-add instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

__intel_avx_rep_memset: 10 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Vector unaligned load/store instructions

Detected 6 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:69
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:249
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:250
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:47

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 109 FP arithmetical operations:

54: addition or subtraction (18 inside FMA instructions)
55: multiply (18 inside FMA instructions)

The binary loop is loading 744 bytes (93 double precision FP elements). The binary loop is storing 672 bytes (84 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	413
nb uops	430
loop length	2181
used x86 registers	15
used mmx registers	0
used xmm registers	26
used ymm registers	21
used zmm registers	0
nb stack references	64
ADD-SUB / MUL ratio	0.97

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	71.67 cycles
front end	71.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	48.00	48.17	26.33	26.33	31.50	47.83	24.40	31.50	31.50	31.50	24.60	26.33
cycles	48.00	48.17	26.33	26.33	31.50	47.83	24.40	31.50	31.50	31.50	24.60	26.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	71.67
Dispatch	48.17
Overall L1	71.67

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	28%
load	50%
store	56%
mul	8%
add-sub	9%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	40%
store	39%
mul	8%
add-sub	8%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	19%
store	22%
mul	13%
add-sub	13%
fma	15%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	16%
load	18%
store	19%
mul	13%
add-sub	13%
fma	15%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 71.67 cycles. At this rate:

5% of peak load performance is reached (10.38 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4503a7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xc0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x48(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xb8(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xb0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 451340 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xa0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RDX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD 0x1c0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x28(%R10),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX,%RAX,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x50(%R10),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVUPD 0x1a0(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBSD 0x78(%R10),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x48(%R10),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70(%R10),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM3,0x1f0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM0,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x38(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM0,%XMM0,%XMM19	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM19,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD %XMM4,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x60(%R10),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD 0x98(%R10),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,0x1d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x88(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM0,%XMM0,%XMM20	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMULSD %XMM16,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM22,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM3,%XMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD 0x190(%RSP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBLENDPD $0x1,%XMM4,%XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM4,%XMM6,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD 0xe99ae(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDPD %XMM4,%XMM9,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM5,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVUPD 0xe99ae(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VFMADD213PD %XMM10,%XMM7,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM6,0x2e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM23,%XMM3,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM22,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM16,%XMM3,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,0x2f0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM5,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x2f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM24,%XMM6,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM26,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM2,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM5,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM24,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM4,%XMM4,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x178(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM28,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM3,%XMM24,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVUPD 0x180(%RSP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDSD %XMM7,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM4,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM5,%XMM4,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM4,0x2a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM25,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM24,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x2b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,0x2b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM16,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM22,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM3,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULPD %XMM3,%XMM5,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPD %XMM3,%XMM9,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM4,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %XMM10,%XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM5,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD %XMM23,%XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM22,%XMM5,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM16,%XMM1,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,0x2d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x2d8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD %XMM24,%XMM5,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM26,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM2,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM4,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM20,%XMM0,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM24,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM0,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM3,%XMM3,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM0,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM28,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VSUBSD %XMM1,%XMM24,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBLENDPD $0x1,%XMM3,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVUPD %XMM2,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM0,%XMM24,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,0x290(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x298(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM21,%XMM21,%XMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM21,%XMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM22,%XMM18,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP 0xe6959(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM21,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMULPD %XMM0,%XMM1,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPD 0xe97c3(%RIP),%XMM15,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM1,%XMM17,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD 0xe97c4(%RIP),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %YMM1,0x300(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x10(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0xe8(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RAX,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM15,0x130(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JE 450805 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x705>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R12,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R12,%RAX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD %RBX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 534740 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD 0x130(%RSP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VCVTTSD2SI %XMM19,%ECX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM25,%EDX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM20,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
MOV 0x20(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EAX,%ESI,%EAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RAX,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
DEC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %EDX,%ESI,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RDX,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R13,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x1f,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %ECX,%ESI,%ECX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVGE %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV 0x38(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RSI,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R8,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R13,%RAX,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R9,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%RDI),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x2(%RDI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%RDI),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R11,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %R9,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %RDX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM16,%XMM21,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM22,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM21,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM16,%XMM21,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM24,%XMM18,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM23,%XMM21,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM26,%XMM21,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM24,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM22,%XMM21,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM21,%XMM24,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM28,%XMM21,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM6,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM24,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x8(%R10),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM17,%XMM7,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%YMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD 0x300(%RSP),%YMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSD %XMM16,%YMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPERMPD $0x55,%YMM16,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM11,%YMM25	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM2,%YMM27	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM28	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM15,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM4,0x380(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM21,%YMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM8,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM5,0x360(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM9,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM6,0x340(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VBROADCASTSD %XMM10,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVUPD %YMM7,0x320(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD %XMM11,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R10,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x10(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RDX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RAX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD 0x20(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R10,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %R10,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %R10,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R8,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R10,%RSI,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R10,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM1,0x270(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM0,0x260(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM2,0x250(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM3,0x240(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM8,0x230(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM9,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM10,0x210(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM11,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 450b33 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xa33>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x60(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R11D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV 0xa8(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0xe8d4c(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f32(%RIP),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f40(%RIP),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f3e(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8d34(%RIP),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe5f6a(%RIP),%XMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe70d8(%RIP),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x1f0(%RSP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x1e0(%RSP),%XMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x1d0(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV 0x50(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 450380 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x280>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD %XMM17,%XMM17,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM18,%XMM18,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM19,%XMM19,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM17,%XMM18,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM17,%XMM19,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM18,%XMM19,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 451280 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VBROADCASTSD %XMM17,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM18,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM19,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM0,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM2,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x5,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R9,4),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R12,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R9,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x50(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 450380 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x280>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 451282 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1182>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R9,4),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RBX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%R9,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 450380 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x280>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code